FIELD OF THE INVENTION
The invention relates generally to the formation of semiconductor devices and, more particularly, to reduced area storage node junction process for fabrication such a junction.
BACKGROUND OF THE INVENTION
Generally, integrated circuits are mass produced by forming many identical circuit patterns on a single silicon wafer, which is thereafter cut into many identical dies or “chips.” Integrated circuits, also commonly referred to as semiconductor devices, are made of various materials that may be electrically conductive, electrically nonconductive or electrically semiconductive. Silicon, in single crystal or polycrystalline form, is the most commonly used semiconductor material. Both forms of silicon can be made electrically conductive by adding impurities. The introduction of impurities into silicon is commonly referred to as doping. Silicon is typically doped with boron or phosphorus. Boron atoms have one less valence electron than silicon atoms. Therefore, if the silicon is doped with boron, then electron “holes” become the dominant charge carrier and the doped silicon is referred to as p-type silicon. By contrast, phosphorous atoms have one more valence electron than silicon atoms. If the silicon is doped with phosphorous, then electrons become the dominant charge carriers and the doped silicon is referred to as n-type silicon.
Dynamic Random Access Memory devices (DRAMs) comprise arrays of memory cells which contain two basic components—a field effect access transistor and a capacitor. Typically, one side of the transistor is connected to one side of the capacitor. This connection is made between a capacitor bottom electrode or “storage node” and an active area. The substrate areas in a DRAM in which electrical connections are made are generally referred to as active areas. Active areas consist of discrete specially doped regions in the surface of the silicon substrate which serve as electrical contact points (or “buried contacts”) as well as source/drain regions for the access transistor. The other side of the transistor and the transistor gate electrode are connected to external contacts—a bit line and a word line, respectively. The other side of the capacitor, the capacitor top electrode or “cell plate,” is connected to a reference voltage. Therefore, the formation of the DRAM memory cell comprises the formation of a transistor, a capacitor, a connection between the capacitor and the transistor, and contacts to external circuits.
The many advantages of the formation of smaller circuit components, so that more and more memory cells may be packed onto each chip, are well known. One such advantage of miniaturization of cell components, and the corresponding reduction in memory cell spacing, is that the operating voltages for the DRAM may be decreased. Thus, the cost to operate the device is reduced and its reliability and longevity is enhanced. Lower operating voltages, however, reduce the time within which each memory cell must be recharged or “refreshed” because less charge is stored on the cell. In DRAMs, the charge on each memory cell must be refreshed periodically because the cell loses or “leaks” charge through the junctions between areas within the silicon substrate having different doping/conductivity characteristics. If the cell is not refreshed before losing a threshold level of charge, then the cell will fail, i.e., lose the bit of information stored therein. And, if a cell fails, then the chip itself is defective and cannot be used. The rate at which charge is leaked through these junctions is an important factor in determining refresh time—the time within which each cell must be recharged. Consequently, it is advantageous to minimize junction leakage to increase refresh time and help compensate for the reductions in refresh time caused by lower operating voltages.
Improvements in refresh are also needed to compensate for increased packing densities. As more and more cells are packed onto each chip, more time is required to refresh all of the cells on the chip. Further, as cell size is reduced, the junction perimeter becomes a more dominant source of leakage and refresh loss mechanism. Since refresh time is controlled by the weakest cell, the average refresh for all cells must be increased to keep the weakest cell above the minimum threshold. There is, thus, a need to lessen or eliminate the effects of perimeter junction leakage and other loss mechanisms to enhance refresh.
SUMMARY OF THE INVENTION
The present invention is directed to an improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction, sometimes also referred to as the capacitor buried contact, in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. These factors will reduce junction leakage and enhance refresh.
Accordingly, these and other objects and advantages are achieved by a semiconductor device having a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to field isolation steps to create active areas bounded by a region of field oxide. The device includes an insulated gate electrode over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. In one preferred embodiment of the invented semiconductor device, the storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.
In another aspect of the invention, this structure is incorporated into a dynamic random access memory cell, which comprises:
a. an electrically insulated transistor gate electrode over a first conductivity type semiconductor substrate;
b. a first contact region for electrical connection to a bit line, the first contact region being defined in the substrate laterally adjacent to one side of the gate electrode;
c. a second contact region for electrical connection to a memory cell capacitor, the second contact region being defined in the substrate laterally adjacent to another side of the gate electrode and extending between the gate electrode and a region of field oxide, the second contact region having a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region, the first segment being thereby isolated from the field oxide region by the second segment, and the first segment being doped to a second conductivity type;
d. a capacitor storage node formed over the substrate in electrical contact with the first segment of the second contact region and in electrical isolation from the second segment of the second contact region;
e. a dielectric layer over the capacitor storage node; and
f. a capacitor cell plate over the dielectric layer.
The storage node is preferably isolated from the field oxide by means of an insulating layer interposed between the storage node and the second segment of the second contact region.
The invention also includes a process for fabricating a dynamic random access memory cell having an access transistor and a capacitor, both of which are formed on an active area of a semiconductor substrate. The active area is bounded by a region of field oxide and the capacitor is electrically connected to the access transistor through a buried contact formed in the active area. The basic process includes the single step of physically isolating the capacitor buried contact from the field oxide. In one version of the invented process, this isolation is incorporated into the fabrication of a DRAM memory cell according to the following steps:
a. providing an electrically insulated transistor gate electrode over a first conductivity type semiconductor substrate;
b. defining a first contact region for electrical connection to a bit line, the first contact region being defined in the substrate laterally adjacent to one side of the gate electrode;
c. defining a second contact region for electrical connection to a memory cell capacitor, the second contact region being defined in the substrate laterally adjacent to another side of the gate electrode and extending between the gate electrode and a region of field oxide, the second contact region having a first segment adjacent to the gate electrode and a second segment adjacent to the field oxide region, the first segment being electrically isolated from the field oxide region by the second segment;
d. implanting a second conductivity type dopant into the first contact region and into only the first segment of the second contact region;
e. depositing a layer of storage polysilicon over the substrate in contact with the first segment of the second contact region;
f. patterning and etching the layer of storage polysilicon to define a capacitor storage node;
g. depositing a dielectric layer over the capacitor storage node;
h. depositing a second layer polysilicon over the dielectric layer; and
i. patterning and etching the second layer of polysilicon to define a capacitor cell plate.
In one preferred embodiment of the fabrication process, the first and second segments are defined prior to depositing the storage polysilicon by forming a layer of insulating material over the entire contact region and then patterning and etching the insulating layer to expose only that portion of the contact region adjacent to the gate electrode, i.e, the first segment of the contact region. In this way, the area of the storage node junction is reduced to only a portion of the contact region and the junction is moved away and electrically isolated from the field oxide.
In conventional DRAM fabrication, the lightly doped drain implants (LDDs) would now be formed by vertically implanting n-type impurities into bit line contact region 28 and capacitor buried contact region 29 beneath the horizontal regions 30 a of first insulating layer 30. This implant is usually self aligned to and masked by the vertical regions 30 b of first insulating layer 30. By contrast, according to the present invention and as described below, the n-type LDD implant for the capacitor buried contact is made only into that portion of contact region 29 immediately adjacent to the access transistor gate. Referring now to FIG. 2, implant mask 32 is formed over the in process structure and patterned to expose (through first insulating layer 30) that portion of capacitor buried contact region 29 immediately adjacent to gate electrode 18. N-type impurities are vertically implanted into the unmasked substrate through the horizontal regions 30 a of first insulating layer 30 as indicated symbolically by arrows 36. This LDD implant will be self aligned to the vertical regions 30 b of first insulating layer 30. The preferred LDD n-type dopants are phosphorus, arsenic, antimony or a combination of these dopants. As is known to those skilled in the art, the type of dopant and the doping parameters for the LDD implant may be varied to obtain the desired storage node junction characteristics. For example, if phosphorus is used, the phosphorus is implanted at doses of approximately 1-5×1013 ions per square centimeter and an implantation energy in the range of 20 to 100 KeV. Implantation at these energy levels results in ion distribution depths of approximately 500-1000 angstroms. Optionally, p-type impurities, typically boron atoms, may be implanted into contact regions 28 and 29 prior to the n-type LDD implant. Boron ions are typically implanted at an energy level of approximately of 25-50 KeV, to a depth of approximately 1000 angstroms. The resulting doped p-type regions extend into the channel area between the source and drain for each access transistor. Although this boron halo implant may improve the transistor characteristic by reducing short channel effects such as Vt rollover, sub Vt slope, punch-through and the like, it is not preferred because it tends to increase storage node junction leakage.