US 20010003530 A1 Abstract A circuit is designed with a plurality of logic circuits (
370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix. Claims(40) 1. A plurality of logic circuits for producing an offset state matrix, each logic circuit comprising:
a first logic circuit coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix, the first logic circuit producing a multi-bit logical combination of corresponding bits of the respective row and the column; and a second logic circuit coupled to receive the multi-bit logical combination, the second logic circuit producing a respective element of the offset state matrix. 2. A plurality of logic circuits as in claim 1 3. A plurality of logic circuits as in claim 2 4. A plurality of logic circuits as in claim 3 5. A plurality of logic circuits as in claim 3 6. A circuit, comprising:
a series of matrix generator circuits, a first matrix generator circuit in the series coupled to receive an input state matrix, a last matrix generator circuit in the series arranged to produce an output state matrix, each matrix generator circuit of the series comprising: a matrix multiplication circuit coupled to receive a respective input matrix, the matrix multiplication circuit arranged to produce a product of the respective input matrix and a respective stored matrix; and a multiplex circuit coupled to receive the respective input matrix, the respective product and a respective count signal, the multiplex circuit selectively producing one of the respective input matrix and the respective product in response to the respective count signal. 7. A circuit as in claim 6 8. A circuit as in claim 7 9. A circuit as in claim 8 10. A circuit as in claim 9 11. A circuit as in claim 8 12. A circuit, comprising:
a first matrix generator circuit coupled to receive a first input state matrix and a count signal, the first matrix generator arranged to produce a first output state matrix having an offset from the input state matrix in response to the count signal; and a plurality of second matrix generator circuits coupled in series, a first in the series of second matrix generator circuits coupled to receive the first output state matrix, each second matrix generator circuit producing a respective output state matrix having a predetermined offset from a respective input state matrix. 13. A circuit as in claim 12 14. A circuit as in claim 13 15. A circuits as in claim 14 16. A circuit as in claim 12 17. A circuit as in claim 12 a series of matrix generator circuits, a first matrix generator circuit in the series coupled to receive the first input state matrix, a last matrix generator circuit in the series arranged to produce the first output state matrix, each matrix generator circuit of the series comprising: a matrix multiplication circuit coupled to receive a respective input matrix, the matrix multiplication circuit arranged to produce a product of the respective input matrix and a respective stored matrix; and a multiplex circuit coupled to receive the respective input matrix, the respective product and a respective count signal, the multiplex circuit selectively producing one of the respective input matrix and the respective product in response to the respective count signal. 18. A circuit as in claim 17 19. A circuit for a communication system, comprising:
a first series of matrix generator circuits, a first matrix generator circuit in the first series coupled to receive a first input state matrix, a last matrix generator circuit in the first series arranged to produce a first output state matrix; a second series of matrix generator circuits, a first matrix generator circuit in the second series coupled to receive a second input state matrix, a last matrix generator circuit in the second series arranged to produce a second output state matrix; and a logic circuit coupled to the last matrix generator circuit in each of the first and second series, the logic circuit arranged to produce a pseudorandom noise sequence in response to the first output state matrix and the second output state matrix. 20. A circuit as in claim 19 21. A circuit as in claim 20 22. A circuit as in claim 21 23. A circuit as in claim 22 24. A circuit as in claim 22 25. A method of generating a matrix, comprising the steps of:
generating a first matrix having a predetermined number of elements, the first matrix characterized by a first offset; generating a second matrix having the predetermined number of elements and different from the first matrix; combining elements from the first matrix with elements from the second matrix, thereby producing a third matrix having the predetermined number of elements; comparing the first offset with a predetermined value; and producing one of the first and third matrices in response to the step of comparing. 26. A method as in claim 25 27. A method as in claim 25 28. A method as in claim 25 29. A method as in claim 25 30. A method as in claim 29 31. A method as in claim 25 32. A method as in claim 31 33. A method as in claim 31 34. A method of producing a matrix, comprising the steps of:
applying a respective plurality of input matrices to a plurality of matrix multiplication circuits; applying a plurality of control signals to the plurality of matrix multiplication circuits, each control signal corresponding to a respective matrix multiplication circuit; producing a respective output matrix as a product of each respective input matrix and a respective predetermined matrix at each matrix multiplication circuit having a corresponding control signal of a first logic state; producing each respective input matrix as a respective output matrix at each matrix multiplication circuit having a corresponding control signal of a second logic state; and applying a plurality of the respective output matrices as the respective input matrices. 35. A method as in claim 34 36. A method as in claim 35 37. A method as in claim 34 38. A method as in claim 37 39. A method as in claim 34 40. A method as in claim 34 Description [0001] This application claims priority under 35 U.S.C. § 119(e)(1) of provisional application Ser. No. 60/114,346, filed Dec. 29, 1998. [0002] This invention relates to wideband code division multiple access (WCDMA) for a communication system and more particularly to a pseudorandom noise generator for generating a Long Code having an arbitrary delay. [0003] Present wideband code division multiple access (WCDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. Base stations in adjacent cells or transmit areas also have a unique pseudorandom noise (PN) code associated with transmitted data. This PN code or Long Code is typically generated by a Linear Feedback Shift Register (LFSR), also known as a Linear Sequence Shift Register, and enables mobile stations within the cell to distinguish between intended signals and interference signals from other base stations. Identification of a PN code requires the mobile station to correctly identify an arbitrary part of the received PN sequence. The identification is frequently accomplished by a sliding window comparison of a locally generated PN sequence with the received part of the PN sequence. The sliding window algorithm often requires the mobile station to efficiently calculate multiple offsets from the LFSR to match the received sequence. [0004] In another application of an LFSR, the base station typically generates a PN sequence for the forward link by a combination of one or more LFSRs 100, 120 as in FIG. 1. The mobile unit is also generates a PN sequence for the reverse link with LFSR circuits 200, 220 as in FIG. 2. This PN sequence is used for quadrature phase shift keyed (QPSK) reverse link transmission. This transmission requires that the PN sequence be arbitrarily shifted by the number of chips equivalent to 250 microseconds for transmitting the in-phase component and the quadrature component. This arbitrary shift may vary with data rate. [0005] Another application of an arbitrary offset LFSR arises for spreading and despreading transmitted signals as disclosed in U.S. Pat. No. 5,228,054 by Timothy I. Rueth and incorporated herein by reference. Rueth discloses an advantage of modulating each data bit at a constant chip rate for various transmit data rates. For example, a constant chip rate produces 128 chips for each bit at 9600 bits per second and 256 chips for each bit at 4800 bits per second. Thus, the chip rate may remain constant while the transmitted data rate may vary in response to rate information from a base station. Rueth further teaches that synchronization of base and mobile stations is simplified by inserting a zero in the PN sequence, thereby increasing the number of states from 2 [0006] These problems are resolved by a circuit designed with a plurality of logic circuits for producing an offset state matrix. The circuit includes a first logic circuit coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix. [0007] The present invention produces a state vector with an arbitrary offset from an initial state vector with minimal power and gate delay. Memory storage requirements for transition matrices are minimized. [0008] A more complete understanding of the invention may be gained by reading the subsequent detailed description with reference to the drawings wherein: [0009]FIG. 1 is a simplified block diagram of a linear feedback shift register of the prior art; [0010]FIG. 2 is a simplified block diagram of another linear feedback shift register of the prior art; [0011]FIG. 3A is a block diagram of a PN generator circuit of the present invention; [0012]FIG. 3B is a schematic diagram of an embodiment of a matrix multiplication circuit of FIG. 3A of the present invention; [0013]FIG. 4 is a block diagram of a state generator circuit of the present invention for producing a plurality of state matrices separated by a predetermined offset; [0014]FIG. 5 is a block diagram of another embodiment of a PN generator of the present invention; [0015]FIG. 6 is a schematic diagram of yet another embodiment of a PN generator of the present invention that may be used for truncated state or zero insertion sequences; [0016]FIG. 7A is a diagram of elements of a PN sequence generated by the circuit of FIG. 6; [0017]FIG. 7B is a diagram of a vector of an exemplary PN sequence generated by the circuit of FIG. 6; and [0018]FIG. 7C is a diagram of another vector of the exemplary PN sequence generated by the circuit of FIG. 6. [0019] Referring to FIG. 3A, there is a block diagram of a PN generator circuit of the present invention that may be used to generate an N-bit PN sequence corresponding to the LFSR 220 of FIG. 2. The N-stage PN generator circuit has [0020] In operation, the output state matrix S [0021] The state matrix S [0022] A transition matrix for producing an arbitrary offset n from initial state S [0023] Any transition matrix having an arbitrary n exponent, therefore, may be calculated by storing the matrices of equation [3] in memory circuits of matrix multiplication circuits 302, 312, 322 and 332. Any zero-value bit of the offset value, for example bit c [0024] This circuit is highly advantageous for efficiently producing a state vector having an arbitrary offset with respect to an initial state vector. Memory requirements are greatly reduced by storing only exponentially weighted matrices rather than the matrices for each desired offset. Moreover, computation time and power are minimized by use of combinatorial logic for modulo-2 matrix multiplication. [0025] Referring now to FIG. 3B, there is a matrix multiplication circuit of the present invention that may be used with the matrix generator circuits of FIG. 3A. The matrix multiplication circuit includes n logic circuits 370-374 corresponding to elements of the state vector s [0026] Alternatively, each element of the state output matrix might be generated by Boolean minimization. For example, the 18-bit LFSR 100 of the prior art (FIG. 1) produces a PN polynomial as in equation [4] where offset value C [0027] An initial transition matrix M [0028] Logic equations for each element of the matrix multiplication product of FIG. 3B have the general form of equation [6].
[0029] The predetermined form of the sparse transition matrix of equation [5], therefore, provides a highly advantageous matrix multiplication circuit. A first element of the offset state vector for the PN polynomial of equation [4], for example, is simply column element s [0030] Turning now to FIG. 4, there is a block diagram of a state generator circuit of the present invention for producing a plurality of state matrices separated by a predetermined count or offset. The circuit includes a state matrix generator circuit as previously described in FIG. 3A. The state matrix generator circuit receives a state-input matrix S [0031] In operation, the count signal c [0032] Referring now to FIG. 5, there is a block diagram of another embodiment of a PN generator of the present invention that may be used in lieu of the prior art circuit of FIG. 1 or FIG. 2. The PN generator circuit includes a first and a second series of matrix generator circuits arranged in parallel. Each series of matrix generator circuits includes preferably N stages having 2 [0033] In operation, each matrix generator circuit of the first series includes a respective exponentially weighted transition matrix N [0034] A practical application of the previously described embodiments creates a need to generate modified PN sequences. These modified sequences include generation of truncated PN sequences and zero insertion in PN sequences as will be described in detail. The need to generate a truncated sequence arises when an application requires a periodic PN sequence that is a subset of a maximal length PN sequence. For example, an N-bit LFSR of the prior art has a maximal length of 2 [0035] Referring now to FIG. 6, there is a block diagram of a circuit of the present invention for generating a truncated sequence. The circuit receives an input state matrix S [0036] Turning to FIG. 7A- [0037] Offset M on lead 619 produces a state matrix B at the output of PN generator 618 on bus 620, including 8 bits extending from bit 15 through bit 22. The three most significant bits 20-22, however, are outside the permissible periodic range zero through L-1. The value R applies zeros to the three most significant bits of signal MASK on bus 622 and ones elsewhere. Thus, AND gate 624 produces state matrix D on bus 626. OR gate 610 combines input state matrices on buses 608 and 626 to produce a modified state matrix on bus 612. This modified state matrix includes original bits 15-19 as the least significant bits and original bits 0-2 as the most significant bits. Comparator circuit 632 determines if offset M is greater than L-k. If so, multiplex circuit 614 applies the modified state matrix on bus 612 to output bus 616. Otherwise, multiplex circuit 614 applies the unmodified PN sequence on bus 620 to output bus 616. The resulting output state matrix S [0038] Although the invention has been described in detail with reference to its preferred embodiment, it is to be understood that this description is by way of example only and is not to be construed in a limiting sense. For example, the circuit of FIG. 6 may also be used to advantageously insert a zero into the PN sequence, thereby producing a sequence having 2 Referenced by
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