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Publication numberUS20010005046 A1
Publication typeApplication
Application numberUS 09/753,735
Publication dateJun 28, 2001
Filing dateJan 2, 2001
Priority dateJan 14, 1999
Also published asUS6252300, US6323546
Publication number09753735, 753735, US 2001/0005046 A1, US 2001/005046 A1, US 20010005046 A1, US 20010005046A1, US 2001005046 A1, US 2001005046A1, US-A1-20010005046, US-A1-2001005046, US2001/0005046A1, US2001/005046A1, US20010005046 A1, US20010005046A1, US2001005046 A1, US2001005046A1
InventorsMin Hsuan, Charlie Han
Original AssigneeHsuan Min Chih, Charlie Han
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Direct contact through hole type wafer structure
US 20010005046 A1
Abstract
A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.
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Claims(23)
What is claimed is:
1. A direct contact through hole type wafer structure, comprising:
a silicon-on-insulator substrate having a first silicon substrate, a second silicon substrate and a first insulation layer with the first insulation layer positioned between the first and second silicon substrates, wherein at least one opening is formed in the second silicon substrate and penetrates into the first silicon substrate through the first insulation layer;
at least one device positioned on the first silicon substrate;
a plurality of contact plugs positioned in the first silicon substrate and exposed by the opening;
a plurality of dielectric layers and a plurality of patterned conductive layers which couples with the device and the contact plugs and a plurality of plugs in the dielectric layers, and the dielectric layers and the patterned conductive layers being alternately stacked on the first silicon substrate, wherein at least one bonding pad is formed on an uppermost conductive layer and exposed by an uppermost dielectric layer formed on the uppermost conductive layer;
a second insulation layer positioned in the opening, wherein the second insulation layer is along a surface of the opening and exposes the contact plugs;
a barrier layer positioned on the second insulation layer and coupled with the contact plugs; and
a metal layer positioned on the barrier layer.
2. The structure of
claim 1
, wherein bumps are positioned on the metal layer and the bonding pad, respectively.
3. The structure of
claim 2
, wherein a conductive material is positioned between the bumps and the metal layer.
4. The structure of
claim 3
, wherein the conductive material includes conductive epoxy.
5. The structure of
claim 3
, wherein the conductive material includes conductive silicone.
6. The structure of
claim 1
, wherein the second insulation layer includes silicon dioxide.
7. The structure of
claim 1
, wherein a material used to form the barrier layer is selected from a group consisting of titanium, titanium nitride, titanium/tungsten alloy, chromium and a combination thereof.
8. The structure of
claim 1
, wherein a material used to form the metal layer is selected from a group consisting of nickel, tungsten, gold, palladium and a combination thereof.
9. The structure of
claim 1
, wherein the bump includes gold.
10. The structure of
claim 1
, wherein the bump includes lead/tin alloy
11. The structure of
claim 1
, wherein the bump includes tin.
12. The structure of
claim 1
, wherein an arrangement of the contact plugs in the opening is an array.
13. A direct contact through hole type wafer structure, comprising:
a substrate having a first surface and a second surface;
at least one device positioned on the first surface;
a first contact positioned over the first surface and coupled with the device; and
a second contact positioned over the second surface and coupled with the device.
14. The structure of
claim 13
, wherein a plurality of bumps is positioned on the first contact and the second contact, respectively.
15. The structure of
claim 13
, wherein the first contact is coupled with the device through at least one conducting wire, which is positioned in the substrate and exposed on the second surface.
16. The structure of
claim 15
, wherein the second contact is coupled with the conducting wire through at least a contact plug, which is positioned in the substrate and exposed on the second surface.
17. The structure of
claim 13
, wherein the second contact is coupled with the device through at least one contact plug, which is positioned in the substrate and exposed on the second surface.
18. The structure of
claim 13
, wherein the substrate includes a silicon-on-insulator substrate.
19. A three-dimensional stacked-type package, comprising:
a substrate; and
a plurality of chips having contacts on both sides attached on the substrate, wherein chips are stacked with each other by the contacts and coupled to the substrate.
20. The structure of
claim 19
, wherein other groups of the chips are coupled on the substrate.
21. The structure of
claim 20
, wherein each group of the chips is coupled with each other by wire bonding.
22. The structure of
claim 20
, wherein each group of the chips is coupled with each other by tape automatic bonding.
23. The structure of
claim 19
, wherein the chips are direct contact through hole type chips.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a wafer structure. More particularly, the present invention relates to a direct contact through hole type wafer structure.
  • [0003]
    2. Description of the Related Art
  • [0004]
    A trend for electrical products is to be light, short, small and thin. Not only the chips manufacturing technology but also the packaging technology is developed rapidly to meet the trend. Since a width of a chip is reduced quickly, an integration of the chip is increased and a volume of a chip is decreased. As a result, it is an important task to develop a new packaging technology, which is able to form a small volume package.
  • [0005]
    Memory modules, for example, are the common semiconductor products. The memory modules are generally formed by the following steps. Chips are first packaged, and then the packages are attached to a printed circuit board. The steps of forming the memory modules are complicated and manufacturing costs are high. Additionally, the arrangement of the packages on the printed circuit board is two-dimensional. An area occupied by the packages is large, so that the packaging density is low. To further reduce reduction of a size of the memory module is limited.
  • [0006]
    A stacked-type package structure is designed to overcome the above problems. The package structure is three-dimensional, thus an area occupied by packages is reduced and the packaging density is increased.
  • [0007]
    [0007]FIG. 1 is a schematic, cross-sectional diagram of a conventional stacked-type package structure.
  • [0008]
    Referring to FIG. 1, chips 10 a, 10 b and 10 c are coupled with leadframes 14 a, 14 b and 14 c by bonding wires 12, respectively. The chips 10 a, 10 b, 10 c and the leadframes 14 a, 14 b, 14 c are sealed by epoxy 16 to form packages 18 a, 18 b and 18 c. The packages 18 a, 18 b, 18 c are stacked and coupled with each other by outer leads of the leadframes 14 a, 14 b, 14 c. Outer leads of the leadframe 14 c couple with contacts 22 on a printed circuit board 20 by tape automatic bonding.
  • [0009]
    Although the stacked-type package structure reduces the area occupied by the packages, a height of the stacked-type package structure is high. Furthermore, a signal-transmitting path from the stacked-type package structure to the printed circuit board is long, so that electrical impedance is increased. As a result, signals transmitted decay and are delayed.
  • SUMMARY OF THE INVENTION
  • [0010]
    Accordingly, the present invention provides a direct contact through hole type wafer structure that has contacts on both sides.
  • [0011]
    The invention provides a direct contact through hole type wafer structure that is used to form a wafer-level package, so that a volume and a height of the package are reduced.
  • [0012]
    The invention provides a direct contact through hole type wafer structure used to form a package, so that a signal transmitting path and electrical impedance of the package are reduced.
  • [0013]
    To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a three-dimensional stacked-type package structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.
  • [0014]
    Because a package structure provided according to the invention is a wafer-level package, a volume and a height of the package are reduced. Additionally, the signal-transmitting path is reduced. The electrical impedance is also reduced, so that the problem of signals delayed and decayed is avoided.
  • [0015]
    It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0016]
    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
  • [0017]
    [0017]FIG. 1 is a schematic, cross-sectional diagram of a conventional tape automatic bonding package structure;
  • [0018]
    [0018]FIGS. 2A through 2H are schematic, cross-sectional diagrams of fabricating a three-dimensional stacked-type package structure according to the invention;
  • [0019]
    [0019]FIG. 2I is a schematic, cross-sectional diagram of another three-dimensional stacked-type package structure according to the invention;
  • [0020]
    [0020]FIG. 3 is a schematic, cross-sectional diagram showing packages formed according to the invention; and
  • [0021]
    [0021]FIG. 4 is a schematic, cross-sectional diagram showing an adhesion part of bumps.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0022]
    Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • [0023]
    [0023]FIGS. 2A through 2H are schematic, cross-sectional diagrams of fabricating a three-dimensional stacked-type package structure according to the invention.
  • [0024]
    As shown in FIG. 2A, a silicon-on-insulator (SOI) substrate 30 is preferred in the invention. The silicon-on-insulator substrate 30 is made from an insulation layer 34 and silicon substrates 32 and 36. The insulation layer 34 is located between the silicon substrates 32 and 36.
  • [0025]
    There are three methods generally used to form the silicon-on-insulator substrate 30.
  • [0026]
    In the first method, an ion implantation process and a thermal process are performed in sequence to form a silicon dioxide layer in a silicon substrate. The depth of the silicon dioxide layer is about 2 to 3 μm.
  • [0027]
    In the second method, a silicon dioxide layer is formed on a silicon substrate. Another silicon substrate is adhered to the silicon dioxide layer.
  • [0028]
    In the third method, a silicon dioxide layer is formed on a silicon substrate. A silicon layer is formed on the silicon dioxide layer by epitaxy.
  • [0029]
    Referring to FIG. 2B, metal-oxide-semiconductor (MOS) transistors 38 and an insulation structure 40 such as shallow trench isolation, are formed in the silicon substrate 32. Additionally, devices (not shown), for example, resistors, capacitors, inductors, diodes and bipolar junction transistors (BJT) are formed in the silicon substrate 32. A plurality of contact plugs 42 is also formed in the silicon substrate 32. The material used to form the contact plugs 42 is selected from a group consisting of tungsten, copper, and aluminum.
  • [0030]
    Referring to FIG. 2C, steps of forming multilevel interconnects are performed. The technique of forming multilevel interconnects is not directly related to the invention and is well known to those skilled in the art, so that detailed description is omitted herein. As a result, insulation layers 48 a, 48 b, 48 c, 48 d and patterned conductive layers 44 a, 44 b, 44 c are formed over the silicon substrate 32. Furthermore, plugs 46 are formed in the insulation layers 48 a, 48 b and 48 c. The conductive layer 44 c is used as a bonding pad. It is also suitable to form a plurality of bonding pads on the conductive layer 44 c. The insulation layer 48 d is formed on the conductive layer 44 c as a passivation layer and exposes a portion of the conductive layer 44 c. The conductive layers 44 a, 44 b and 44 c include aluminum, doped polysilicon, tungsten or copper, and the step of forming the conductive layer 44 a, 44 b and 44 c includes sputtering or chemical vapor deposition. The material used to form the insulation layers 48 a, 48 b, 48 c and 48 d is selected from a group consisting of silicon dioxide, silicon nitride, spin-on-glass (SOG) and borophosphosilicate glass (BPSG). The plugs 46 include tungsten, aluminum or copper.
  • [0031]
    Referring to FIG. 2D, a patterned photoresist layer 50 is formed on the silicon substrate 36. A portion of the silicon substrate 36 is removed by using the insulation layer 34 as a stop layer to form an opening 52 and the opening 52 is aligned with the contact plugs 42. The step of removing the silicon substrate 36 includes wet etching or electrochemical etching.
  • [0032]
    Referring to FIG. 2E, a portion of the insulation layer 34 and a portion of the silicon substrate 32 are removed by using the photoresist layer 50 as a mask to form an opening 52 a. The step of removing the silicon substrate 32 and the insulation layer 34 is preferably dry etching. The contact plugs 42 are exposed by the opening 52 a. Then, the photoresist layer 50 is removed.
  • [0033]
    The steps illustrated in FIGS. 2D and 2E are like a micro machining process. The purpose of the above two steps is to expose the contact plugs 42 in the opening 52 a. As a result, the contact plugs 42 can serve as contacts on the silicon-on-insulator substrate 30.
  • [0034]
    Referring to FIG. 2F, an insulation layer 54 is formed in the opening 52 aand along the exposed silicon substrate 32 and 36. Additionally, the contact plugs 42 are exposed. The step of forming the insulation layer 54 includes thermal oxidation or deposition. The purpose of the insulation layer 54 is to isolate the contact plugs 42 from the silicon substrate 32.
  • [0035]
    Referring to FIG. 2G, a barrier layer 56 and a metal layer 58 are formed in sequence on the insulation layer 54. The purpose of the barrier layer 56 is to prevent ions in subsequently formed thin films from penetrating into the silicon-on-insulator 30 and affecting the devices in the silicon-on-insulator 30. The material used to form the barrier layer 56 is selected from a group consisting of titanium, titanium nitride, titanium/tungsten alloy, chromium and a combination thereof. The purpose of the metal layer 58 is to improve the adhesion between the barrier layer 56 and a subsequently formed bump. The material used to form the metal layer 58 is selected from a group consisting of nickel, tungsten, gold, palladium and a combination thereof.
  • [0036]
    Referring to FIG. 2H, bumps 60 are formed on the metal layer 58 and the conductive layer 44 c. Furthermore, a barrier layer (not shown) and a metal layer (not shown) can also be formed on the conductive layer 44 c before forming the bumps 60 to improve the reliability. The material used to form the bumps 60 is selected from a group consisting of gold, tin and lead/tin alloy, whose ratio is about 95 to 5. The bumps 60 are coupled with the devices in the silicon-on-insulator 30 by the contact plugs 42, the conductive layer 44 a, 44 b, 44 c and the plugs 46.
  • [0037]
    In the invention, the contact plugs 42 are exposed in the opening 52 a, so that a direct contact through hole (DCTH) type wafer is fabricated and both sides of the silicon-on-insulator 30 have contacts. The contact plugs 42 are arranged as an array, thus a plurality of the contact plugs 42 are coupled with a bump 60. Furthermore, a bump 60 formed to cover a plurality of the opening 52 a is also acceptable.
  • [0038]
    [0038]FIG. 21 is a schematic, cross-sectional diagram of another three-dimensional stacked-type package structure according to the invention.
  • [0039]
    Referring to FIG. 2I, a conductive material 62 fills the opening 52 a to reduce stresses. Then, the bump 60 is formed on the conductive material 62. The conductive material 62 includes conductive silicone or conductive epoxy.
  • [0040]
    [0040]FIG. 3 is a schematic, cross-sectional diagram showing packages formed according to the invention.
  • [0041]
    Referring to FIG. 3, chips 74 formed according to the invention have bumps 60 on both sides of the chips 74. Each chip 74 couples with other chips 74 or contacts 72 on a printed circuit board 70 by the bumps 60. In FIG. 3, a stack 78 a formed by three chips 74 is shown on the right-hand side and a stack 78 b formed by two chips 74 is shown on the left-hand side. The stacks 78 a and 78 b are coupled by a bonding wire 76. The step of coupling the stacks 78 a and 78 b includes wire bonding or tape automatic bonding.
  • [0042]
    [0042]FIG. 4 is a schematic, cross-sectional diagram showing an adhesion part of bumps.
  • [0043]
    Referring to FIG. 4, the bump 60 on the chip 74 is made from a substantially high melting point material. A substantially low melting point material 80 such as lead/tin alloy, whose ratio is about 63 to 37, is used as a solder when the chip 74 adheres to another chip 74. Anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) is also suitable for the solder. In order to avoid a stress generated by heat during the operation, which usually breaks the adhesion between the bumps 60, an underfill 82 is filled between chips 74, and the chip 74 and the printed circuit board 70 (FIG. 3). Since the chip 74 is directly attached to the printed circuit board 70 (FIG. 3), no carrier is used. The package according to the invention is a wafer-level package, so that a volume and a height of the package are reduced.
  • [0044]
    In the embodiment, one bump is formed over an opening. However, a bump formed over a plurality of openings is acceptable. The process is similar to the one mentioned above, so that the detailed description is omitted herein.
  • [0045]
    According to the foregoing, the advantages of the invention include the following:
  • [0046]
    1. A wafer fabricated according to the invention is a direct contact through hole type wafer, so that both sides of the wafer have contacts. As a result, chips according to the invention are easily stacked. Especially, the chips are stacked three-dimensionally.
  • [0047]
    2. A package according to the invention is a wafer-level package and stacked three-dimensionally, so that the volume and the height of the package are decreased.
  • [0048]
    3. Because chips are coupled with other chips or the printed circuit board by the bumps, the signal transmitting path is reduced. As a result, electrical impedance is reduced. The problem of the signals delaying and decaying is avoided.
  • [0049]
    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Referenced by
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US6838310 *Jun 11, 2002Jan 4, 2005United Microelectronics CorporationIntegrated circuit with improved interconnect structure and process for making same
US7391114 *Feb 1, 2005Jun 24, 2008Matsushita Electric Industrial Co., Ltd.Electrode pad section for external connection
US7528068 *Mar 22, 2005May 5, 2009Nec Electronics CorporationMethod for manufacturing semiconductor device
US7692315 *Feb 11, 2005Apr 6, 2010Fujitsu Microelectronics LimitedSemiconductor device and method for manufacturing the same
US8034703Dec 18, 2009Oct 11, 2011Fujitsu Semiconductor LimitedSemiconductor device and method for manufacturing the same
US8034704 *Nov 27, 2007Oct 11, 2011Sony CorporationMethod for manufacturing semiconductor device and semiconductor device
US8089162Aug 10, 2009Jan 3, 2012Fujitsu Semiconductor LimitedSemiconductor device and method for manufacturing the same
US8603911 *May 11, 2011Dec 10, 2013Siliconware Precision Industries Co., Ltd.Semiconductor device and fabrication method thereof
US20030173678 *Feb 14, 2003Sep 18, 2003Fujitsu LimitedSemiconductor device and method for fabricating the same
US20050146041 *Feb 11, 2005Jul 7, 2005Fujitsu LimitedSemiconductor device and method for manufacturing the same
US20050173801 *Feb 1, 2005Aug 11, 2005Matsushita Elec. Ind. Co. Ltd.Semiconductor device
US20060131691 *Jun 11, 2004Jun 22, 2006Koninklijke Philips Electronics N.V.Electronic device, assembly and methods of manufacturing an electronic device
US20080136023 *Nov 27, 2007Jun 12, 2008Sony CorporationMethod for manufacturing semiconductor device and semiconductor device
US20090294988 *Aug 10, 2009Dec 3, 2009Fujitsu Microelectronics LimitedSemiconductor device and method for manufacturing the same
US20100130004 *Dec 18, 2009May 27, 2010Fujitsu Microelectronics LimitedSemiconductor device and method for manufacturing the same
US20120223425 *May 11, 2011Sep 6, 2012Siliconware Precision Industries Co., Ltd.Semiconductor device and fabrication method thereof
WO2003065440A1 *Jan 23, 2003Aug 7, 2003Strand Interconnect AbMethod to arrange silicon structures on top of each other and arrangement herefor
Legal Events
DateCodeEventDescription
Jan 2, 2001ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSUAN, MIN-CHIH;HSN, CHARLIE;REEL/FRAME:011427/0913;SIGNING DATES FROM 19990209 TO 19990210
Apr 26, 2005FPAYFee payment
Year of fee payment: 4
May 4, 2009FPAYFee payment
Year of fee payment: 8
Mar 1, 2013FPAYFee payment
Year of fee payment: 12