FIELD OF THE INVENTION
The invention relates generally to asynchronous data transfer over a high-speed synchronous transmission system, such as those utilizing ATM transport over a Digital Subscriber Line (DSL). More particularly, the present invention is directed to latency minimization between a host computing system and an ADSL transceiver.
BACKGROUND OF THE INVENTION
In a high-speed synchronous transmission system, modulated symbols are sent continuously in time. When it is implemented by a computer host processor (so called software modem), it is extremely critical to maintain a continuous bit stream output between the real time transceiver and the non-real time host system (such as a local host computing system running an operating system such as Microsoft Windows® NT or the like). To reduce transport delay, latencies between each interface located in the data path (i.e., between the upstream transceiver to operating system) must be kept to a minimum.
There are a number of such interfaces in such data path, and various mechanisms have been proposed to ensure a continuous stream of demodulated/modulated data. First, an analog channel interface portion of a downstream ADSL transceiver is responsible for receiving, transmitting, processing analog data signals, and maintaining a synchronized data link through a channel to an upstream transceiver interface. This is a real-time link, and accordingly a modulated signal must be present (at some level, even in reduced power management modes) at all times. An example of a prior art approach for ensuring that the data link is kept synchronized, even when one end is connected to an asynchronous source, is U.S. Pat. No. 5,003,558. This reference teaches sending an “idle” signal to keep the link active even when there is no real data, but, notably, does not address the problem of how to cure latencies which may be present in such asynchronous source.
Next after the channel interface portion in the data path lies a physical layer transport circuit. This portion of the data link is responsible for modulating and demodulating data symbols. To reduce latencies between the channel interface and the physical layer, Receive/Transmit FIFO buffers are used. This technique is well known in the art, and an example of this type of technology is depicted in U.S. Pat. Nos. 4,823,312 and 5,140,679 assigned to National. Accordingly, there are reasonably well developed solutions to the problems of latency and transport delay between a channel interface and physical layer in an ADSL transceiver, and this portion of the data path can be maintained as real time without undue cost and/or complexity.
A larger challenge is posed, however, by the data path located between the physical layer and the logical layer, in this case, an ATM protocol layer. The ATM protocol layer is required to interface both with the physical layer (a real time data path) and with the operating system (an asynchronous data path). To reduce latencies between these two interfaces, one approach would be to use the same kinds of Receive/Transmit FIFO buffers as explained earlier between the channel interface and physical layer. In this respect, on the receive side of the data path, it is possible to use a sufficiently large Receiver buffer to compensate for latencies inherent in the operations of the ADSL physical layer and ATM protocol layer when the latter are implemented in a software modem. Such latencies arise from the fact that, in a software modem context, both such functions are performed by the host processing device executing routines of different priority. For instance, in a Windows operating system, the ADSL physical layer is configured as an Interrupt Service Routine (ISR), while the ATM protocol layer is set up as a lower priority Delayed Procedure Call (DPC). The ADSL Physical layer is configured as a high priority task in the operating system, because, in this manner, latency between this layer and the channel interface is reduced, and the buffers between such interfaces can be reduced as well.
Because a DPC is a lower priority task than an ISR, however, there is an inherent latency between the physical layer and ATM operations, and a Receiver buffer must be employed between the two to handle such disparity. Nevertheless, when a buffer is used, a transport delay is introduced, which, of course, is undesirable. To reduce this delay, the buffer size must be correspondingly reduced. This design goal of course must be tempered by the fact that the buffer must be at least large enough to accommodate expected latencies caused by the difference in priorities of the ADSL Physical Layer and the ATM protocol layer. One proposed solution would be to make the ATM protocol an ISR as well, so that there is no latency between the ADSL Physical Layer and the ATM protocols. This approach is unattractive for the plain fact that ATM protocols require many system calls that cannot be accommodated in an ISR routine, because such routines must be executed in a very short period of time.
Consequently, in most ADSL software modem systems, it is expected there will be a buffer interface between the ADSL physical layer and the ATM protocol. The size of the buffer can be varied, of course, depending on the expected channel data rate, expected operating system latencies, etc. In a typical PC using Microsoft Windows, a latency time of about 10 to 30 msec is contemplated. It is, of course, extremely critical to reduce this latency as much as possible to ensure efficient data transmissions across the entire data link.
One approach suggested in the prior art (such as described in the aforementioned references above) is to include some kind of threshold fill point, or “water mark” for the receive and transmit buffers. In the transmit direction, a transmit buffer water mark is set to some value that is close to the full capacity of the buffer size. When the data in the buffer drops below this mark, an ATM protocol layer routine is activated and more data is loaded (poured in) in the transmit buffer. Accordingly, at any moment in time, an amount of data equal to the transmit buffer water mark level is available to sustain continuous data transmission due to system latency. In the receiving direction, a receive buffer water mark is set to some value close to the empty capacity of the buffer size. When the buffer fills with data above this level, the ATM protocol layer routine is again activated and more data is extracted (poured out) from the receive buffer. Accordingly, at any moment in time, an amount of data equal to the capacity above the receive water mark level is available for the synchronous receiver to store received data due to system latency.
The problem with this approach is the fact that there is often no real data to be transmitted by the operating system to the upstream transmitter, yet the data link on the upstream side must be maintained. As a result, after verifying from the operating system that there are no applications transmitting data, the ATM protocol layer routine must load the buffer with “dummy” data corresponding to a fixed pattern recognizable by the upstream transmitter as such, in a manner similar to that noted in U.S. Pat. No. 5,003,558 discussed above Performing this extra task, however, consumes valuable processing time, and reduces system efficiency. Moreover, by loading the transmit buffer with “dummy” ATM cells, overall data transport latency increases because such data must be flushed in serial fashion through the channel to the upstream transceiver, even when new transmit data is available from the operating system.
Accordingly, the commonly suggested techniques for handling latency in an ADSL software environment while maintaining a synchronous link are impractical, and, in many cases, inefficient.
SUMMARY OF THE INVENTION
An object of the present invention, therefore, is to provide an improved system and method for maintaining a continuous and uninterrupted ADSL data bit stream between an operating system implementing a downstream transceiver, and a remote upstream transmitter;
A further object of the present invention is to provide an improved ATM protocol system and method which is simpler to implement in an ADSL software transceiver;
A related object of the present invention is to provide an improved system and method for reducing overall data transport latency in a data path between an operating system implementing a downstream transceiver, and a remote upstream transmitter.
A further object of the present invention is to apply the above methods in any high-speed synchronous transmission systems which must include a source of asynchronous traffic transport.
A system of the present invention therefore eliminates latencies caused by asynchronous data transport requirements associated with a synchronous data channel, which, in a preferred embodiment, carries ADSL signals in accordance with known protocols and standards. The system first includes a logical data layer, which is coupled to the asynchronous operating system, which can be a personal computer. This logical layer receives data blocks corresponding to actual data to be transmitted by applications running on an asynchronously running operating system. These data blocks are converted into actual data logical blocks. A transmit data buffer is coupled to the logical data layer, and stores the actual data logical block after it is processed by the logical data layer. A dummy data buffer is used for storing a dummy data logical block corresponding to a logical data block containing no actual operating system data, i.e., a fixed data pattern that can sent on the synchronous data link as fill data to maintain synchronization. A physical data layer is also coupled to the transmit data buffer, the dummy data buffer, and the synchronous data channel. The physical data layer converts the actual data logical blocks into actual data digital signals for transmission in the synchronous data channel. It also converts the dummy data logical blocks to dummy data digital signals for transmission in the synchronous data channel to maintain synchronization as noted. Thus, the physical data layer transmits real data digital signals to the synchronous data channel when there is an actual data logical block in the transmit data buffer and otherwise transmits the dummy data digital signals. The dummy data logical block is selected to be equal in size to a single actual data logical block to facilitate handling by the physical layer.
The advantages of this approach are many, and include the fact that the latency is reduced because dummy data is not stored in the transmit buffer, and the fact that the logical layer does not waste time storing such dummy data in the first place. Furthermore, the latency in the synchronous data channel is limited to be no more than the time required to transmit a single dummy data logical block. More importantly, it can be seen that the latency is substantially independent of any latency caused by the asynchronous operating system.
In a preferred embodiment, the latency reduction system is used within a software modem environment.
In this regard, the logical data layer is implemented as an ATM protocol layer, which has a transmit routine for converting the asynchronous data block into an actual logical data block corresponding to an ATM cell. Such protocol layer can be implemented in hardware, or preferably, as an ATM protocol routine executed by a processing device within the asynchronously operating computing system. The transmit portion (subroutine) of the ATM protocol routine is specifically configured, therefore, so that when no actual operating system data is available for transmission, it does load any data (or dummy data cells) into the transmit data buffer. The transmit portion of the ATM protocol routine is preferably activated or invoked whenever the transmit data buffer contains an amount of data less than a transmit threshold value (or water mark). Further in a preferred embodiment, the physical data layer is an ADSL physical layer routine executed by the processing device. Such physical layer can be implemented in dedicated front end transceiver hardware, or preferably as an ADSL physical data layer routine which is executed with a higher priority (or lower latency) than the ATM protocol routine. The ADSL physical layer transmit routine sends a dummy data digital signal when there is no data, but does not load such data from the transmit data buffer. At the end of such operation, it checks the transmit data buffer to determine if any actual data logic block should be converted and transmitted. If yes, it does not send any further dummy data, and goes on to send real data. This operational feature ensures the maximum 1 dummy cell maximum latency length.
A preferred embodiment of an ADSL transceiver implemented in accordance with the present invention includes the aforementioned latency reduction system, as well as a number of additional transmit and receive components. In particular, a downstream transceiver front end circuit is coupled to the physical data layer and converts the real data digital signals and the dummy data digital signals into real data analog signals and dummy data analog signals respectively for transmission through the synchronous channel to a second upstream transceiver. As part of this front end, a second transmit data buffer is coupled between the physical data layer and the downstream transceiver front end circuit for storing data corresponding to the real data digital signals and the dummy data digital signals. Such front end also includes a first receive data buffer coupled between the physical layer and the downstream transceiver front end circuit for storing data corresponding to received data digital signals from the upstream transceiver. In addition, a second receive data buffer is coupled between the physical data layer and the logical data layer for storing data corresponding to received data logical blocks from the upstream transceiver. This latter structure helps minimize latency on the receive side of the transmitter.
The latency reducing system of the present invention, including the physical layer and logical layer routines, can also be implemented in a computer program executable within the aforementioned operating system. Alternatively, the system can be embedded in silicon form such as in a programmed ROM or the like which can be executed by a dedicated hardware DSP.
A preferred method of transmitting data between a synchronous data channel and an asynchronous operating system based on the present invention accomplishes this objective by generally performing the following steps: (a) determining if there is actual data to be transmitted by the asynchronous operating system; (b) converting any such actual data into an actual data logical block; and (c) buffering the actual data logical block; and (d) determining whether an actual data logical block has been buffered; and (e) when an actual data logical block has been buffered, converting the actual data logical block into actual data digital signals for transmission in the synchronous data channel; and when no actual data logical block has been buffered, converting a dummy data logical block to dummy data digital signals for transmission in the synchronous data channel.
As noted above, the actual logical data block preferably corresponds to an ATM formatted cell. Again, too, only actual data logic blocks are buffered, which reduces latency significantly. When the number of actual data logical blocks falls below a predetermined threshold value, steps (a) through (c) are repeated. Since only actual data is stored in the transmit buffer, the use of the water mark or threshold provides significant performance advantage because it now more accurately reflects transmit data status. As also alluded to above, the aforementioned steps are preferably performed by various routines executed by a software modem. As such, these steps are performed by a number of routines executed by a processing device within the asynchronous computing system. Also, as noted earlier, the logical layer routine is executed with a lower priority than the physical layer routine. The same latency improvement advantages as outlined above are possible with the disclosed method therefore.
A method of implementing an ADSL transceiver, therefore, includes the aforementioned latency reducing process, as well as further necessary steps. These include, generally, a step (f): converting the real data digital signals and the dummy data digital signals into real data analog signals and dummy data analog signals respectively for transmission through the synchronous channel to a second upstream transceiver. Again, an additional step (g) can also be employed of buffering data corresponding to the real data digital signals and the dummy data digital signals. On the receiving side, the preferred method includes a step (h): buffering data corresponding to received data digital signals from the upstream transceiver. An additional step (i): buffering data corresponding to received data logical blocks from the upstream transceiver is also executed.
Although the inventions are described below in a preferred embodiment involving an ADSL transceiver, it will be apparent to those skilled in the art the present invention would be beneficially used in many environments where it is necessary to minimize latencies in a real time data transmission path for non-real time traffic transport.
The important distinction is that the present invention overcomes the latency problems of the prior art through the use of an improved ATM protocol layer 120, and a “dummy” cell buffer 130 as now explained more fully. As noted earlier, at many times, there is no real data traffic on the transmit side coming from applications 125; in such cases, the transmit portion of ATM protocol layer 120 must insert “dummy” cells into second transmit buffer 115. This is because, as also explained above, an overall constant data stream bit rate meeting the ADSL standard must be maintained on this side of ADSL transceiver 100. In other words, the return leg of the ADSL link must be kept synchronous as well, despite the fact that there is an asynchronous data source at one end. These dummy cells are inserted into the bit stream, but are discarded at the other end of the data link by upstream transceiver 102 because they carry no information. Unlike other systems, however, the transmit portion of ATM protocol layer 120 of the present invention does not load second transmit buffer 115 with dummy cells, even when there is no data traffic forthcoming from applications 125. Instead, the transmit portion of ATM protocol layer 120 only loads actual data cells to second transmit buffer 115. Accordingly, second transmit buffer 115 is never loaded with dummy cells, and only contains actual transmit data. To handle the problem of stuffing the bit stream with dummy cells to maintain synchronization, a separate dummy buffer 130 is employed. This dummy buffer contains a predefined cell pattern for the dummy cell that would otherwise be generated, retrieved or transmitted by the transmit subroutine portion of ATM protocol layer 120. Like second transmit buffer 115, dummy buffer 130 is also coupled to ADSL Physical Layer 110, and therefore can provide the dummy cell pattern data as required during a transmit operation. As with second transmit buffer 115, dummy buffer can be implemented as a software structure in system memory of arbitrary size, or in hardware since the cell pattern data is fixed. It is conceivable, of course, that dummy buffer can contain patterns other than dummy cells which may be fixed data patterns that must be transmitted to an upstream transceiver during portions of a data transmission. Again, as with other systems which utilize a transmit buffer “water mark,” (or transmit data threshold) a transmit portion of ATM Protocol Layer 120 can be activated when transmit data buffer 115 falls below the transmit water mark.