Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010005615 A1
Publication typeApplication
Application numberUS 09/735,952
Publication dateJun 28, 2001
Filing dateDec 14, 2000
Priority dateDec 24, 1999
Also published asUS6287938
Publication number09735952, 735952, US 2001/0005615 A1, US 2001/005615 A1, US 20010005615 A1, US 20010005615A1, US 2001005615 A1, US 2001005615A1, US-A1-20010005615, US-A1-2001005615, US2001/0005615A1, US2001/005615A1, US20010005615 A1, US20010005615A1, US2001005615 A1, US2001005615A1
InventorsKi-Yeup Lee, Byoung-Ju Kang
Original AssigneeKi-Yeup Lee, Byoung-Ju Kang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for manufacturing shallow trench isolation in semiconductor device
US 20010005615 A1
Abstract
A method for manufacturing a trench isolation in a semiconductor device, wherein the method includes the steps of: forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization, thereby forming the trench isolation.
Images(2)
Previous page
Next page
Claims(9)
What is claimed is:
1. A method for manufacturing a trench isolation, comprising the steps of:
a) forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization;
b) forming a vertical sidewall at a middle of the trench by a second etching of low polymerization; and
c) forming a narrow rounded concave shape at a bottom portion of the trench by a third etching of high polymerization, thereby forming the trench isolation.
2. The method as recited
claim 1
, wherein the step a) is carried out using a RF power of 100200 W, a pressure of 5060 mTorr, a flux of chlorine gas (Cl2) of 1020 sccm, and nitrogen gas (N2) of 1525 sccm.
3. The method as recited in
claim 1
, wherein the step b) is carried out using a RF power of 400500 W, a pressure of 3040 mTorr, a flux of Cl2 of 1525 sccm, a flux of sulfur hexafluoride (SF6) of 2540 sccm, and a flux of N2 of 1525 sccm.
4. The method as recited in
claim 1
, wherein the step c) is carried out using a RF power of 100200 W, a pressure of 5060 mTorr, a flux of Cl2 of 1020 sccm, and a flux of N2 of 2330 sccm.
5. The method as recited in
claim 1
, after the step c), further comprising the steps of:
d) removing defects produced from the etching steps by annealing process for moving the defects on a surface area and by washing a substrate at least one time in phosphoric acid (H3PO4);
e) forming a first oxide film by oxidizing the surface of the trench and removing the first oxide film by wet etching, at least one time;
f) forming a nitride and a second oxide films on whole the trench surface; and
g) annealing the substrate again, thereby a stress direction moving from the substrate toward the second oxide film.
6. The method as recited in
claim 5
, wherein the nitride film is formed to a thickness ranging from 20 to 100 Å.
7. The method as recited in
claim 5
, wherein the annealing process is carried out at 9501,200 C. for 1040 minutes.
8. The method as recited in
claim 5
, wherein the step e) is carried out under the condition that a thickness of the first oxide film is 100300 Å, a temperature is 400500 C., and fluxes of O2, H2 and N2 are 28 sccm, 38 sccm and 13 sccm, respectively.
9. The method as recited in
claim 8
, wherein the first oxide film is removed by using an etchant such as hydro fluoride (HF) solution or buffered oxide etchant (BOE).
Description
FIELD OF THE INVENTION

[0001] The present invention relates to a method for manufacturing a semiconductor memory device; and, more particularly, to a method for manufacturing a shallow trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.

DESCRIPTION OF THE PRIOR ART

[0002] As is well known, a dynamic random access memory (DRAM) having a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization.

[0003] Therefore, as the device dimension becomes reduced in the memory cell, the dimensions of active regions and the space therebetween are accordingly reduced as well. Isolation regions, which play an important role in preventing current leakage between two adjacent devices, become narrow which results in several problems occuring mainly due to the high integration of the device. The narrow isolation structure is thinner for a field oxide (FOX) layer in the narrow space between the adjacent active regions. Therefore, the FOX layer cannot effectively perform its isolation. Moreover, during the formation of the FOX layer, a bird's peak occurs at the edge of the active region so that a current leakage may occur on the gate oxide layer.

[0004] To overcome the above problem, a trench isolation structure is proposed and widely used for the semiconductor memory device with high integration, e.g., 1 Gigabit DRAM to 4 Gigabit DRAM application, wherein a trench region is formed in a silicon substrate of the semiconductor with a depth that is enough for isolating the adjacent devices.

[0005] Therefore, a method for manufacturing the conventional trench isolation comprises the steps of forming a pad oxide or nitride layer on a silicon substrate, selectively etching the pad oxide or nitride layer, and dry etching the silicon substrate by using the patterned pad oxide or the nitride layer as a mask.

[0006] The conventional trench isolation has a drawback, which is that a compressive stress concentrates on a bottom portion of the trench due to thermal budget during processes, such as annealing and other thermal treatment processes. Therefore, defects in the silicon substrate move easily so that the morphology of the trench sidewall deteriorates and dislocations occur easily. Dislocations are apt to occur more easily due to the concentration of the compressive stress around the bottom portion of the trench when the trench experiences the thermal budget.

SUMMARY OF THE INVENTION

[0007] It is, therefore, an object of the present invention to provide a method for manufacturing a trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.

[0008] In accordance with one aspect of the present invention, there is provided a method for manufacturing a trench isolation, the method comprising the steps of: a) forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; b) forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and c) forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

[0010]FIGS. 1 and 2 show cross sectional views setting forth manufacturing steps for forming a trench isolation in accordance with a preferred embodiment of the present invention; and

[0011]FIG. 3 is a schematic cross sectional view of a semiconductor device having the trench isolation structure of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] There are provided in FIGS. 1 to 3 cross sectional views setting forth a method for manufacturing a trench isolation in accordance with a preferred embodiment of the present invention. It should be noted that like parts appearing in FIGS. 1 to 3 are represented by like reference numerals.

[0013] To begin with, a silicon substrate 10 is selectively etched to form a trench profile that is capable of reducing a compressive stress geometrically around the trench profile. That is, an etching process is carried out by using a mask pattern provided with a pad oxide or nitride layer (not shown), wherein a first etching process is carried out to obtain a rounded upper portion 2 of the trench 8 under conditions of low voltage and lots of polymer, a second etching process is carried out to obtain a vertical middle portion 4 under high voltage and a small amount of polymer, and a third etching process is carried out to obtain a rounded bottom portion 6 under low voltage and lots of polymer as similar to the first etching conditions. Each etching step is illustrated in more detail hereinafter.

[0014] In the first etching step, it is performed preferably on condition that RF power is 100200 W, pressure is 5060 mTorr, flux of chlorine gas (Cl2) is 1020 sccm, and flux of nitrogen gas (N2) is 1525 sccm. Since the first etching step is performed under low RF power and N2 rich ambient to produce lots of polymer, it is possible to obtain a convex shape of a rounding profile at the upper portion 2 of the trench 8.

[0015] In the second etching step, it is performed preferably on condition that RF power is 400500 W, pressure is 3040 mTorr, flux of Cl2 is 1525 sccm, flux of sulfur hexafluoride (SF6) is 2540 sccm, and flux of N2 is 010 sccm. As the fluorine radical increases under high RF power and low pressure, a removal capability for polymer and silicon also increases. Thus, the middle portion 4 of the trench 8 becomes close to the vertical sidewall.

[0016] In the third etching step, it is performed preferably on condition that RF power is 100200 W, pressure is 5060 mTorr, flux of chlorine gas (Cl2) is 1020 sccm, and flux of nitrogen gas (N2) is 2330 sccm. Since the third etching step is performed under low RF power and N2 rich ambient to produce lots of polymer, which is similar to the first etching step, it is possible to obtain a narrow concave shape of a rounded profile at the bottom portion 6 of the trench 8.

[0017] After the third etching step, a thermal treatment, i.e., annealing, is carried out to move defects produced during the etching steps toward a surface of the trench and to release the stress concentration due to the edge profile of the trench 8. The annealing process is performed preferably at 9501,200 C. for 1040 minutes. After annealing the substrate 10 having the trench profile, the substrate 10 is washed in phosphoric acid (H3PO4) at 80120 C. so that defects on the surface of the trench 8 can be removed. To improve the removal capability, H3PO4 washing step can be repeatedly carried out two times or more.

[0018] In the next step, the defects moved toward the trench surface during the annealing process are removed by using a method of a wet oxidization to form an oxide layer and a wet etching to remove the oxide layer. Here, wet oxidization process is performed preferably on the condition that the temperature is 400500 C., oxygen gas fluxes (O2), H2 and N2 are 28 sccm, 38 sccm and 13 sccm, respectively, to form an oxide layer with a thickness ranging from approximately 100 Å to 300 Å. The wet etching process is carried out by using an etchant such as a hydro fluoride (HF) solution or a buffered oxide etchant (BOE). To improve the removal capability, the wet oxidization and etching processes can be repeatedly carried out two times or more.

[0019] In the next step, a thin nitride film 11 is deposited uniformly on the surface of the trench 8 to the thickness of approximately 20100 Å, and then, subsequently, an oxide film 12 is formed on the nitride layer 11 to the thickness of approximately 500 Å using a dry oxidization process, as shown in FIG. 2. In more detail, the formation of the nitride film 11 is performed preferably on condition that pressure is 200300 mTorr, temperature is 600700 C., concentration of NH3 and dichlorosilane (DCS) is less than 1 sccm. The formation of the oxide film 12 is performed preferably on condition that temperature is 700800 C., fluxes of O2, N2, H2 are 520 sccm, 13 sccm and 16 sccm, respectively.

[0020] Thereafter, another annealing process is carried out to release the stress concentration induced by expansion of silicon and the oxide film 12. At this time, a stress direction moves from the silicon substrate 10 to the oxide film 12 by means of the nitride film 11.

[0021] Finally, insulating material, e.g., made of polimyde or undoped polysilicon is filled into the trench and then made flat by using a method such as a chemical mechanical polishing (CMP).

[0022] Referring to FIG. 3, there is shown a semiconductor device having a trench isolation with enhanced profile to reduce the compressive stress around the bottom portion of the trench in accordance with the present invention. Here, reference numerals 13A and 13B denote transistors, 14A, 14B, 14C and 14D denote diffusion or retrograde regions, and 15 denote insulating material.

[0023] In comparison with the prior art, the present invention provides an advantage in that the enhanced trench profile permits the compressive stress to be uniformly-distributed geometrically. The trench profile has the shape of the upper portion 2, which is a wide round convex shape, and the bottom portion 6, which is a narrow rounded concave shape. The defects in the silicon substrate 10 can be removed during the annealing and the oxidization process. Furthermore, the trench surface deformation which causes the dislocation can be effectively prevented by forming the nitride film thereon. With regard to device characteristics, the dangling bond can be removed and the leakage current is also prohibited by inhibiting the penetration of impurities.

[0024] Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claim.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6800530Jan 14, 2003Oct 5, 2004International Business Machines CorporationTriple layer hard mask for gate patterning to fabricate scaled CMOS transistors
US8691696 *May 21, 2012Apr 8, 2014GlobalFoundries, Inc.Methods for forming an integrated circuit with straightened recess profile
EP1376683A1 *Jun 28, 2002Jan 2, 2004STMicroelectronics S.r.l.Process for forming trenches with oblique profile and rounded top corners
Classifications
U.S. Classification438/296, 438/714, 257/E21.549, 438/424, 438/719, 438/710
International ClassificationH01L27/108, H01L21/8242, H01L21/76, H01L21/762
Cooperative ClassificationH01L21/76232
European ClassificationH01L21/762C6
Legal Events
DateCodeEventDescription
Feb 27, 2013FPAYFee payment
Year of fee payment: 12
Feb 11, 2009FPAYFee payment
Year of fee payment: 8
Feb 17, 2005FPAYFee payment
Year of fee payment: 4
Feb 13, 2001ASAssignment
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, KI-YEUP;KANG, BYOUNG-JU;REEL/FRAME:011522/0925
Effective date: 20001212
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. KYOUNGKI-
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, KI-YEUP /AR;REEL/FRAME:011522/0925