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Publication numberUS20010005623 A1
Publication typeApplication
Application numberUS 09/741,880
Publication dateJun 28, 2001
Filing dateDec 22, 2000
Priority dateDec 24, 1999
Also published asUS6444559
Publication number09741880, 741880, US 2001/0005623 A1, US 2001/005623 A1, US 20010005623 A1, US 20010005623A1, US 2001005623 A1, US 2001005623A1, US-A1-20010005623, US-A1-2001005623, US2001/0005623A1, US2001/005623A1, US20010005623 A1, US20010005623A1, US2001005623 A1, US2001005623A1
InventorsJeong Kim, Yu Kim
Original AssigneeKim Jeong Ho, Kim Yu Chang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Forming isolating film, gate insulating film, gate electrode, film spacer, source/drain regions, forming pad polycrystalline silicon layer pattern, forming contact plug using silicon pattern as seed, forming planarization film, contact hole
US 20010005623 A1
Abstract
The present invention discloses a method for fabricating a semiconductor device. In a process for forming a contact plug, a pad polycrystalline silicon layer pattern is formed at the presumed contact region, and a contact plug is formed according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed. Accordingly, a higher contact plug is formed by improving a growth rate of the SEG process, and thus a succeeding process can be easily performed. In the SEG process, a contact property is improved by compensating for a semiconductor substrate damaged in a process for forming an insulating film spacer at the sidewalls of a gate electrode. As a result, the property and yield of the semiconductor device are remarkably improved.
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Claims(14)
What is claimed is:
1. A method for fabricating a semiconductor device, the method comprising:
forming an isolating film for defining an active region on a semiconductor substrate;
forming a gate insulating film over the whole surface of the structure;
forming on the gate insulating film a gate electrode where a mask insulating film pattern is stacked;
forming an insulating film spacer at the sidewalls of the gate electrode and the mask insulating film pattern;
forming source/drain regions at both sides of the insulating film spacer on the semiconductor substrate;
forming a pad polycrystalline silicon layer pattern on the semiconductor substrate where a bit line contact and a storage electrode contact will be formed, and at the sidewalls of the insulating film spacer;
forming a contact plug according to a selective epitaxial growth method using the pad polycrystalline silicon layer pattern as a seed;
forming a planarization film over the whole surface of the structure; and
forming a contact hole by etching the planarization film by using a contact mask for exposing the contact plug as an etching mask.
2. The method according to
claim 1
, wherein the insulating film spacer and the mask insulating film pattern are selected from the group consisting of an SiN film, SiON film, Al2O3 film, Ta2O5 film, SiCH film and SiOH film.
3. The method according to
claim 1
, wherein the pad polycrystalline silicon layer pattern is formed by depositing a pad polycrystalline silicon layer and etching the pad polycrystalline silicon layer according to at least one of a dry and a wet isotropic etching process.
4. The method according to
claim 3
, wherein the wet isotropic etching process is performed by using a mixed solution as an etchant, the mixed solution comprising HNO3, CH3COOH, HF and deionized water.
5. The method according to
claim 3
, wherein the dry isotropic etching process is performed by using a mixed gas as an etchant, the mixed gas comprising a mixture of a main etching gas selected from the group consisting of CF4, SF6, NF3, C2F6 and mixtures thereof, an oxygen containing gas, and an inert gas.
6. The method according to
claim 1
, wherein the planarization film is etched by using an perfluorocarbon containing gas for generating a large amount of polymers in order to obtain a high selection ratio in regard to the mask insulating film pattern and the insulating film spacer.
7. The method according to
claim 6
, wherein the perfluorocarbon containing gas is selected from the group consisting of C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10, C2HF5, and combinations thereof.
8. The method according to
claim 6
, wherein the planarization film is etched by using a mixed gas as an etching gas, the mixed gas comprising perfluorocarbon containing gas and an inert gas.
9. The method according to
claim 6
, wherein the planarization film is etched by using a mixed gas as an etching gas, the mixed gas comprising perfluorocarbon containing gas and a hydrogen containing gas.
10. The method according to
claim 9
, wherein the hydrogen containing gas is selected from the group consisting of CHF3, CH3F, CH2F2, CH2, CH4, C2H4, H2, and mixtures thereof.
11. The method according to
claim 9
, wherein the mixed gas further comprises an inert gas.
12. The method according to
claim 1
, wherein the planarization film is etched by using CxHyFz gas (x≧2, y≧2, z≧2) as an etching gas in order to obtain a high etching selection ratio in regard to the mask insulating film pattern and the insulating film spacer.
13. The method according to
claim 12
, wherein the planarization film is etched by using a mixed gas of the CxHyFz gas (x≧2, y≧2, z≧2) and an inert gas as an etching gas.
14. The method according to
claim 1
, wherein the contact hole comprises at least one of a bit line contact hole and a storage electrode contact hole.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for forming a pad polycrystalline silicon layer pattern at a presumed region of a contact plug for a high integration device, and forming the contact plug according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed.

[0003] 2. Description of the Background Art

[0004] Recently, the high integration of a semiconductor device has been remarkably influenced by the development of techniques for forming a fine pattern. In a method for fabricating the semiconductor device, it is essential to miniaturize a photoresist film pattern used as a mask in an etching or ion implantation process.

[0005] Resolution (R) of the photoresist film pattern is proportional to a light source wavelength (X) and a process variable (k) of a micro exposure device, and inversely proportional to a numerical aperture (NA) of the exposure device, and is given by:

R=k*λ/NA

[0006] Here, in order to improve optical resolution of the micro exposure device, the wavelength of the light source is decreased. For example, resolution of the G-line and i-line micro exposure devices, having wavelengths of 436 nm and 365 nm, respectively is limited to about 0.7 μm and 0.5 μm, respectively. Accordingly, the exposure device using a deep ultraviolet (DUV) light having a small wavelength, for example, a KrF laser of 248 nm or an ArF laser of 193 nm, is employed to form a fine pattern less than 0.5 μm. In addition, in order to improve the resolution, a method for using a phase shift mask as a photo mask has been suggested. A contrast enhancement layer (CEL) method for forming a thin film on a wafer has been suggested for enhancing an image contrast. A tri layer resist (TLR) method has been suggested for positioning an intermediate layer, such as a spin on glass (SOG) film, between two photoresist films. And a silylation method has been suggested for selectively implanting a silicon into an upper portion of a photoresist film.

[0007] According to the high integration of the semiconductor device, the size of a contact hole, which connects the upper and lower conductive interconnections, and the space between the contact hole and an adjacent interconnection are decreased, and an aspect ratio which is the ratio of diameter and depth in the contact hole is increased.

[0008] The high integration semiconductor device having multi-layer conductive interconnections requires precise alignment of masks in a contact formation process, thereby reducing a process margin.

[0009] In order to maintain a space between the contact holes, masks are formed in consideration of: misalignment tolerance in a mask alignment, lens distortion in an exposure process, critical dimension variations in mask formation and photoetching processes, and mask registration between masks.

[0010] In addition, there has been taught a self aligned contact (SAC) method for forming a contact hole according to a self alignment method to overcome a disadvantage of a lithography process.

[0011] The SAC method uses a polycrystalline silicon layer, a nitride film or an oxide nitride film as an etching barrier film. In general, the nitride film is employed as the etching barrier film.

[0012] Although not illustrated, the conventional SAC method for fabricating the semiconductor device will now be described.

[0013] Firstly, a substructure consisting of, for example, a device isolating insulating film, a gate insulating film and a metal-oxide semiconductor field effect transistor (MOSFET) having a gate electrode overlapped with a gate insulating film and a mask insulating film pattern, and source/drain regions are formed on a semiconductor substrate. An etching barrier film and an interlayer insulating film consisting of an oxide film are sequentially formed over the whole surface of the structure.

[0014] Thereafter, a photoresist film pattern exposing a presumed region for a storage electrode contact or bit line contact on the semiconductor substrate is formed on the upper side of the interlayer insulating film.

[0015] The interlayer insulating film exposed by the photoresist film pattern is dry-etched to expose the etching barrier film. Then, a contact hole is formed by etching the etching barrier film.

[0016] In the conventional SAC method for fabricating the semiconductor device, the bit line contact and the storage electrode contact are formed according to the SAC method using the nitride film or oxide nitride film. In this case, the contact is formed in a hall or T type.

[0017] In the case of the hall type contact, the overlap precision of the lithography process has a limit and the contact hole has a sloped section in the etching process of a planarization film. Thus, it is difficult to obtain a contact region. In order to overcome the disadvantages of the hall type contact, the hall type contact is transformed into the T type contact.

[0018] However, to form the T type contact a chemical mechanical polishing (CMP) process is performed several times, thereby increasing fabrication costs. In addition, the CMP process includes a complicated and difficult process for isolating a contact plug, so that it cannot achieve mass-production. Furthermore, a yield of the device is reduced.

[0019] Accordingly, there has been suggested a method for forming the contact plug according to a selective epitaxial growth (SEG) method.

[0020] However, when an insulating film spacer is formed at the sidewalls of the gate electrode, the semiconductor substrate is damaged, thereby restricting the selective epitaxial growth. That is, a growth rate of a selective epitaxial growth film has a limit. Thus, it is difficult to form the contact plug having a free height.

[0021] When the planarization film is etched to form the succeeding bit line contact or storage electrode contact, the contact plug may damage the device isolating film, thereby causing gate induced drain leakage. Accordingly, a property of the device is deteriorated, and simultaneously a yield thereof is reduced.

SUMMARY OF THE INVENTION

[0022] Therefore, there is a need to provide a method for fabricating a semiconductor device which can prevent gate induced drain leakage by forming a MOSFET, forming a pad polycrystalline silicon layer pattern at a presumed region of a contact plug, and then forming the contact plug according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed, and which can improve a contact resistance property and a device operation property by reducing a contact junction leakage current.

[0023] Accordingly, the present invention provides a method for fabricating a semiconductor device, the method including: forming an isolating film for defining an active region on a semiconductor substrate; forming a gate insulating film over the whole surface of the structure; forming on the gate insulating film a gate electrode where a mask insulating film pattern is stacked; forming an insulating film spacer at the sidewalls of the gate electrode and the mask insulating film pattern; forming source/drain regions at the both sides of the insulating film spacer on the semiconductor substrate; forming a pad polycrystalline silicon layer pattern at a presumed region for a bit line contact and a storage electrode contact on the semiconductor substrate, and at the sidewalls of the insulating film spacer; forming a contact plug according to a selective epitaxial growth method using the pad polycrystalline silicon layer pattern as a seed; forming a planarization film over the whole surface of the structure; and forming a contact hole by etching the planarization film by using a contact mask for exposing the contact plug as an etching mask.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:

[0025]FIG. 1 illustrates a layout of a semiconductor device in accordance with the present invention; and

[0026]FIG. 2A-FIG. 2F are cross-sectional views respectively illustrating sequential steps of a method for fabricating the semiconductor device, taken along line X-X′ in FIG. 1.

DETAILED DESCRIPTION

[0027] A method for fabricating a semiconductor device in accordance with the present invention will now be described in detail with reference to the accompanying drawings.

[0028] In FIG. 1, active regions 30 are spaced out by an isolating film 13. A plurality of gate electrodes 15 are aligned overlapping the active regions 30.

[0029] In FIG. 2A, the isolating film 13 is formed at a presumed device isolating region of a semiconductor substrate 11, and a gate insulating film (not shown) is formed on the upper side of the whole surface of the resultant structure.

[0030] Thereafter, a stacked structure of a gate electrode conductive layer (not shown) and a mask insulating film (not shown) is formed on the gate insulating film.

[0031] The stacked structure is etched by using a gate electrode mask as an etching mask, thereby forming a gate electrode 15 and a mask insulating film pattern 17.

[0032] An insulating film spacer 19 is formed at the sidewalls of the gate electrode 15 and the mask insulating film pattern 17, by forming an insulating film over the entire structure, and etching the front side of the resultant structure.

[0033] Here, the insulating film spacer 19 and the mask insulating film pattern 17 may be one or more films selected from the group consisting of SiN film, SiON film, Al2O3 film, Ta2O5 film, SiCH film or SiOH film.

[0034] As shown in FIG. 2B, a pad polycrystalline silicon layer 21 having a predetermined thickness is formed over the whole surface of the structure. The pad polycrystalline silicon layer 21 compensates for the semiconductor substrate 11 damaged in the process of forming the insulating film spacer 19, and is used as a seed in a succeeding process for forming a contact plug.

[0035] A first photoresist film pattern 23 for protecting the presumed regions of the bit line contact and storage electrode contact is formed at the upper portion of the pad polycrystalline silicon layer 21. At this time, the first photoresist film pattern 23 is formed between the insulating film spacers 19 at the presumed contact region of the semiconductor substrate 11.

[0036] As depicted in FIG. 2C, the pad polycrystalline silicon layer 21 is etched by using the first photoresist film pattern 23 as an etching mask, thereby forming a pad polycrystalline silicon layer 22 at the presumed contact region of the semiconductor substrate 11 and the sidewalls of the insulating film spacer 19. The pad polycrystalline silicon layer 21 is etched according to a wet isotropic etching process using a mixed solution as an etchant, the mixed solution HNO3, CH3COOH, HF and deionized water, or a dry isotropic etching process using a mixed gas as an etchant, the mixed gas comprising a mixture of a main etching gas such as CF4, SF6, NF3 or C2F6, an oxygen containing gas such as O2, CO2, CO or SO2, and an inert gas such as He, Ne, Ar or Xe.

[0037] Next, the first photoresist film pattern 23 is removed.

[0038] Referring to FIG. 2D, a contact plug 23 is formed by selectively growing an epitaxial silicon layer by using the pad polycrystalline silicon layer pattern 22 as a seed.

[0039] As illustrated in FIG. 2E, a planarization film 25 is formed over the entire surface of the structure.

[0040] Next, a second photoresist film pattern 27 for exposing a presumed region of the bit line contact in the contact plug 23 is formed on the planarization film 25.

[0041] As shown in FIG. 2F, the planarization film 25 is etched by using the second photoresist film pattern 27 as an etching mask, thereby forming a contact hole 29 for exposing the presumed region of the bit line contact in the contact plug 23.

[0042] The etching process is performed by using a perfluorocarbon containing gas for generating a large amount of polymers, or a mixed gas of the perfluorocarbon containing gas and a hydrogen containing gas.

[0043] The perfluorocarbon containing gas is selected from the group consisting of C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10 and C2HF5.

[0044] The hydrogen containing gas is selected from the group consisting of CHF3, CH3F, CH2F2, CH2, CH4, C2H4 and H2.

[0045] The etching process can be performed by adding the inert gas such as He, Ne, Ar or Xe into the perfluorocarbon containing gas and the mixed gas. In this case, an etching stop phenomenon can be overcome by improving the plasma stability and sputtering effects, so that the reproducible etching process can be carried out.

[0046] In addition, the etching process can be performed by using CxHyFz gas (x≧2, y≧2, z≧2) as an etching gas, thereby obtaining a high etching selection ratio in regard to the mask insulating film pattern 17 and the insulating film spacer 19. The etching process can be also carried out by using a mixed gas of the CxHyFz gas (x≧2, y≧2, z≧2) and the inert gas as an etching gas.

[0047] Next, the second photoresist film pattern 27 is removed.

[0048]FIGS. 2A to 2F illustrate the sequential steps of the process for forming the bit line contact hole, which can be applied to the process for forming the storage electrode contact hole.

[0049] As described above, in accordance with the method for fabricating the semiconductor device of the present invention, the pad polycrystalline silicon layer pattern is formed at the presumed contact region in the process for forming the contact plug, and the contact plug is formed according to the SEG method using the pad polycrystalline silicon layer pattern as a seed. Accordingly, the higher contact plug is formed by improving the growth rate of the SEG process, and thus a succeeding process can be easily performed. In the SEG process, the contact property is improved by compensating for the semiconductor substrate damaged in the process for forming the insulating film spacer at the sidewalls of the gate electrode. As a result, the property and yield of the semiconductor device can be remarkably improved.

[0050] As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7052983Oct 16, 2003May 30, 2006Samsung Electronics Co., Ltd.Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads
US7342275Apr 7, 2006Mar 11, 2008Samsung Electronics Co., Ltd.Semiconductor device and method of manufacturing the same
US7385242 *Jun 16, 2005Jun 10, 2008Samsung Electronics Co., Ltd.Semiconductor device having landing pad and fabrication method thereof
DE102004003315B4 *Jan 22, 2004Oct 19, 2006Samsung Electronics Co., Ltd., SuwonHalbleitervorrichtung mit elektrischem Kontakt und Verfahren zur Herstellung derselben
Classifications
U.S. Classification438/597, 257/E21.166, 438/706, 257/E21.131, 438/197, 438/607, 438/704
International ClassificationH01L21/285, H01L21/20
Cooperative ClassificationH01L21/2018, H01L21/28525
European ClassificationH01L21/285B4B
Legal Events
DateCodeEventDescription
Apr 11, 2014REMIMaintenance fee reminder mailed
Feb 26, 2010FPAYFee payment
Year of fee payment: 8
Feb 3, 2006FPAYFee payment
Year of fee payment: 4
Dec 22, 2000ASAssignment
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, JEONG HO;KIM, YU CHANG;REEL/FRAME:011401/0718;SIGNING DATES FROM 20001201 TO 20001202
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. SAN 136-1