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Publication numberUS20010006233 A1
Publication typeApplication
Application numberUS 09/771,778
Publication dateJul 5, 2001
Filing dateJan 29, 2001
Priority dateFeb 25, 1997
Also published asUS6245587, US6452209
Publication number09771778, 771778, US 2001/0006233 A1, US 2001/006233 A1, US 20010006233 A1, US 20010006233A1, US 2001006233 A1, US 2001006233A1, US-A1-20010006233, US-A1-2001006233, US2001/0006233A1, US2001/006233A1, US20010006233 A1, US20010006233A1, US2001006233 A1, US2001006233A1
InventorsDavid Vallett
Original AssigneeVallett David P.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor devices having backside probing capability
US 20010006233 A1
Abstract
Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.
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Claims(10)
What is claimed is:
1. An integrated circuit comprising: a plurality of interconnected circuits, each having a plurality of internal circuit nodes, and at least one circuit node accessing means including an insulated electrical conductor extending from a surface of the integrated circuit to a point substantially below the surface and positioned to facilitate non-invasive electrical probing of at least one preselected circuit node via the backside of the circuit.
2. An integrated circuit in accordance with
claim 1
, where the circuit node accessing means is in the form of a trench having insulated side walls and a conductive interior.
3. An integrated circuit in accordance with
claim 2
, where the insulated side walls of the trench comprise silicon dioxide and are sufficiently thick to minimize its capacitance.
4. An integrated circuit in accordance with
claim 2
, where the conductive interior of the trench comprises polycrystalline silicon doped with phosphorous.
5. A method of introducing backside probing means in an integrated circuit having a plurality of circuits to facilitate failure analysis of such integrated circuit while it is in the active or inactive state, which method comprises, patterning the trenches in a predetermined manner in the integrated circuit surface to allow electrical connection between selected node points of the integrated circuit, where the trenches are formed below the integrated circuit surface to a depth sufficient to permit ready access by non-invasive electrical probing from the backside of such surface after using at least one standard overall substrate thinning technique, followed by at least one test point, cite specific accessing technique, where the trenches are formed by:
(1) etching the in the aforesaid predetermined pattern,
(2) forming an insulating layer on the sidewalls of the resulting trenches to a thickness sufficient to minimize its capacitance, and
(3) filling the trenches with a conductive material.
6. An integrated circuit made in accordance with
claim 5
, where the backside of the surface has been thinned sufficiently to permit the use of a focused ion beam, laser-assisted etch, or chemical etching, to permit the probing of at least one preselected circuit node.
7. An integrated circuit made in accordance with the method of
claim 5
, where the backside of the integrated circuit surface can be accessed by e-beam or mechanical probing after backside probe points have been exposed by partially polishing the back surface of the integrated circuit followed by the use of focused ion beam, lased-assisted etch, or chemical etching to expose the probe points.
8. A method in accordance with
claim 5
, where the insulating layer on the sidewalls of the resulting trenches comprises silicon-dioxide, silicon-nitride, or a mixture thereof.
9. A method in accordance with
claim 5
, where the conductive material used to fill the trenches comprises polycrystalline silicon doped with phosphorous.
10. An integrated circuit comprising a silicon substrate comprising a plurality of interconnected semiconductor devices, each forming a plurality of circuits, each having a plurality of internal circuit nodes, and at least one circuit node accessing means comprising a silicon dioxide insulated trench and a doped polycrystalline silicon interior extending from the substrate surface of the integrated circuit to a point substantially below the surface of the substrate and positioned to facilitate non-invasive electrical probing of at least one preselected circuit node via the backside of the substrate.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present invention relates to integrated circuit devices having improved backside probing capability. More particularly, the present invention relates to the use of deep trenches which have been critically fabricated with respect to degree of depth and location to facilitate characterization, diagnostic testing, and potential defect detection during development, manufacture, and usage. The conductive portions of the trenches can be accessed by conventional electrical probing methods after the backside of the semiconductor chip has been subjected to standard polishing techniques, followed by milling with focused ion beam, laser-assisted etch techniques, or chemical etching.

[0003] 2. Background Art

[0004] In the manufacture of semiconductor devices, the ability to obtain waveform measurements from internal nodes has been found to be critical to carryout failure analysis and characterization. Often active surfaces of the semiconductor devices are obscured by I/O (input/output) circuits, interconnect wiring, packaging, or limitations of the probing apparatus.

[0005] During the integrated circuit development phase, early engineering hardware is often characterized by subjecting the device to various test conditions such as speed, temperature, etc. Measuring and diagnosing the performance of these devices is done by acquiring waveforms from key circuit nodes within the device such as clock lines, enable signals, address buses, and data buses. If the early engineering hardware does not perform adequately, or is non-functional, it is critical to be able to trace back signals to the source of the problem. A convenient mode of detecting such failure source is by waveform analysis. The ability to diagnose problems by waveform analysis is also necessary during manufacture and throughout the life of the product so that corrective action can be taken.

[0006] Those skilled in the art know that waveforms can be acquired from internal circuit nodes by direct-contact mechanical probing or electron-beam probing. Additional techniques such as laser-induced light also have been reported. In order to prepare a device for diagnosis, it is necessary to establish electrical contact with a tester and one or more of the numerous Input/Output (I/O) circuits in the device. In some instances, these I/O circuits are placed in the periphery of the device, or located in a manner to provide some degree of access to the device's active surface by some form of mechanical or electron beam probe during operation. However, as a result increasing circuit complexity, a trend toward higher density packaging, or the density of the I/O circuits and related probes needed to activate the device, improvments in semiconductor device structures to provide enhanced means for mechanical or electron beam probe are needed.

[0007] To facilitate electrical access to the I/O of the IC, additional circuits and pads are frequently positioned adjacent to, or on the upper-most level of the IC die. Quite frequently, such IC dies with I/O circuit elements situated on the top surface have the disadvantage of obstructing internal circuitry. Additionally, packaging methods, often referred to as a “flip-chip”, “C4”, or direct chip attach (DCA), can be attached upside-down, or flipped onto a package substrate, or directly onto a circuit board, flexible cable, or other assembly into which the IC is interconnected. As a result, the internal circuit nodes of the IC are buried and inaccessible for characterizing electrical circuit performance, performing diagnostic testing, or performing failure analysis while the IC is operating normally and in a fully functioning state.

[0008] A procedure for monitoring the fabrication of a semiconductor device using an electrical characteristic such as resistance is shown by Rostoker, U.S. Pat. No. 5,321,304. A semiconductor wafer is provided having vias through the wafer, and a contact structure at the top to provide a conductive path through the wafer. An insulating layer overlies the contact structure to signal the endpoint of chem-mech polishing. Lu et al, U.S. Pat. No. 4,688,063, incorporated herein by reference, shows the feasibility of introducing a storage capacitor in a semiconductor device in the form of a trench capacitor which is used as part of a Dynamic Random Access Memory (DRAM) cell. The trench capacitors are positioned from the surface of semiconductor device to a heavily doped region within the cell. A DRAM cell is shown which uses a field effect transistor (FET) and a trench capacitor which forms a well in the semiconductor substrate. An electrode disposed in the trench capacitor is directly connected to the source drain of the access transistor.

[0009] While exterior conductive contact structures connected to vias extending through a semiconductor wafer have been used to facilitate the polishing of such wafer, or trench capacitors have been disposed in a semiconductor substrate as part of a DRAM cell, nothing is shown by the art to satisfy the need for enhanced characterization, diagnosis, or failure analysis capability in semiconductor devices through mechanical or electron beam probe techniques, particularly from the backside of the die.

SUMMARY OF THE INVENTION

[0010] It is an aspect of the present invention therefore to provide a system for obtaining access to internal circuit nodes of fully processed and packaged integrated circuits (IC's) for the purpose of making electrical measurements to facilitate electrical characterization, diagnostic testing, and failure analysis.

[0011] It is another aspect of the present invention to provide test points which can be incorporated into the design of an IC without adversly affecting the operation of the device.

[0012] It is a further aspect of the present invention to provide internal IC test points which can be readily accessed for electrical characterization, diagnostic testing, and failure analysis.

[0013] It is an additional aspect of the present invention to provide a method for accessing internal test points through the back or reverse-side of an IC in a non-invasive manner.

[0014] Accordingly, the present invention is directed to the use of trenches in a semiconductor device which have been fabricated in preselected locations. The trenches are filled with a conductive material and are electrically connected to particular circuit nodes of the semiconductor device to provide readily accessible test points which are also suitable for backside electrical probing. Unlike a trench capacitor normally used as a memory cell in a semiconductor device, trenches used in the integrated circuit devices of the present invention are insulated on the sidewall to the extent that their performance as capacitors is substantially precluded.

[0015] There is provided by the present invention, an integrated circuit comprising a plurality of interconnected circuits, each having a plurality of internal circuit nodes, and at least one circuit node accessing means including an insulated electrical conductor extending from a surface of the integrated circuit to a point substantially below the surface and positioned to facilitate non-invasive electrical probing of at least one preselected circuit node via the backside of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features and advantages of the invention will become apparent from the following description when taken in conjunction with the accompanying drawings in which:

[0017]FIG. 1 is a plan view of a preferred embodiment of the present invention showing the placement of buried test points in a typical IC layout;

[0018]FIG. 2 is a cross-sectional view of a preferred embodiment of the invention showing the buried test points and their connection to overlying circuit elements;

[0019]FIG. 3 is a cross-sectional view of a preferred embodiment of the invention showing how the buried test points may be accessed from the back-side of the IC.

DETAILED DESCRIPTION OF THE INVENTION

[0020]FIG. 1, more particularly shows a top view portion of a typical IC layout. For example, gate elements shown at 3 are over source/drain areas shown at 1 and 2, and interconnected with a first level of wiring at 4 and a second level of wiring 5. Additional levels of wiring (not shown) are common and included as needed. Inter-level contacts or vias at 6 provide vertical connections between the various elements.

[0021] There is further shown in FIG. 1, the location of a particular test point at 7, consisting of a conductive material at 8, and an insulating layer at 9. Overall, this IC layout can be placed on a semiconductor substrate such as silicon having a thickness of several hundred microns.

[0022] With reference to FIG. 2, three test points, more specifically illustrated by 7, are shown. The test points are filled trenches that extend into substrate 10. They are composed of a conductive inner material shown by 8 and an insulating outer layer shown by 9. The conductive inner material 8 is electrically connected to the circuit elements of interest, such as wiring levels 4 or 5. The insulating outer layer 9 neutralizes any test points, for example, 7. Insulating outer layer 9 also minimizes the capacitance between the various circuit elements, 1, 2, 3, 4, and 5, and substrate 10.

[0023] Test points shown in FIG. 2, are constructed using technology well known in the semiconductor field. In the manufacture of deep trenches for isolation, or as storage capacitors for dynamic random access memory (DRAM) cells, deep trenches can be formed in a silicon substrate using reactive ion etch (RIE). An oxide layer can then be grown on the sidewalls of the trench to form an insulating layer. The resulting cavity is then filled with an appropriate material, for example, polycrystalline silicon which is highly doped with phosphorous to prevent depletion effects outside the trench depending on whether it is to be used for isolation, or as a storage capacitor. In instances where the trench is used as a storage capacitor for making DRAM's, as described for example in U.S. Pat. No. 4,688,063 to Lu et al, it is usually necessary to increase its density, while minimizing its surface area. In addition to the surface area of the trench, other factors for influencing its capacitance are the dielectric constant and thickness of the insulating material 9. Values of 40 to 100 femtofarads of capacitance are typical, with cell areas of 20 to 40 square microns, and insulator thicknesses of about 15 nanometers, using silicon-dioxide, silicon-nitride, or combinations thereof. Trenches of 3 to 10 microns deep are also typical.

[0024] While capacitance values in the afordescribed femtofarad range will have no detrimental effects on the logic signals found on most IC devices, in particular situations, such as operating at higher frequencies, it may be desirable to modify the filled trenches. In such instances, capacitance can be minimized by using a thicker insulating layer. This can be accomplished by growing a thicker layer during the oxidation step of the trench process. The use of a thicker insulating layer is also desirable to counteract the increased capacitance that may arise from the use of a larger or deeper trench. Thicknesses on the order of 150 to 250 nanometers or more would be appropriate, depending on the corresponding surface area. Trench depths of 8-12 micrometers are sufficient in order to ensure that that the test points extend significantly below any active circuit areas and are more accessible.

[0025] A two step process can be used to gain access to the test points without disturbing the operation of the IC. The first step is thinning the entire semiconductor substrate and the second is drilling, milling, or etching holes to specific test points or groups of test points. Referring to FIG. 3, a cross-section of a circuit and associated test points are shown. The original back surface of a semiconductor substrate 10 has been thinned several hundred microns by mechanical, chemical, or chemical-mechanical polishing techniques to surface 11. This enables the use of focused ion beam (FIB), laser-assisted micro-machining, or chemical etching to form a hole 12 from the polished back surface of the IC die to the tip of the desired test point or group of test points. The desired test point or group of test points is located using reflected infrared microscopy from the back surface of the IC die alone or in combination with CAD navigation software and a motorized stage to precisely position the desired test point in the focused ion beam (FIB) or laser-assisted micro-machining tool. A small portion of the insulating material at 9 is also removed thereby exposing the conductive fill material at 8 to be probed at 13 using either in contact-mode with a conductive tip, or in non-contact mode with an electron -beam.

[0026] Probing techniques are often not feasible while the IC is in operation, since the internal IC circuit nodes may be obscured by the input/output (I/O) interconnect structures, packaging material, or probe apparatus used to interface with the IC. However, in view of the advantages provided by the present invention, once the desired test point, or group of test points is exposed, it may be accessed to carry out various procedures with electron-beam or mechanical probing, such as electrical characterization, diagnostic testing, and failure analysis.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6724030 *Jan 18, 2002Apr 20, 2004Infineon Technologies North American Corp.System and method for back-side contact for trench semiconductor device characterization
US6746938 *Jun 7, 2002Jun 8, 2004Hitachi, Ltd.Manufacturing method for semiconductor device using photo sensitive polyimide etching mask to form viaholes
US7173327May 18, 2005Feb 6, 2007Tru-Si Technologies, Inc.Clock distribution networks and conductive lines in semiconductor integrated circuits
US7696609 *Dec 1, 2005Apr 13, 2010Elpida Memory, Inc.Semiconductor device comprising a memory portion and a peripheral circuit portion
US7842948Feb 27, 2004Nov 30, 2010Nvidia CorporationFlip chip semiconductor die internal signal access system and method
US8121487 *Feb 5, 2008Feb 21, 2012Honeywell International Inc.System and method for free space micro machined optical bench
US8271252Nov 8, 2007Sep 18, 2012Nvidia CorporationAutomatic verification of device models
US8357931Dec 28, 2007Jan 22, 2013Nvidia CorporationFlip chip semiconductor die internal signal access system and method
US8368416Sep 11, 2007Feb 5, 2013Nvidia CorporationIn-process system level test before surface mount
US8510616Feb 14, 2008Aug 13, 2013Nvidia CorporationScalable scan-based test architecture with reduced test time and test power
US8745200May 6, 2008Jun 3, 2014Nvidia CorporationTesting operation of processors setup to operate in different modes
US8943457Nov 24, 2008Jan 27, 2015Nvidia CorporationSimulating scan tests with reduced resources
US8951814Jan 22, 2013Feb 10, 2015Nvidia CorporationMethod of fabricating a flip chip semiconductor die with internal signal access
WO2005088715A1 *Feb 23, 2005Sep 22, 2005Nvidia CorpSystem and method pertaining to semiconductor dies
Classifications
U.S. Classification257/48, 438/667
International ClassificationG01R31/28, H01L23/58
Cooperative ClassificationG01R31/2884, H01L22/32
European ClassificationH01L22/32, G01R31/28G4
Legal Events
DateCodeEventDescription
Nov 9, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100917
Sep 17, 2010LAPSLapse for failure to pay maintenance fees
Apr 26, 2010REMIMaintenance fee reminder mailed
Nov 18, 2005FPAYFee payment
Year of fee payment: 4