US20010006233A1 - Semiconductor devices having backside probing capability - Google Patents
Semiconductor devices having backside probing capability Download PDFInfo
- Publication number
- US20010006233A1 US20010006233A1 US09/771,778 US77177801A US2001006233A1 US 20010006233 A1 US20010006233 A1 US 20010006233A1 US 77177801 A US77177801 A US 77177801A US 2001006233 A1 US2001006233 A1 US 2001006233A1
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- integrated circuit
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- backside
- trenches
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000523 sample Substances 0.000 claims abstract description 9
- 238000012360 testing method Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 15
- 238000004458 analytical method Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 238000010884 ion-beam technique Methods 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229960001866 silicon dioxide Drugs 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000003801 milling Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 11
- 238000012512 characterization method Methods 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 6
- 238000002405 diagnostic procedure Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000003745 diagnosis Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000005459 micromachining Methods 0.000 description 2
- 238000004971 IR microspectroscopy Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
- 1. Technical Field
- The present invention relates to integrated circuit devices having improved backside probing capability. More particularly, the present invention relates to the use of deep trenches which have been critically fabricated with respect to degree of depth and location to facilitate characterization, diagnostic testing, and potential defect detection during development, manufacture, and usage. The conductive portions of the trenches can be accessed by conventional electrical probing methods after the backside of the semiconductor chip has been subjected to standard polishing techniques, followed by milling with focused ion beam, laser-assisted etch techniques, or chemical etching.
- 2. Background Art
- In the manufacture of semiconductor devices, the ability to obtain waveform measurements from internal nodes has been found to be critical to carryout failure analysis and characterization. Often active surfaces of the semiconductor devices are obscured by I/O (input/output) circuits, interconnect wiring, packaging, or limitations of the probing apparatus.
- During the integrated circuit development phase, early engineering hardware is often characterized by subjecting the device to various test conditions such as speed, temperature, etc. Measuring and diagnosing the performance of these devices is done by acquiring waveforms from key circuit nodes within the device such as clock lines, enable signals, address buses, and data buses. If the early engineering hardware does not perform adequately, or is non-functional, it is critical to be able to trace back signals to the source of the problem. A convenient mode of detecting such failure source is by waveform analysis. The ability to diagnose problems by waveform analysis is also necessary during manufacture and throughout the life of the product so that corrective action can be taken.
- Those skilled in the art know that waveforms can be acquired from internal circuit nodes by direct-contact mechanical probing or electron-beam probing. Additional techniques such as laser-induced light also have been reported. In order to prepare a device for diagnosis, it is necessary to establish electrical contact with a tester and one or more of the numerous Input/Output (I/O) circuits in the device. In some instances, these I/O circuits are placed in the periphery of the device, or located in a manner to provide some degree of access to the device's active surface by some form of mechanical or electron beam probe during operation. However, as a result increasing circuit complexity, a trend toward higher density packaging, or the density of the I/O circuits and related probes needed to activate the device, improvments in semiconductor device structures to provide enhanced means for mechanical or electron beam probe are needed.
- To facilitate electrical access to the I/O of the IC, additional circuits and pads are frequently positioned adjacent to, or on the upper-most level of the IC die. Quite frequently, such IC dies with I/O circuit elements situated on the top surface have the disadvantage of obstructing internal circuitry. Additionally, packaging methods, often referred to as a “flip-chip”, “C4”, or direct chip attach (DCA), can be attached upside-down, or flipped onto a package substrate, or directly onto a circuit board, flexible cable, or other assembly into which the IC is interconnected. As a result, the internal circuit nodes of the IC are buried and inaccessible for characterizing electrical circuit performance, performing diagnostic testing, or performing failure analysis while the IC is operating normally and in a fully functioning state.
- A procedure for monitoring the fabrication of a semiconductor device using an electrical characteristic such as resistance is shown by Rostoker, U.S. Pat. No. 5,321,304. A semiconductor wafer is provided having vias through the wafer, and a contact structure at the top to provide a conductive path through the wafer. An insulating layer overlies the contact structure to signal the endpoint of chem-mech polishing. Lu et al, U.S. Pat. No. 4,688,063, incorporated herein by reference, shows the feasibility of introducing a storage capacitor in a semiconductor device in the form of a trench capacitor which is used as part of a Dynamic Random Access Memory (DRAM) cell. The trench capacitors are positioned from the surface of semiconductor device to a heavily doped region within the cell. A DRAM cell is shown which uses a field effect transistor (FET) and a trench capacitor which forms a well in the semiconductor substrate. An electrode disposed in the trench capacitor is directly connected to the source drain of the access transistor.
- While exterior conductive contact structures connected to vias extending through a semiconductor wafer have been used to facilitate the polishing of such wafer, or trench capacitors have been disposed in a semiconductor substrate as part of a DRAM cell, nothing is shown by the art to satisfy the need for enhanced characterization, diagnosis, or failure analysis capability in semiconductor devices through mechanical or electron beam probe techniques, particularly from the backside of the die.
- It is an aspect of the present invention therefore to provide a system for obtaining access to internal circuit nodes of fully processed and packaged integrated circuits (IC's) for the purpose of making electrical measurements to facilitate electrical characterization, diagnostic testing, and failure analysis.
- It is another aspect of the present invention to provide test points which can be incorporated into the design of an IC without adversly affecting the operation of the device.
- It is a further aspect of the present invention to provide internal IC test points which can be readily accessed for electrical characterization, diagnostic testing, and failure analysis.
- It is an additional aspect of the present invention to provide a method for accessing internal test points through the back or reverse-side of an IC in a non-invasive manner.
- Accordingly, the present invention is directed to the use of trenches in a semiconductor device which have been fabricated in preselected locations. The trenches are filled with a conductive material and are electrically connected to particular circuit nodes of the semiconductor device to provide readily accessible test points which are also suitable for backside electrical probing. Unlike a trench capacitor normally used as a memory cell in a semiconductor device, trenches used in the integrated circuit devices of the present invention are insulated on the sidewall to the extent that their performance as capacitors is substantially precluded.
- There is provided by the present invention, an integrated circuit comprising a plurality of interconnected circuits, each having a plurality of internal circuit nodes, and at least one circuit node accessing means including an insulated electrical conductor extending from a surface of the integrated circuit to a point substantially below the surface and positioned to facilitate non-invasive electrical probing of at least one preselected circuit node via the backside of the substrate.
- Other features and advantages of the invention will become apparent from the following description when taken in conjunction with the accompanying drawings in which:
- FIG. 1 is a plan view of a preferred embodiment of the present invention showing the placement of buried test points in a typical IC layout;
- FIG. 2 is a cross-sectional view of a preferred embodiment of the invention showing the buried test points and their connection to overlying circuit elements;
- FIG. 3 is a cross-sectional view of a preferred embodiment of the invention showing how the buried test points may be accessed from the back-side of the IC.
- FIG. 1, more particularly shows a top view portion of a typical IC layout. For example, gate elements shown at3 are over source/drain areas shown at 1 and 2, and interconnected with a first level of wiring at 4 and a second level of
wiring 5. Additional levels of wiring (not shown) are common and included as needed. Inter-level contacts or vias at 6 provide vertical connections between the various elements. - There is further shown in FIG. 1, the location of a particular test point at7, consisting of a conductive material at 8, and an insulating layer at 9. Overall, this IC layout can be placed on a semiconductor substrate such as silicon having a thickness of several hundred microns.
- With reference to FIG. 2, three test points, more specifically illustrated by7, are shown. The test points are filled trenches that extend into
substrate 10. They are composed of a conductive inner material shown by 8 and an insulating outer layer shown by 9. The conductiveinner material 8 is electrically connected to the circuit elements of interest, such aswiring levels outer layer 9 neutralizes any test points, for example, 7. Insulatingouter layer 9 also minimizes the capacitance between the various circuit elements, 1, 2, 3, 4, and 5, andsubstrate 10. - Test points shown in FIG. 2, are constructed using technology well known in the semiconductor field. In the manufacture of deep trenches for isolation, or as storage capacitors for dynamic random access memory (DRAM) cells, deep trenches can be formed in a silicon substrate using reactive ion etch (RIE). An oxide layer can then be grown on the sidewalls of the trench to form an insulating layer. The resulting cavity is then filled with an appropriate material, for example, polycrystalline silicon which is highly doped with phosphorous to prevent depletion effects outside the trench depending on whether it is to be used for isolation, or as a storage capacitor. In instances where the trench is used as a storage capacitor for making DRAM's, as described for example in U.S. Pat. No. 4,688,063 to Lu et al, it is usually necessary to increase its density, while minimizing its surface area. In addition to the surface area of the trench, other factors for influencing its capacitance are the dielectric constant and thickness of the insulating
material 9. Values of 40 to 100 femtofarads of capacitance are typical, with cell areas of 20 to 40 square microns, and insulator thicknesses of about 15 nanometers, using silicon-dioxide, silicon-nitride, or combinations thereof. Trenches of 3 to 10 microns deep are also typical. - While capacitance values in the afordescribed femtofarad range will have no detrimental effects on the logic signals found on most IC devices, in particular situations, such as operating at higher frequencies, it may be desirable to modify the filled trenches. In such instances, capacitance can be minimized by using a thicker insulating layer. This can be accomplished by growing a thicker layer during the oxidation step of the trench process. The use of a thicker insulating layer is also desirable to counteract the increased capacitance that may arise from the use of a larger or deeper trench. Thicknesses on the order of 150 to 250 nanometers or more would be appropriate, depending on the corresponding surface area. Trench depths of 8-12 micrometers are sufficient in order to ensure that that the test points extend significantly below any active circuit areas and are more accessible.
- A two step process can be used to gain access to the test points without disturbing the operation of the IC. The first step is thinning the entire semiconductor substrate and the second is drilling, milling, or etching holes to specific test points or groups of test points. Referring to FIG. 3, a cross-section of a circuit and associated test points are shown. The original back surface of a
semiconductor substrate 10 has been thinned several hundred microns by mechanical, chemical, or chemical-mechanical polishing techniques to surface 11. This enables the use of focused ion beam (FIB), laser-assisted micro-machining, or chemical etching to form ahole 12 from the polished back surface of the IC die to the tip of the desired test point or group of test points. The desired test point or group of test points is located using reflected infrared microscopy from the back surface of the IC die alone or in combination with CAD navigation software and a motorized stage to precisely position the desired test point in the focused ion beam (FIB) or laser-assisted micro-machining tool. A small portion of the insulating material at 9 is also removed thereby exposing the conductive fill material at 8 to be probed at 13 using either in contact-mode with a conductive tip, or in non-contact mode with an electron -beam. - Probing techniques are often not feasible while the IC is in operation, since the internal IC circuit nodes may be obscured by the input/output (I/O) interconnect structures, packaging material, or probe apparatus used to interface with the IC. However, in view of the advantages provided by the present invention, once the desired test point, or group of test points is exposed, it may be accessed to carry out various procedures with electron-beam or mechanical probing, such as electrical characterization, diagnostic testing, and failure analysis.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/771,778 US6452209B2 (en) | 1997-02-25 | 2001-01-29 | Semiconductor devices having backside probing capability |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US08/806,570 US5990562A (en) | 1997-02-25 | 1997-02-25 | Semiconductor devices having backside probing capability |
US09/010,881 US6078057A (en) | 1997-02-25 | 1998-01-22 | Semiconductor devices having backside probing capability |
US09/501,920 US6245587B1 (en) | 1997-02-25 | 2000-02-10 | Method for making semiconductor devices having backside probing capability |
US09/771,778 US6452209B2 (en) | 1997-02-25 | 2001-01-29 | Semiconductor devices having backside probing capability |
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US09/501,920 Division US6245587B1 (en) | 1997-02-25 | 2000-02-10 | Method for making semiconductor devices having backside probing capability |
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US20010006233A1 true US20010006233A1 (en) | 2001-07-05 |
US6452209B2 US6452209B2 (en) | 2002-09-17 |
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US09/771,778 Expired - Fee Related US6452209B2 (en) | 1997-02-25 | 2001-01-29 | Semiconductor devices having backside probing capability |
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US09/501,920 Expired - Fee Related US6245587B1 (en) | 1997-02-25 | 2000-02-10 | Method for making semiconductor devices having backside probing capability |
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US20030136993A1 (en) * | 2002-01-18 | 2003-07-24 | Infineon Technologies North America Corp. | System and method for back-side contact for trench semiconductor device characterization |
US20030197239A1 (en) * | 2002-04-18 | 2003-10-23 | Oleg Siniaguine | Clock distribution networks and conductive lines in semiconductor integrated circuits |
US6746938B2 (en) * | 2001-06-27 | 2004-06-08 | Hitachi, Ltd. | Manufacturing method for semiconductor device using photo sensitive polyimide etching mask to form viaholes |
US20050191770A1 (en) * | 2004-02-27 | 2005-09-01 | Schieck Brian S. | Flip chip semiconductor die internal signal access system and method |
US20060125060A1 (en) * | 2004-12-15 | 2006-06-15 | Elpida Memory Inc. | Semiconductor chip, and manufacturing method and application of the chip |
US20080001618A1 (en) * | 2004-08-06 | 2008-01-03 | King Marc E | In-process system level test before surface mount |
US20090125290A1 (en) * | 2007-11-08 | 2009-05-14 | Prosenjit Chatterjee | Automatic verification of device models |
US20090196623A1 (en) * | 2008-02-05 | 2009-08-06 | Honeywell International Inc. | System and method for free space micro machined optical bench |
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Publication number | Priority date | Publication date | Assignee | Title |
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US6455334B1 (en) * | 1999-09-30 | 2002-09-24 | Advanced Micro Devices, Inc. | Probe grid for integrated circuit analysis |
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US8048774B2 (en) * | 2001-10-01 | 2011-11-01 | Electro Scientific Industries, Inc. | Methods and systems for laser machining a substrate |
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Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3235461A1 (en) | 1982-09-24 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR THE CONTACT-LESS TESTING OF AN OBJECT, IN PARTICULAR OF MICROWIRD WIRES, WITH A CARPULAR RAY PROBE |
US4751458A (en) | 1984-04-02 | 1988-06-14 | American Telephone And Telegraph Company, At&T Bell Laboratories | Test pads for integrated circuit chips |
US4688063A (en) | 1984-06-29 | 1987-08-18 | International Business Machines Corporation | Dynamic ram cell with MOS trench capacitor in CMOS |
US4983544A (en) | 1986-10-20 | 1991-01-08 | International Business Machines Corporation | Silicide bridge contact process |
US4873205A (en) | 1987-12-21 | 1989-10-10 | International Business Machines Corporation | Method for providing silicide bridge contact between silicon regions separated by a thin dielectric |
US4924589A (en) | 1988-05-16 | 1990-05-15 | Leedy Glenn J | Method of making and testing an integrated circuit |
US5210599A (en) | 1988-09-30 | 1993-05-11 | Fujitsu Limited | Semiconductor device having a built-in capacitor and manufacturing method thereof |
US4888087A (en) | 1988-12-13 | 1989-12-19 | The Board Of Trustees Of The Leland Stanford Junior University | Planarized multilevel interconnection for integrated circuits |
JPH0680713B2 (en) | 1989-10-11 | 1994-10-12 | 三菱電機株式会社 | Wafer test probe card and method of manufacturing the same |
US5270261A (en) | 1991-09-13 | 1993-12-14 | International Business Machines Corporation | Three dimensional multichip package methods of fabrication |
KR940001341A (en) | 1992-06-29 | 1994-01-11 | 디. 아이. 캐플란 | Instant connection for quick electrical access to electronic devices |
US5265378A (en) * | 1992-07-10 | 1993-11-30 | Lsi Logic Corporation | Detecting the endpoint of chem-mech polishing and resulting semiconductor device |
KR0136569B1 (en) | 1992-10-24 | 1998-04-29 | 김주용 | Fabrication method of contact hole in semiconductor device |
US5316978A (en) * | 1993-03-25 | 1994-05-31 | Northern Telecom Limited | Forming resistors for intergrated circuits |
US5990562A (en) | 1997-02-25 | 1999-11-23 | International Business Machines Corporation | Semiconductor devices having backside probing capability |
US5821549A (en) | 1997-03-03 | 1998-10-13 | Schlumberger Technologies, Inc. | Through-the-substrate investigation of flip-chip IC's |
-
2000
- 2000-02-10 US US09/501,920 patent/US6245587B1/en not_active Expired - Fee Related
-
2001
- 2001-01-29 US US09/771,778 patent/US6452209B2/en not_active Expired - Fee Related
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US20090282143A1 (en) * | 2008-05-06 | 2009-11-12 | Nvidia Corporation | Testing operation of processors setup to operate in different modes |
US8745200B2 (en) | 2008-05-06 | 2014-06-03 | Nvidia Corporation | Testing operation of processors setup to operate in different modes |
US20100131910A1 (en) * | 2008-11-24 | 2010-05-27 | Nvidia Corporation | Simulating Scan Tests with Reduced Resources |
US8943457B2 (en) | 2008-11-24 | 2015-01-27 | Nvidia Corporation | Simulating scan tests with reduced resources |
EP4321882A1 (en) * | 2022-08-03 | 2024-02-14 | NXP USA, Inc. | Structure for test-point access in a semiconductor |
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US6245587B1 (en) | 2001-06-12 |
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