US20010006837A1 - Method for manufacturing a semiconductor memory device using hemispherical grain silicon - Google Patents
Method for manufacturing a semiconductor memory device using hemispherical grain silicon Download PDFInfo
- Publication number
- US20010006837A1 US20010006837A1 US09/735,626 US73562600A US2001006837A1 US 20010006837 A1 US20010006837 A1 US 20010006837A1 US 73562600 A US73562600 A US 73562600A US 2001006837 A1 US2001006837 A1 US 2001006837A1
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- United States
- Prior art keywords
- supporting layer
- patterned
- forming
- layer
- bottom electrodes
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3146—Carbon layers, e.g. diamond-like layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
Description
- The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a semiconductor memory device incorporating therein textured electrodes for implementing a high-density storage capacitor.
- As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
- To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
- In attempt to meet the demand, there have been proposed a high-density dynamic random access memory (DRAM) which incorporates bottom electrodes having textured surface morphology by forming hemispherical grain (HSG) thereon.
- One of the major shortcomings of the above-described high-density DRAM is that it requires processes for forming a nitride layer and a buffer oxide layer as an etching stop layer during the formation of the bottom electrodes.
- It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device capable of simplifying the manufacturing steps thereof by incorporating therein a carbon layer as a supporting layer.
- In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; d) removing the patterned supporting layer; e) forming hemispherical grains (HSGs) on surfaces of the bottom electrodes; f) forming capacitor dielectric films on top of the bottom electrodes; and g) forming top electrodes on top of the capacitor dielectric films, thereby obtaining a capacitor.
- The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
- FIG. 1 is a cross sectional view setting forth a semiconductor device in accordance with the present invention; and
- FIGS. 2A to2F are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention.
- There are provided in FIGS. 1 and 2A to2F a cross sectional view of a
semiconductor device 100 for use in a memory cell and cross sectional views setting forth a method for the manufacture thereof in accordance with preferred embodiments of the present invention. It should be noted that like parts appearing in FIGS. 1 and 2A to 2F are represented by like reference numerals. - In FIG. 1, there is provided a cross sectional view of the
inventive semiconductor device 100 comprising anactive matrix 10,bottom electrodes 25 provided with hemispherical grains (HSGs) 26, a capacitordielectric layer 28 and atop electrode layer 30. Theactive matrix 10 includes asilicon substrate 2, transistors formed on top of thesilicon substrate 2, anisolation region 4 for isolating the transistors,poly plugs 16, abit line 18 andword lines 20. Each of the transistors hasdiffusion regions 6, a gate oxide 8, agate line 12 and aside wall 14. - In the
semiconductor device 100, thebit line 18 is electrically connected to one of thediffusion regions 6 to apply an electric potential. Each of thebottom electrodes 26 is electrically connected to theother diffusion regions 6 through thepoly plugs 16. Although thebit line 18 actually extends in right and left directions bypassing thepoly plugs 16, the drawing does not show these parts of thebit line 18. It is preferable that thebottom electrodes 25 are made of a material such as polysilicon, amorphous silicon (a—Si) or the like. And also, each of thebottom electrodes 26 has a textured surface to enlarge the electrode surface area without increasing the lateral dimensions thereof. - FIGS. 2A to4F are schematic cross sectional views setting forth the method for manufacture of a
semiconductor memory device 100 in accordance with the present invention. - The process for manufacturing the
semiconductor device 100 begins with the preparation of anactive matrix 10 including asilicon substrate 2, anisolation region 4,diffusion regions 6, gate oxides 8,gate lines 12,side walls 14, abit line 18,poly plugs 16 and aninsulating layer 22, as shown in FIG. 2A. Thebit line 18 is electrically connected to one of thediffusion regions 6 to apply an electric potential. Each of thepoly plugs 16 is electrically connected to theother diffusion regions 6, respectively. Although thebit line 18 actually extends in right and left directions bypassing thepoly plugs 16, the drawing does not show these parts of thebit line 18. Theinsulating layer 22 is made of a material, e.g., boron-phosphor-silicate glass (BPSG). - In an ensuing step, a supporting layer, e.g., made of carbon, is formed on top of the
active matrix 10 by using a method such as a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) and patterned into a predetermined configuration, thereby obtaining a patterned supportinglayer 24, as shown in FIG. 2B. If the supporting layer is made of oxide and an etching stop layer is made of nitride, there is occurred a punch effect during the etching of the supporting layer due to its low etching ratio between the supporting layer and the etching stop layer. In the preferred embodiment, the present invention employs a carbon layer as a supporting layer to prevent theactive matrix 10 from the attack during the etching of the supporting layer without forming an additional etching stop layer. This is achieved by utilizing an O2 gas as an etchant gas. - In a following step, a
conductive layer 23 is formed on top of the patterned supportinglayer 24 and theactive matrix 10, as shown in FIG. 2C. Preferably, theconductive layer 25 is made of a material selected from a group consisting of amorphous silicon, poly silicon, Ta2O5 and TiN. In the preferred embodiment, theconductive layer 23 has a thickness ranging from approximately 400 Å to approximately 700 Å. - In the next step, a photoresist layer (not shown) is formed on the entire surface of the
conductive layer 23. The photoresist layer has a thickness ranging from approximately 8,000 Å to approximately 15,500 Å. And then, the photoresist layer and theconductive layer 23 are planarized by using a method such as a chemical mechanical polishing (CMP) or the like until the patterned supportinglayer 24 is exposed. Thereafter, the patterned supportinglayer 24 are removed by using a dry etching, thereby obtainingbottom electrode structures 25, as shown in FIG. 2D. In this case, the dry etching utilizes an O2 gas as a reaction gas. It is possible that the patterned supportinglayer 24 can be removed by using an etch-back process. - In an ensuing step, the
bottom electrode structures 25 are carried out by a seeding and an annealing processes to produce a rugged surface which has relatively large polycrystalline silicon grains of about 50 to about 250 nm, thereby obtainingbottom electrodes 26, as shown in FIG. 2E. The annealing process can include the step of dispersing a material such as polysilicon or silicon dioxide on the surfaces of thebottom electrode structures 25 for producing nucleation sites. And also, the annealing process can include the step of accumulating silicon at the nucleation sites, thereby forming the rugged surface having a rough surface morphology. The resulting surface morphology is usually comprised of relatively large polycrystallites, referred as hemispherical grain (HSG) silicon. - Thereafter, a capacitor
dielectric layer 28 and atop electrode layer 30 are formed on top of thebottom electrodes 26, successively, as shown in FIG. 2F. - By utilizing a carbon layer as a supporting layer, the present invention can manufacture a semiconductor memory device without forming an etch stop layer on top of the active matrix.
- While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1999-66676 | 1999-12-30 | ||
KR1019990066676A KR20010059284A (en) | 1999-12-30 | 1999-12-30 | A method for forming a capacitor of a semiconductor device |
KR99-66676 | 1999-12-30 |
Publications (2)
Publication Number | Publication Date |
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US20010006837A1 true US20010006837A1 (en) | 2001-07-05 |
US6444538B2 US6444538B2 (en) | 2002-09-03 |
Family
ID=19633811
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/735,626 Expired - Lifetime US6444538B2 (en) | 1999-12-30 | 2000-12-14 | Method for manufacturing a semiconductor memory device using hemispherical grain silicon |
Country Status (2)
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US (1) | US6444538B2 (en) |
KR (1) | KR20010059284A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6518612B2 (en) * | 1999-12-30 | 2003-02-11 | Hyundai Electronics Industries Co., Ltd. | Semiconductor memory device using hemispherical grain silicon for bottom electrodes |
US20050056835A1 (en) * | 2003-09-12 | 2005-03-17 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US20060001175A1 (en) * | 2003-09-12 | 2006-01-05 | Micron Technology, Inc. | Masking structure having multiple layers including an amorphous carbon layer |
US20070034928A1 (en) * | 2005-08-10 | 2007-02-15 | Micron Technology, Inc. | Capacitor structure for two-transistor dram memory cell and method of forming same |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6410955B1 (en) * | 2001-04-19 | 2002-06-25 | Micron Technology, Inc. | Comb-shaped capacitor for use in integrated circuits |
US6888217B2 (en) * | 2001-08-30 | 2005-05-03 | Micron Technology, Inc. | Capacitor for use in an integrated circuit |
KR100539268B1 (en) * | 2004-06-24 | 2005-12-27 | 삼성전자주식회사 | Method of manufacturing semiconductor memory device |
Family Cites Families (11)
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US3639121A (en) * | 1969-03-03 | 1972-02-01 | Eastman Kodak Co | Novel conducting lacquers for electrophotographic elements |
DE2227751B2 (en) * | 1972-06-07 | 1979-02-08 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Electric capacitor and process for its manufacture |
JP2681298B2 (en) * | 1989-03-20 | 1997-11-26 | 富士通株式会社 | Method for manufacturing semiconductor memory device |
US5155657A (en) * | 1991-10-31 | 1992-10-13 | International Business Machines Corporation | High area capacitor formation using material dependent etching |
KR960005251B1 (en) * | 1992-10-29 | 1996-04-23 | 삼성전자주식회사 | Manufacture of memory device |
JP2817645B2 (en) * | 1995-01-25 | 1998-10-30 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5612558A (en) * | 1995-11-15 | 1997-03-18 | Micron Technology, Inc. | Hemispherical grained silicon on refractory metal nitride |
JP3230663B2 (en) * | 1998-03-27 | 2001-11-19 | 日本電気株式会社 | Manufacturing method of cylindrical stack electrode |
JPH11289063A (en) * | 1998-04-03 | 1999-10-19 | Matsushita Electron Corp | Manufacture of semiconductor device |
JP3905977B2 (en) * | 1998-05-22 | 2007-04-18 | 株式会社東芝 | Manufacturing method of semiconductor device |
EP1001459B1 (en) * | 1998-09-09 | 2011-11-09 | Texas Instruments Incorporated | Integrated circuit comprising a capacitor and method |
-
1999
- 1999-12-30 KR KR1019990066676A patent/KR20010059284A/en not_active Application Discontinuation
-
2000
- 2000-12-14 US US09/735,626 patent/US6444538B2/en not_active Expired - Lifetime
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6518612B2 (en) * | 1999-12-30 | 2003-02-11 | Hyundai Electronics Industries Co., Ltd. | Semiconductor memory device using hemispherical grain silicon for bottom electrodes |
US20060022247A1 (en) * | 2003-09-12 | 2006-02-02 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US20060244086A1 (en) * | 2003-09-12 | 2006-11-02 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
WO2005034229A1 (en) * | 2003-09-12 | 2005-04-14 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US20060003237A1 (en) * | 2003-09-12 | 2006-01-05 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US20060001175A1 (en) * | 2003-09-12 | 2006-01-05 | Micron Technology, Inc. | Masking structure having multiple layers including an amorphous carbon layer |
US20050056835A1 (en) * | 2003-09-12 | 2005-03-17 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US7129180B2 (en) | 2003-09-12 | 2006-10-31 | Micron Technology, Inc. | Masking structure having multiple layers including an amorphous carbon layer |
US20050059262A1 (en) * | 2003-09-12 | 2005-03-17 | Zhiping Yin | Transparent amorphous carbon structure in semiconductor devices |
US7132201B2 (en) | 2003-09-12 | 2006-11-07 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US7341957B2 (en) | 2003-09-12 | 2008-03-11 | Micron Technology, Inc. | Masking structure having multiple layers including amorphous carbon layer |
US7220683B2 (en) | 2003-09-12 | 2007-05-22 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US7298024B2 (en) | 2003-09-12 | 2007-11-20 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
US20070034928A1 (en) * | 2005-08-10 | 2007-02-15 | Micron Technology, Inc. | Capacitor structure for two-transistor dram memory cell and method of forming same |
US7488664B2 (en) * | 2005-08-10 | 2009-02-10 | Micron Technology, Inc. | Capacitor structure for two-transistor DRAM memory cell and method of forming same |
Also Published As
Publication number | Publication date |
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US6444538B2 (en) | 2002-09-03 |
KR20010059284A (en) | 2001-07-06 |
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