|Publication number||US20010006843 A1|
|Application number||US 09/750,226|
|Publication date||Jul 5, 2001|
|Filing date||Dec 29, 2000|
|Priority date||Dec 29, 1999|
|Also published as||US6303481|
|Publication number||09750226, 750226, US 2001/0006843 A1, US 2001/006843 A1, US 20010006843 A1, US 20010006843A1, US 2001006843 A1, US 2001006843A1, US-A1-20010006843, US-A1-2001006843, US2001/0006843A1, US2001/006843A1, US20010006843 A1, US20010006843A1, US2001006843 A1, US2001006843A1|
|Original Assignee||Park Dong Su|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (8), Classifications (20), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 1. Field of the Invention
 The present invention relates to a method for forming a gate insulating film for a semiconductor device, and in particular to an improved method for forming a gate insulating film for a high integration semiconductor device which has a superior electric property.
 2. Description of the Background Art
 In general, in a metal oxide semiconductor field effect transistor (MOSFET), the gate electrodes are isolated from the substrate by a thin, high quality, silicon dioxide film that is referred to as the gate oxide or gate insulating film. By insulating the gate electrodes from the substrate, MOSFET devices provide reduced impedance when compared with equivalent junction effect transistors (JFET). In addition, the silicon dioxide gate insulating film is easily formed by a single and relatively brief thermal oxidation process, making the process generally suitable for even highly integrated semiconductor devices.
 However, as the level of integration of semiconductor memory devices has increased, the size of the various components that define a functional unit cell have become even more miniaturized. For a DRAM cell transistor, this has required reductions in both the thickness of the gate insulating film and the gate width. For example, advanced memory devices such as a 256M DRAM generally use a conventional gate insulating film of approximately 50 Åof silicon dioxide that is formed in a wet oxidation process at between 800 and 900° C. to obtain the necessary device properties. The minimum thickness of the silicon dioxide gate insulating film is, however, limited by the need to maintain adequate breakdown resistance and other parametric properties.
 Recently, a Ta2O5 film having a higher dielectric constant (ε of approximately 25) has been used as the gate insulating film for highly integrated memory devices as an alternative to the conventional SiO2 film. However, because the deposited Ta2O5 film has an relatively unstable stoichiometry, vacancy Ta atoms resulting from variations in the composition ratio between the component Ta and O atoms will be present in the thin film. Further, during the deposition of the Ta2O5 gate insulating film various contaminants such as carbon (C), carbon compounds (CH4, C2H4, etc.) and water vapor (H2O) may be generated and incorporated into the film. This contaminants are the result of byproduct reactions between the organic metal precursor, such as Ta(OC2H5)5 or Ta(N(CH3)2)5, and the reaction gas, typically O2 or N2O, in the deposition chamber.
 These contaminants, as well as other ions or radicals present in the film, will result in increased leakage currents and degraded dielectric properties if left untreated. In order to overcome such a disadvantage, the deposited Ta2O5 film is typically subjected to at least one low temperature thermal treatment (for example, a plasma N2O or UV-O3 treatment) and at least one high temperature thermal treatment. These thermal treatments are, however, rather complicated and can produce in other undesirable results. For example, because the Ta2O5 can act as a strong oxidizer, it can react with the silicon substrate during the high temperature thermal treatment and form a heterogeneous parasitic oxide film at the interface. This parasitic oxide film degrades the electrical properties of the Ta2O5 gate insulating film and increases the thickness of the gate insulating film.
 Accordingly, a primary object of the present invention is to provide a method for forming a gate insulating film for a semiconductor device that exhibits superior electric properties.
 Another object of the present invention is to provide a method for forming a gate insulating film for a semiconductor device that prevents degradation or deterioration of the electric properties of the resulting semiconductor device.
 Still another object of the present invention is to provide a method for forming a gate insulating film for a semiconductor device that simplifies the fabrication process.
 Still another object of the present invention is to provide a method for forming a gate insulating film for a semiconductor device that can increase the life span of the resulting products.
 In order to achieve these objects, the present invention provides a method for forming a gate insulating film for a semiconductor device including the steps of: providing a semiconductor substrate where a field oxide film for defining an active region and a device isolating region has been formed; forming an insulating film containing nitride on the exposed surface of the semiconductor substrate; forming an amorphous TaON insulating film on the insulating film; and crystallizing the amorphous TaON insulating film.
 In addition, the present invention provides a method for forming a gate insulating film for a semiconductor device, including the steps of: providing a semiconductor substrate where a field oxide film for defining an active region and a device isolating region has been formed; forming an SiN or SiON film on the exposed surface of the semiconductor substrate; forming an amorphous TaON insulating film on the SiN or SiON film; and crystallizing the amorphous TaON insulating film.
 The present invention also provides a method for forming a gate insulating film for a semiconductor device, including the steps of: providing a semiconductor substrate where a field oxide film for defining an active region and a device isolating region has been formed; forming an insulating film containing nitride on the exposed surface of the semiconductor substrate; forming an amorphous TaON insulating film on the insulating film; and crystallizing the amorphous TaON insulating film according to an annealing process.
 The above objects, and other features and advantages of the present invention will become more apparent in light of the following detailed description and the accompanying figures.
 FIGS. 1 to 5 are cross-sectional views illustrating sequential steps of a method for forming a gate insulating film for a semiconductor device in accordance with the present invention.
 Referring to FIG. 1, a field oxide film 12 is formed on a semiconductor substrate 10 to define an active region and a device isolating region according to a conventional device isolation process such as LOCOS or trench processes. As illustrated in FIG. 2, the surface of the substrate 10 in the action region is then cleaned, typically using chemicals such as HF, SC-1 (NH4OH mixture in which NH4OH+H2O2+H2O is mixtured to a rate of 1:4:20) and/or H2SO4 to remove any natural oxide film, particles, or other contaminants.
 After the surface of the substrate has been cleaned, a silicon nitride (SixNy; Si-N bond) or silicon oxynitride (SiON) film 14 is formed on the surface of the substrate. This film 14 prevents the formation of a heterogeneous oxide film having a low dielectric constant at the interface between the substrate 10 and the gate insulating film during subsequent processing such as the deposition of an amorphous TaON film. A suitable SixNy( Si-N bond) film may be formed in a low pressure chemical vapor deposition (LPCVD) chamber operating at 200 to 600° C. by forming a plasma and supplying ammonia (NH3) or forming gas (N2/H2). Alternatively, a SiON film may be formed in the low pressure chemical vapor deposition chamber at 200 to 600° C., by forming a plasma and supplying a mixture of ammonia (NH3) and oxygen (O2) (for example, a ratio of NH3:O2 is 0.5:1 to 10:1, or preferably 3:1 to 5:1) and/or N2O gas through a mass flow controller at 10 to 1000 sccm.
 A process of forming SiON film is carried out under a power of 50 to 600 W and a pressure of 0.2 to 10 torr.
 Preferably, in the formation of a SiON film, NH3 is injected into the deposition chamber for an initial period before beginning the injection of the O2 and/or N2O to further suppress formation of a parasitic oxide film on the surface of the substrate 10.
 Thus, in contrast to the conventional method, the surface of substrate 10 is nitrided (or oxynitrided) at a low temperature of 200 to 600° C. before depositing the amorphous TaON film. This nitriding (or oxynitriding) process helps maintain the electric properties the subsequent thin films and resulting device.
 As depicted in FIG. 3, an amorphous TaON film 16 is then deposited on the SiN or SiON film 14 using a LPCVD process. A gate insulating film is actually the stacked structure of the SiN or SiON film 14 and amorphous TaON film 16.
 The TaON film 16 is the product of the reaction between a tantalum-containing organic metal compound, such as Ta(OC2H5)5 or Ta(N(CH3)2)5, with reaction gases NH3 and O2 at a temperature of 300 to 600° C. The absolute and relative flow rates of the, Ta chemical vapor, NH3 and O2 gases into the LPCVD chamber are controlled to produce the desired TaON film. The process of forming TaON 16 is carried out under Ta source of 3 to 100 mg/min, NH3) of 10 to 1000 sccm and O2 of 0.1 to 10000 sccm.
 The Ta chemical vapor is typically prepared by injecting a predetermined amount of the Ta compound, either directly or in solution, into an evaporator through a mass flow controller (MFC), and evaporating it at a temperature ranging from 150 to 200° C., a power ranging from 10 to 50 W and a pressure of from 0.15 to 2 torr (in a low pressure process) or from 50 to 300 torr (in a high pressure process).
 In order to increase the density of the gate insulating film 16 and reduce the level of impurities, the deposited TaON film is annealed. This annealing process removes the carbon, carbon compounds, water, and oxygen vacancies present in the thin film and induces crystallization of the amorphous TaON film.
 This annealing process preferably utilizes either a rapid thermal process or an electric furnace to treat the wafer under an atmosphere of N2O, O2 or N2 for a period of between 0.5 to 30 minutes and at a temperature ranging from 650 to 950° C. This annealing process converts and/or removes the carbon-based contaminants as volatile carbon compounds (such as CO, CO2, CH4, C2H4) and induces crystallization of the amorphous TaON film. In addition to crystallizing the TaON film, this annealing process corrects other structural defects such as micro cracks and pinholes in the film, thereby improving the overall film homogeneity to provide an improved gate insulating film 16.
 In the alternative, the surface of the TaON gate insulating film 16 may be nitrided with a plasma treatment in an atmosphere of NH3 (or N2/H2), or oxynitrided in an atmosphere of N2O (or a mixture of N2 and O2), at a temperature ranging from 200 to 600° C. This nitriding or oxynitriding process may be performed either in-situ after the deposition of the TaON film or in a subsequent ex-situ process. If the TaON film is subjected to either the nitriding or oxynitriding process, the separate high temperature annealing process (650-900° C.) described above may be skipped. The TaON gate insulating film 16 will, however, generally be crystallized during subsequent thermal processing associated with the formation of the gate electrode.
 As illustrated in FIG. 4, a doped polysilicon film 18 that will serve as the gate electrode is then formed on the upper portion of the gate insulating film 16. The gate electrode may also include a silicide, such as a W-silicide or a Ti-silicide, that is stacked on the doped polysilicon film 18 to lower the effective gate electrode resistance.
 Referring to FIG. 5, the doped polysilicon film 18, with or without an additional silicide layer, the TaON gate insulating film 16 and the SiN or SiON film 14 are then patterned and etched using conventional photolithography and etch processes to form the gate structure. The remaining portions of the doped polysilicon film 18 a, the TaON gate insulating film 16 a and the SiN or SiON film 14 a comprise the completed gate structure.
 The method for forming the gate insulating film for the semiconductor device in accordance with the present invention provide the following advantages:
 Firstly, the dielectric constant (ε=20˜25) of the TaON film used for the gate insulating film is significantly higher than the conventional SiO2 gate insulating film. This improvement in dielectric constant allows the physical thickness of the gate insulating film to be increased while simultaneously reducing the electrical thickness when compared with a conventional gate oxide film. Thus a gate insulating film according to the present invention increases the resistance of a highly integrated semiconductor device to degraded gate performance or gate failure, thereby improving the life span of resulting products.
 In addition, as compared with the conventional Ta2O5 gate insulating film, the TaON gate insulating film has a more stable structure, and thus exhibits reduced oxidation reactivity with the silicon substrate and gate electrode. The TaON gate insulating film according to the present invention is, therefore, is resistant to externally-applied electric discharges (ESD), provides a high insulation breakdown voltage, and exhibits very low leakage currents.
 Moreover, the oxidation resistance of the interface between the silicon substrate 10 and the gate insulating film can be increased by nitriding or oxynitriding the surface of the silicon substrate 10 before depositing the TaON gate insulating film. As a result, generation of a heterogeneous oxide film is further suppressed, thereby providing improved interface properties.
 In contrast to conventional nitriding or oxynitriding processes utilizing rapid thermal treatment, the nitriding or oxynitriding processes of the present invention are performed at lower temperatures of between 200 and 600° C., thereby avoiding degradation of other electric properties. Furthermore, the nitriding or oxynitriding processes of the present invention can be performed in-situ in combination with the TaON deposition, thus eliminating the need for special or separate apparatus and providing additional simplification of the fabrication process.
 As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the embodiments is not limited to the specific details provided in the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims. All changes and modifications to the specifically described methods that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are, therefore, intended to be embraced by the appended claims.
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|US20040224531 *||May 6, 2004||Nov 11, 2004||Samsung Electronics Co., Ltd.||Method of forming an oxide layer and method of forming an oxinitride layer|
|US20050124121 *||Dec 9, 2003||Jun 9, 2005||Rotondaro Antonio L.||Anneal of high-k dielectric using NH3 and an oxidizer|
|DE102006009822A1 *||Mar 1, 2006||Sep 6, 2007||Schott Ag||Verfahren und Vorrichtung zur Plasmabehandlung von akali- und erdalkalihaltigen Oberflächen|
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|U.S. Classification||438/591, 438/287, 257/E21.194, 438/786|
|International Classification||C23C16/40, H01L21/318, H01L29/78, H01L29/51, H01L21/28, H01L21/336|
|Cooperative Classification||H01L29/518, H01L29/513, H01L21/28185, H01L21/28176, H01L21/28202|
|European Classification||H01L21/28E2C2N, H01L29/51B2, H01L21/28E2C2C, H01L21/28E2C2B, H01L29/51N|
|Mar 12, 2001||AS||Assignment|
|Mar 23, 2005||FPAY||Fee payment|
Year of fee payment: 4
|Mar 18, 2009||FPAY||Fee payment|
Year of fee payment: 8
|Mar 15, 2013||FPAY||Fee payment|
Year of fee payment: 12