US20010008308A1 - Integrated circuit chip and method for fabricating the same - Google Patents
Integrated circuit chip and method for fabricating the same Download PDFInfo
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- US20010008308A1 US20010008308A1 US09/791,077 US79107701A US2001008308A1 US 20010008308 A1 US20010008308 A1 US 20010008308A1 US 79107701 A US79107701 A US 79107701A US 2001008308 A1 US2001008308 A1 US 2001008308A1
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- circuit board
- board unit
- die
- lead frame
- pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the invention relates to an integrated circuit chip and a method for fabricating the same, more particularly to an integrated circuit chip and a method for fabricating the same that can reduce production costs and that can increase production capacity.
- FIG. 1A a die 10 having an upper surface provided with a plurality of solder pads 100 is attached to a tie bar 130 on a lead frame 13 by means of a double-side adhesive tape 12 to fix the die 10 on the lead frame 13 .
- the solder pads 100 are exposed via a bore 1300 formed in the tie bar 130 , as shown in FIG. 1D.
- FIG. 1B each of the solder pads 100 is connected electrically to a respective lead 131 of the lead frame 13 via known wire bonding techniques by means of a conductive wire 14 that extends through the bore 1300 .
- a plastic protective layer 15 is used to encapsulate the die 10 and a portion of the lead frame 13 to form an integrated circuit chip.
- the aforesaid method needs different kinds of lead frames for different kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on.
- TSOP TSOP
- SOJ SOJ
- QFP QFP
- SOP SOP
- at least one mold is prepared for each customer, thereby increasing costs.
- the main object of the present invention is to provide an integrated circuit chip and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art.
- a method for fabricating an integrated circuit chip comprises:
- FIGS. 1A to 1 C are fragmentary schematic, partly sectional views showing a conventional method for fabricating an integrated circuit chip.
- FIG. 1D is a fragmentary top view showing a lead frame used in the conventional method for fabricating an integrated circuit chip.
- FIGS. 2A to 2 D are fragmentary schematic, partly sectional views showing the first preferred embodiment of a method for fabricating an integrated circuit chip of this invention.
- FIG. 2E is a fragmentary top view showing a lead frame used in the first preferred embodiment of this invention.
- FIG. 3 is a fragmentary schematic, partly sectional view showing the second preferred embodiment of this invention.
- FIG. 4 is a fragmentary schematic, partly sectional view showing the third preferred embodiment of this invention.
- FIG. 5 is a fragmentary schematic, partly sectional view showing the fourth preferred embodiment of this invention.
- FIG. 6 is a fragmentary schematic, partly sectional view showing the fifth preferred embodiment of this invention.
- FIG. 7 is a fragmentary schematic, partly sectional view showing the sixth preferred embodiment of this invention.
- FIG. 8 is a fragmentary schematic, partly sectional view showing the seventh preferred embodiment of this invention.
- FIG. 9 is a fragmentary top view showing the seventh preferred embodiment of this invention.
- FIG. 10 is a fragmentary schematic, partly sectional view showing the eighth preferred embodiment of this invention.
- FIG. 11 is a fragmentary schematic, partly sectional view showing the ninth preferred embodiment of this invention.
- FIG. 12 is a fragmentary schematic, partly sectional view showing the tenth preferred embodiment of this invention.
- FIG. 13 is a fragmentary schematic, partly sectional view showing the eleventh preferred embodiment of this invention.
- FIG. 14 is a fragmentary schematic, partly sectional view showing the twelfth preferred embodiment of this invention.
- FIG. 15 is a fragmentary schematic, partly sectional view showing the thirteenth preferred embodiment of this invention.
- FIG. 16 is a fragmentary schematic, partly sectional view showing the fourteenth preferred embodiment of this invention.
- FIG. 17 is a fragmentary schematic, partly sectional view showing the fifteenth preferred embodiment of this invention.
- FIG. 18 is a fragmentary schematic, partly sectional view showing the sixteenth preferred embodiment of this invention.
- FIG. 19 is a fragmentary schematic, partly sectional view showing the seventeenth preferred embodiment of this invention.
- FIG. 20 is a fragmentary schematic, partly sectional view showing the eighteenth preferred embodiment of this invention.
- FIG. 21 is a fragmentary schematic, partly sectional view showing the nineteenth preferred embodiment of this invention.
- FIG. 22 is a fragmentary schematic, partly sectional view showing the twentieth preferred embodiment of this invention.
- FIG. 23 is a fragmentary schematic, partly sectional view showing the twenty-first preferred embodiment of this invention.
- FIG. 24 is a fragmentary schematic, partly sectional view showing the twenty-second preferred embodiment of this invention.
- FIG. 25 is a fragmentary schematic, partly sectional view showing the twenty-third preferred embodiment of this invention.
- FIG. 26 is a fragmentary schematic, partly sectional view showing the twenty-fourth preferred embodiment of this invention.
- an integrated circuit chip includes a circuit board unit 2 , a die 3 , a plurality of conductive wires 4 , a lead frame 5 , a conductive contact layer 51 , and a plastic protective layer 6 .
- the circuit board unit 2 has a bottom surface 200 formed with a die-receiving cavity 20 , a top surface 210 formed with a bore 21 to access the die-receiving cavity 20 , and a plurality of contact pads 22 on the top surface 210 of the circuit board unit 2 .
- the die 3 has an upper surface 300 provided with a plurality of solder pads 30 .
- the die 3 is placed inside the die-receiving cavity 20 such that the solder pads 30 are exposed via the bore 21 in the circuit board unit 2 .
- the conductive wires 4 extend through the bore 21 and wire-bond the solder pads 30 to the contact pads 22 .
- the lead frame 5 is placed on top of the circuit board unit 2 .
- the lead frame 5 has a plurality of leads 50 .
- the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 .
- the conductive contact layer 51 is formed from a silver epoxy, such as one that contains both tin and lead, or solder paste that contains tin.
- the plastic protective layer 6 is used to encapsulate the circuit board unit 2 and at least a portion of the lead frame 5 , as shown in FIG. 2E.
- FIG. 3 illustrates the second preferred embodiment of this invention, which is based on the first preferred embodiment.
- the circuit board unit 2 A is further formed with a plurality of electroplated holes 23 registered respectively with the contact pads 22 A and extending through a bottom surface of the circuit board unit 2 A.
- the lead frame 5 is placed below the circuit board unit 2 A.
- the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 A to bond leads 50 on the lead frame 5 onto the electroplated holes 23 to establish electrical connection with corresponding ones of the contact pads 22 A.
- FIG. 4 illustrates the third preferred embodiment of this invention, which is based on the first preferred embodiment.
- the circuit board unit 2 B includes a lower circuit board 25 formed with the die-receiving cavity 20 B, and an upper circuit board 24 superimposed on the lower circuit board 25 and formed with the bore 21 B.
- the upper circuit board 24 has the contact pads 22 B formed on the top surface thereof, and is further formed with first electroplated holes 240 registered respectively with the contact pads 22 B.
- the lower circuit board 25 is formed with second electroplated holes 250 registered respectively with the first electroplated holes 240 .
- FIG. 5 illustrates the fourth preferred embodiment of this invention, which is based on the first preferred embodiment.
- the circuit board unit 2 C has a top surface 21 C formed with the die-receiving cavity 20 C.
- the die 3 is placed in the die-receiving cavity 20 C.
- the upper surface 300 of the die 3 is flush with the top surface 21 C of the circuit board unit 2 C.
- FIG. 6 illustrates the fifth preferred embodiment of this invention, which is based on the fourth preferred embodiment.
- the circuit board unit 2 D is further formed with a plurality of electroplated holes 23 D registered respectively with the contact pads 22 D and extending through a bottom surface of the circuit board unit 2 D.
- the lead frame 5 is placed below the circuit board unit 2 D.
- the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 D to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 D to establish electrical connection with corresponding ones of the contact pads 22 D.
- FIG. 7 illustrates the sixth preferred embodiment of this invention, which is based on the fourth preferred embodiment.
- the circuit board unit 2 E includes a lower circuit board 25 E and an upper circuit board 24 E superimposed on the lower circuit board 25 E and formed with the die-receiving cavity 20 E.
- the upper circuit board 24 E has the contact pads 22 E formed on a top surface 21 E thereof, and is further formed with first electroplated holes 240 E registered respectively with the contact pads 22 E.
- the lower circuit board 25 E is formed with second electroplated holes 250 E registered respectively with the first electroplated holes 240 E. Circuit traces (not shown) on the bottom side of the lower circuit board 25 E can be connected to the contact pads 22 E via the holes 250 E, 240 E.
- FIGS. 8 and 9 illustrate the seventh preferred embodiment of this invention, which is based on the first preferred embodiment.
- the circuit board unit 2 F further has opposite side portions formed with a plurality of positioning notches 26 that correspond respectively to the contact pads 22 F.
- Each of leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 .
- the conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 F. The height of the resulting integrated circuit chip can thus be reduced.
- FIG. 10 illustrates the eighth preferred embodiment of this invention, which is based on the seventh preferred embodiment.
- the circuit board unit 2 G includes a lower circuit board 25 G formed with the die-receiving cavity, and an upper circuit board 24 G superimposed on the lower circuit board 25 G and formed with the bore to access the die-receiving cavity.
- the upper circuit board 24 G has the contact pads 22 G on a top surface thereof, and is further formed with first electroplated holes 240 G registered respectively with the contact pads 22 G.
- the lower circuit board 25 G is formed with second electroplated holes 250 G registered respectively with the first electroplated holes 240 G. Circuit traces (not shown) on the bottom side of the lower circuit board 25 G can be connected to the contact pads 22 G via the holes 250 G, 240 G.
- FIG. 11 illustrates the ninth preferred embodiment of this invention, which is based on the seventh preferred embodiment.
- the circuit board unit 2 H has a top surface 21 H formed with the die-receiving cavity 20 H.
- the die 3 is placed in the die-receiving cavity 20 H.
- An upper surface 300 of the die 3 is flush with the top surface 21 H of the circuit board unit 2 H.
- FIG. 12 illustrates the tenth preferred embodiment of this invention, which is based on the ninth preferred embodiment.
- the circuit board unit 2 I includes a lower circuit board 25 I and an upper circuit board 24 I superimposed on the lower circuit board 25 I and formed with the die-receiving cavity 20 I.
- the upper circuit board 24 I has the contact pads 22 I formed on a top surface 21 I thereof, and is further formed with first electroplated holes 240 I registered respectively with the contact pads 22 I.
- the lower circuit board 25 I is formed with second electroplated holes 250 I registered respectively with the first electroplated holes 240 I. Circuit traces (not shown) on the bottom side of the lower circuit board 25 I can be connected to the contact pads 22 I via the holes 250 I, 240 I.
- FIG. 13 illustrates the eleventh preferred embodiment of this invention.
- a circuit board unit 2 J has a bottom surface formed with a plurality of die-receiving cavities 20 J, and a top surface formed with a plurality of bores 21 J to access a respective one of the die-receiving cavities 20 J and further formed with a plurality of contact pads 22 J.
- Each of a number of dies 3 has an upper surface provided with a plurality of solder pads 30 .
- Each of the dies 3 is placed in a respective one of the die-receiving cavities 20 J such that the solder pads 30 on each of the dies 3 are exposed via a respective one of the bores 21 J in the circuit board unit 2 J.
- a plurality of conductive wires 4 extend through the bore 21 J and wire-bond the solder pads 30 J to the contact pads 22 J.
- a lead frame 5 is placed on top of the circuit board unit 2 J, and has a plurality of leads 50 .
- a conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 J to bond the leads SO on the lead frame 5 onto corresponding ones of the contact pads 22 J.
- a plastic protective layer 6 is used to encapsulate the circuit board unit 2 J and at least a portion of the lead frame 5 .
- FIG. 14 illustrates the twelfth preferred embodiment of this invention, which is based on the eleventh preferred embodiment.
- the circuit board unit 2 L further has opposite side portions formed with a plurality of posit ioning notches 26 L that correspond respectively to the contact pads 22 L.
- Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 L.
- the conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 L.
- FIG. 15 illustrates the thirteenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment.
- the circuit board unit 2 M has a top surface 21 M formed with a plurality of die-receiving cavities 20 M.
- Each of the dies 3 is placed in a respective one of the die-receiving cavities 20 M.
- An upper surface 300 of each die 3 is flush with the top surface 21 M of the circuit board unit 2 M.
- FIG. 16 illustrates the fourteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment.
- the circuit board unit 2 N further has opposite side portions formed with a plurality of positioning notches 26 N that correspond respectively to the contact pads 22 N.
- Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 N.
- a conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 N.
- FIG. 17 is illustrates the fifteenth preferred embodiment of this invention, which is based on the second preferred embodiment.
- first and second circuit board units 2 P that are identical in construction.
- Each of the first and second circuit board units 2 P has a bottom surface formed with a die-receiving cavity 20 P, a top surface formed with a bore 21 P to access the die-receiving cavity 20 P, and a plurality of contact pads 22 P on the top surface.
- Each of the first and second circuit board units 2 P is further formed with a plurality of electroplated holes 23 P registered respectively with the contact pads 22 P and extending through the bottom surface thereof.
- the lead frame 5 is placed between the first and second circuit board units 2 P.
- Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 P to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 P to establish electrical connection with corresponding ones of the contact pads 22 P.
- FIG. 18 is illustrates the sixteenth preferred embodiment of this invention, which is based on the fifth preferred embodiment.
- first and second circuit board units 2 Q that are identical in construction.
- Each of the first and second circuit board units 2 Q has a top surface formed with a die-receiving cavity 20 Q and a plurality of contact pads 22 Q, and a plurality of electroplated holes 23 Q that are registered-respectively with the contact pads 22 Q and that extend through a bottom surface thereof.
- the lead frame 5 is placed between the first and second circuit board units 2 P.
- Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 P to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 P to establish electrical connection with corresponding ones of the contact pads 22 P.
- FIG. 19 is illustrates the seventeenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment.
- the circuit board unit 2 R is further formed with a plurality of electroplated holes 23 R registered respectively with the contact pads 22 R and extending through a bottom surface of the circuit board unit 2 R.
- the lead frame 5 is placed below the circuit board unit 2 R.
- the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 R to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 R to establish electrical connection with corresponding ones of the contact pads 22 R.
- FIG. 20 is illustrates the eighteenth preferred embodiment of this invention, which is based on the seventeenth preferred embodiment.
- first and second circuit board units 2 S that are identical in construction.
- Each of the first and second circuit board units 2 S is formed with a plurality of electroplated holes 23 S registered respectively with the contact pads 22 S and extending through a bottom surface thereof.
- the lead frame 5 is placed between the first and second circuit board units 2 S.
- Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 S to bond the leads 50 on the lead 5 frame 5 onto respective ones of the electroplated holes 23 S to establish electrical connection with corresponding ones of the contact pads 22 S.
- FIG. 21 illustrates the nineteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment.
- the circuit board unit 2 T is further formed with a plurality of electroplated holes 23 T registered respectively with the contact pads 22 T and extending through a bottom surface of the circuit board unit 2 T.
- the lead frame 5 is placed below the circuit board unit 2 T.
- the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 T to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 T to establish electrical connection with corresponding ones of the contact pads 22 T.
- FIG. 22 is illustrates the twentieth preferred embodiment of this invention, which is based on the nineteenth preferred embodiment.
- first and second circuit board units 2 U that are identical in construction.
- Each of the first and second circuit board units 2 U is formed with a plurality of electroplated holes 23 U registered respectively with the contact pads 22 U and extending through a bottom surface thereof.
- the lead frame 5 is placed between the first and second circuit board units 2 U.
- Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 U to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 U to establish electrical connection with corresponding ones of the contact pads 22 U.
- FIG. 23 illustrates the twenty-first preferred embodiment of this invention.
- a circuit board unit 2 V has a top surface formed with a bore 21 V and a plurality of contact pads 22 V.
- a die 3 has an upper surface provided with a plurality of solder pads 30 .
- the die 3 is attached to a bottom surface of the circuit board unit 2 V by an adhesive layer 27 such that the solder pads 30 on the die 3 are exposed via the bore 21 V in the circuit board unit 2 V.
- a plurality of conductive wires 4 extend through the bore 21 V and wire-bond the solder pads 30 to the contact pads 22 V.
- a lead frame 5 is placed on top of the circuit board unit 2 V and has a plurality of leads 50 .
- a conductive contact layer 51 bonds the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 V.
- a plastic protective layer 6 is used to encapsulate the circuit board unit 2 V and at least a portion of the lead frame 5 .
- FIG. 24 illustrates the twenty-second preferred embodiment of this invention, which is based on the twenty-first preferred embodiment.
- the circuit board unit 2 W further has opposite side portions formed with a plurality of positioning notches 26 W that correspond respectively to the contact pads 22 W.
- Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 W.
- a conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 W.
- FIG. 25 illustrates the twenty-third preferred embodiment of this invention, which is based on the twenty-first preferred embodiment.
- the circuit board unit 2 X is further formed with a plurality of electroplated holes 23 X registered respectively with the contact pads 22 X and extending through a bottom surface of the circuit board unit 2 X.
- the lead frame 5 is placed below the circuit board unit 2 X.
- the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 X to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 X to establish electrical connection with corresponding ones of the contact pads 22 X.
- FIG. 26 illustrates the twenty-fourth preferred embodiment of this invention, which is based on the twenty-third preferred embodiment.
- first and second circuit board units 2 Y that are identical in construction.
- Each of the first and second circuit board units 2 Y is formed with a plurality of electroplated holes 23 Y registered respectively with the contact pads 22 Y and extending through a bottom surface thereof.
- the lead frame 5 is placed between the first and second circuit board units 2 Y.
- Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 Y to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 Y to establish electrical connection with corresponding ones of the contact pads 22 Y.
Abstract
Description
- 1. Field of the Invention
- The invention relates to an integrated circuit chip and a method for fabricating the same, more particularly to an integrated circuit chip and a method for fabricating the same that can reduce production costs and that can increase production capacity.
- 2. Description of the Related Art
- Referring to Figs. 1A to1C, a conventional method for fabricating an integrated circuit chip is shown. As shown in FIG. 1A, a die 10 having an upper surface provided with a plurality of
solder pads 100 is attached to atie bar 130 on alead frame 13 by means of a double-sideadhesive tape 12 to fix thedie 10 on thelead frame 13. Thesolder pads 100 are exposed via abore 1300 formed in thetie bar 130, as shown in FIG. 1D. Referring to FIG. 1B, each of thesolder pads 100 is connected electrically to arespective lead 131 of thelead frame 13 via known wire bonding techniques by means of aconductive wire 14 that extends through thebore 1300. Referring to FIG. 1C, a plasticprotective layer 15 is used to encapsulate thedie 10 and a portion of thelead frame 13 to form an integrated circuit chip. - The following are some of the drawbacks of the conventional method for fabricating an integrated circuit chip:
- 1. The aforesaid method needs different kinds of lead frames for different kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on. Thus, at least one mold is prepared for each customer, thereby increasing costs.
- 2. In the aforesaid method, double-side adhesive tape is needed to secure the die on the tie bar, thereby increasing the fabricating costs.
- 3. In the aforesaid method, it will take a long time to form the molds for the lead frames, thereby affecting the ability of manufacturers to compete.
- Therefore, the main object of the present invention is to provide an integrated circuit chip and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art.
- According to this invention, a method for fabricating an integrated circuit chip comprises:
- (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit;
- (b) forming a die having an upper surface provided with a plurality of solder pads;
- (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed;
- (d) wire-bonding the solder pads to the contact pads via conductive wires;
- (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and
- (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
- Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:
- FIGS. 1A to1C are fragmentary schematic, partly sectional views showing a conventional method for fabricating an integrated circuit chip.
- FIG. 1D is a fragmentary top view showing a lead frame used in the conventional method for fabricating an integrated circuit chip.
- FIGS. 2A to2D are fragmentary schematic, partly sectional views showing the first preferred embodiment of a method for fabricating an integrated circuit chip of this invention.
- FIG. 2E is a fragmentary top view showing a lead frame used in the first preferred embodiment of this invention.
- FIG. 3 is a fragmentary schematic, partly sectional view showing the second preferred embodiment of this invention.
- FIG. 4 is a fragmentary schematic, partly sectional view showing the third preferred embodiment of this invention.
- FIG. 5 is a fragmentary schematic, partly sectional view showing the fourth preferred embodiment of this invention.
- FIG. 6 is a fragmentary schematic, partly sectional view showing the fifth preferred embodiment of this invention.
- FIG. 7 is a fragmentary schematic, partly sectional view showing the sixth preferred embodiment of this invention.
- FIG. 8 is a fragmentary schematic, partly sectional view showing the seventh preferred embodiment of this invention.
- FIG. 9 is a fragmentary top view showing the seventh preferred embodiment of this invention.
- FIG. 10 is a fragmentary schematic, partly sectional view showing the eighth preferred embodiment of this invention.
- FIG. 11 is a fragmentary schematic, partly sectional view showing the ninth preferred embodiment of this invention.
- FIG. 12 is a fragmentary schematic, partly sectional view showing the tenth preferred embodiment of this invention.
- FIG. 13 is a fragmentary schematic, partly sectional view showing the eleventh preferred embodiment of this invention.
- FIG. 14 is a fragmentary schematic, partly sectional view showing the twelfth preferred embodiment of this invention.
- FIG. 15 is a fragmentary schematic, partly sectional view showing the thirteenth preferred embodiment of this invention.
- FIG. 16 is a fragmentary schematic, partly sectional view showing the fourteenth preferred embodiment of this invention.
- FIG. 17 is a fragmentary schematic, partly sectional view showing the fifteenth preferred embodiment of this invention.
- FIG. 18 is a fragmentary schematic, partly sectional view showing the sixteenth preferred embodiment of this invention.
- FIG. 19 is a fragmentary schematic, partly sectional view showing the seventeenth preferred embodiment of this invention.
- FIG. 20 is a fragmentary schematic, partly sectional view showing the eighteenth preferred embodiment of this invention.
- FIG. 21 is a fragmentary schematic, partly sectional view showing the nineteenth preferred embodiment of this invention.
- FIG. 22 is a fragmentary schematic, partly sectional view showing the twentieth preferred embodiment of this invention.
- FIG. 23 is a fragmentary schematic, partly sectional view showing the twenty-first preferred embodiment of this invention.
- FIG. 24 is a fragmentary schematic, partly sectional view showing the twenty-second preferred embodiment of this invention.
- FIG. 25 is a fragmentary schematic, partly sectional view showing the twenty-third preferred embodiment of this invention.
- FIG. 26 is a fragmentary schematic, partly sectional view showing the twenty-fourth preferred embodiment of this invention.
- Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure.
- Referring to FIGS. 2A to2E, according to the first preferred embodiment of this invention, an integrated circuit chip includes a
circuit board unit 2, adie 3, a plurality ofconductive wires 4, alead frame 5, aconductive contact layer 51, and a plasticprotective layer 6. Referring to FIGS. 2A and 2B, thecircuit board unit 2 has abottom surface 200 formed with a die-receivingcavity 20, atop surface 210 formed with abore 21 to access the die-receivingcavity 20, and a plurality ofcontact pads 22 on thetop surface 210 of thecircuit board unit 2. Thedie 3 has anupper surface 300 provided with a plurality ofsolder pads 30. Thedie 3 is placed inside the die-receivingcavity 20 such that thesolder pads 30 are exposed via thebore 21 in thecircuit board unit 2. Referring to FIG. 2C, theconductive wires 4 extend through thebore 21 and wire-bond thesolder pads 30 to thecontact pads 22. Referring to FIGS. 2C and 2D, thelead frame 5 is placed on top of thecircuit board unit 2. Thelead frame 5 has a plurality of leads 50. Theconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2 to bond the leads 50 on thelead frame 5 onto corresponding ones of thecontact pads 22. Theconductive contact layer 51 is formed from a silver epoxy, such as one that contains both tin and lead, or solder paste that contains tin. The plasticprotective layer 6 is used to encapsulate thecircuit board unit 2 and at least a portion of thelead frame 5, as shown in FIG. 2E. - FIG. 3 illustrates the second preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 3, unlike the first preferred embodiment shown in of FIG. 2D, the
circuit board unit 2A is further formed with a plurality of electroplatedholes 23 registered respectively with thecontact pads 22A and extending through a bottom surface of thecircuit board unit 2A. Thelead frame 5 is placed below thecircuit board unit 2A. Theconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2A to bond leads 50 on thelead frame 5 onto the electroplatedholes 23 to establish electrical connection with corresponding ones of thecontact pads 22A. - FIG. 4 illustrates the third preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 4, unlike the first preferred embodiment shown in FIG. 2D, the
circuit board unit 2B includes alower circuit board 25 formed with the die-receivingcavity 20B, and anupper circuit board 24 superimposed on thelower circuit board 25 and formed with thebore 21B. Theupper circuit board 24 has thecontact pads 22B formed on the top surface thereof, and is further formed with first electroplated holes 240 registered respectively with thecontact pads 22B. Thelower circuit board 25 is formed with second electroplated holes 250 registered respectively with the first electroplated holes 240. Thus, circuit traces (not shown) on the bottom side of thelower circuit board 25 can be connected to theleads 50 of thelead frame 5 via the holes 250, 240 and thecontact pads 22B. FIG. 5 illustrates the fourth preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 5, unlike the first preferred embodiment shown in FIG. 2D, thecircuit board unit 2C has atop surface 21C formed with the die-receivingcavity 20C. Thedie 3 is placed in the die-receivingcavity 20C. Theupper surface 300 of thedie 3 is flush with thetop surface 21C of thecircuit board unit 2C. - FIG. 6 illustrates the fifth preferred embodiment of this invention, which is based on the fourth preferred embodiment. In FIG. 6, unlike the fourth preferred embodiment shown in FIG. 5, the
circuit board unit 2D is further formed with a plurality of electroplatedholes 23D registered respectively with thecontact pads 22D and extending through a bottom surface of thecircuit board unit 2D. Thelead frame 5 is placed below thecircuit board unit 2D. Theconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2D to bond the leads 50 on thelead frame 5 onto the electroplatedholes 23D to establish electrical connection with corresponding ones of thecontact pads 22D. - FIG. 7 illustrates the sixth preferred embodiment of this invention, which is based on the fourth preferred embodiment. In FIG. 7, unlike the fourth preferred embodiment shown in FIG. 5, the
circuit board unit 2E includes a lower circuit board 25E and anupper circuit board 24E superimposed on the lower circuit board 25E and formed with the die-receivingcavity 20E. Theupper circuit board 24E has thecontact pads 22E formed on atop surface 21E thereof, and is further formed with firstelectroplated holes 240E registered respectively with thecontact pads 22E. The lower circuit board 25E is formed with secondelectroplated holes 250E registered respectively with the first electroplated holes 240E. Circuit traces (not shown) on the bottom side of the lower circuit board 25E can be connected to thecontact pads 22E via theholes - FIGS. 8 and 9 illustrate the seventh preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 8, unlike the first preferred embodiment shown in FIG. 2D, the
circuit board unit 2F further has opposite side portions formed with a plurality ofpositioning notches 26 that correspond respectively to thecontact pads 22F. Each ofleads 50 on thelead frame 5 has one end inserted into a respective one of thepositioning notches 26. Theconductive contact layer 51 is used to bond the leads 50 on thelead frame 5 onto corresponding ones of thecontact pads 22F. The height of the resulting integrated circuit chip can thus be reduced. - FIG. 10 illustrates the eighth preferred embodiment of this invention, which is based on the seventh preferred embodiment. In FIG. 10, unlike the seventh preferred embodiment shown in FIG. 8, the
circuit board unit 2G includes alower circuit board 25G formed with the die-receiving cavity, and anupper circuit board 24G superimposed on thelower circuit board 25G and formed with the bore to access the die-receiving cavity. Theupper circuit board 24G has thecontact pads 22G on a top surface thereof, and is further formed with firstelectroplated holes 240G registered respectively with thecontact pads 22G. Thelower circuit board 25G is formed with secondelectroplated holes 250G registered respectively with the first electroplated holes 240G. Circuit traces (not shown) on the bottom side of thelower circuit board 25G can be connected to thecontact pads 22G via theholes - FIG. 11 illustrates the ninth preferred embodiment of this invention, which is based on the seventh preferred embodiment. In FIG. 11, unlike the seventh preferred embodiment shown in FIG. 8, the
circuit board unit 2H has atop surface 21H formed with the die-receivingcavity 20H. Thedie 3 is placed in the die-receivingcavity 20H. Anupper surface 300 of thedie 3 is flush with thetop surface 21H of thecircuit board unit 2H. - FIG. 12 illustrates the tenth preferred embodiment of this invention, which is based on the ninth preferred embodiment. In FIG. 12, unlike the ninth preferred embodiment shown in FIG. 11, the circuit board unit2I includes a lower circuit board 25I and an upper circuit board 24I superimposed on the lower circuit board 25I and formed with the die-receiving cavity 20I. The upper circuit board 24I has the contact pads 22I formed on a top surface 21I thereof, and is further formed with first electroplated holes 240I registered respectively with the contact pads 22I. The lower circuit board 25I is formed with second electroplated holes 250I registered respectively with the first electroplated holes 240I. Circuit traces (not shown) on the bottom side of the lower circuit board 25I can be connected to the contact pads 22I via the holes 250I, 240I.
- FIG. 13 illustrates the eleventh preferred embodiment of this invention. In this embodiment, a
circuit board unit 2J has a bottom surface formed with a plurality of die-receivingcavities 20J, and a top surface formed with a plurality ofbores 21J to access a respective one of the die-receivingcavities 20J and further formed with a plurality ofcontact pads 22J. Each of a number of dies 3 has an upper surface provided with a plurality ofsolder pads 30. Each of the dies 3 is placed in a respective one of the die-receivingcavities 20J such that thesolder pads 30 on each of the dies 3 are exposed via a respective one of thebores 21J in thecircuit board unit 2J. A plurality ofconductive wires 4 extend through thebore 21J and wire-bond the solder pads 30J to thecontact pads 22J. Alead frame 5 is placed on top of thecircuit board unit 2J, and has a plurality of leads 50. Aconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2J to bond the leads SO on thelead frame 5 onto corresponding ones of thecontact pads 22J. Finally, a plasticprotective layer 6 is used to encapsulate thecircuit board unit 2J and at least a portion of thelead frame 5. Thus, surface mounting steps are reduced to enhance the production capacity. - FIG. 14 illustrates the twelfth preferred embodiment of this invention, which is based on the eleventh preferred embodiment. In FIG. 14, unlike the eleventh preferred embodiment shown in FIG. 13, the
circuit board unit 2L further has opposite side portions formed with a plurality ofposit ioning notches 26L that correspond respectively to thecontact pads 22L. Each of theleads 50 on thelead frame 5 has one end inserted into a respective one of thepositioning notches 26L. Theconductive contact layer 51 is used to bond the leads 50 on thelead frame 5 onto corresponding ones of thecontact pads 22L. - FIG. 15 illustrates the thirteenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment. In FIG. 15, unlike the eleventh preferred embodiment shown in FIG. 13, the
circuit board unit 2M has atop surface 21M formed with a plurality of die-receivingcavities 20M. Each of the dies 3 is placed in a respective one of the die-receivingcavities 20M. Anupper surface 300 of each die 3 is flush with thetop surface 21M of thecircuit board unit 2M. - FIG. 16 illustrates the fourteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment. In FIG. 16, unlike the thirteenth preferred embodiment shown in FIG. 15, the
circuit board unit 2N further has opposite side portions formed with a plurality ofpositioning notches 26N that correspond respectively to thecontact pads 22N. Each of theleads 50 on thelead frame 5 has one end inserted into a respective one of thepositioning notches 26N. Aconductive contact layer 51 is used to bond the leads 50 on thelead frame 5 onto corresponding ones of thecontact pads 22N. - FIG. 17 is illustrates the fifteenth preferred embodiment of this invention, which is based on the second preferred embodiment. In FIG. 17, unlike the second preferred embodiment shown in FIG. 3, there are first and second
circuit board units 2P that are identical in construction. Each of the first and secondcircuit board units 2P has a bottom surface formed with a die-receivingcavity 20P, a top surface formed with abore 21P to access the die-receivingcavity 20P, and a plurality ofcontact pads 22P on the top surface. Each of the first and secondcircuit board units 2P is further formed with a plurality of electroplatedholes 23P registered respectively with thecontact pads 22P and extending through the bottom surface thereof. Thelead frame 5 is placed between the first and secondcircuit board units 2P. Each of two conductive contact layers 51 is disposed between thelead frame 5 and a respective one of the first and secondcircuit board units 2P to bond the leads 50 on thelead frame 5 onto respective ones of the electroplatedholes 23P to establish electrical connection with corresponding ones of thecontact pads 22P. - FIG. 18 is illustrates the sixteenth preferred embodiment of this invention, which is based on the fifth preferred embodiment. In FIG. 18, unlike the fifth preferred embodiment shown in FIG. 6, there are first and second
circuit board units 2Q that are identical in construction. Each of the first and secondcircuit board units 2Q has a top surface formed with a die-receivingcavity 20Q and a plurality ofcontact pads 22Q, and a plurality of electroplatedholes 23Q that are registered-respectively with thecontact pads 22Q and that extend through a bottom surface thereof. Thelead frame 5 is placed between the first and secondcircuit board units 2P. Each of two conductive contact layers 51 is disposed between thelead frame 5 and a respective one of the first and secondcircuit board units 2P to bond the leads 50 on thelead frame 5 onto respective ones of the electroplatedholes 23P to establish electrical connection with corresponding ones of thecontact pads 22P. - FIG. 19 is illustrates the seventeenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment. In FIG. 19, unlike the eleventh preferred embodiment shown in FIG. 13, the
circuit board unit 2R is further formed with a plurality of electroplatedholes 23R registered respectively with thecontact pads 22R and extending through a bottom surface of thecircuit board unit 2R. Thelead frame 5 is placed below thecircuit board unit 2R. Theconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2R to bond the leads 50 on thelead frame 5 onto the electroplatedholes 23R to establish electrical connection with corresponding ones of thecontact pads 22R. - FIG. 20 is illustrates the eighteenth preferred embodiment of this invention, which is based on the seventeenth preferred embodiment. In FIG. 20, unlike the seventeenth preferred embodiment shown in FIG. 19, there are first and second circuit board units2S that are identical in construction. Each of the first and second circuit board units 2S is formed with a plurality of electroplated holes 23S registered respectively with the contact pads 22S and extending through a bottom surface thereof. The
lead frame 5 is placed between the first and second circuit board units 2S. Each of two conductive contact layers 51 is disposed between thelead frame 5 and a respective one of the first and second circuit board units 2S to bond the leads 50 on thelead 5frame 5 onto respective ones of the electroplated holes 23S to establish electrical connection with corresponding ones of the contact pads 22S. - FIG. 21 illustrates the nineteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment. In FIG. 21, unlike the thirteenth preferred embodiment shown in FIG. 1S, the
circuit board unit 2T is further formed with a plurality of electroplatedholes 23T registered respectively with thecontact pads 22T and extending through a bottom surface of thecircuit board unit 2T. Thelead frame 5 is placed below thecircuit board unit 2T. Theconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2T to bond the leads 50 on thelead frame 5 onto the electroplatedholes 23T to establish electrical connection with corresponding ones of thecontact pads 22T. - FIG. 22 is illustrates the twentieth preferred embodiment of this invention, which is based on the nineteenth preferred embodiment. In FIG. 22, unlike the nineteenth preferred embodiment shown in FIG. 19, there are first and second circuit board units2U that are identical in construction. Each of the first and second circuit board units 2U is formed with a plurality of electroplated
holes 23U registered respectively with thecontact pads 22U and extending through a bottom surface thereof. Thelead frame 5 is placed between the first and second circuit board units 2U. Each of two conductive contact layers 51 is disposed between thelead frame 5 and a respective one of the first and second circuit board units 2U to bond the leads 50 on thelead frame 5 onto respective ones of the electroplatedholes 23U to establish electrical connection with corresponding ones of thecontact pads 22U. - FIG. 23 illustrates the twenty-first preferred embodiment of this invention. In this embodiment, a circuit board unit2V has a top surface formed with a
bore 21V and a plurality ofcontact pads 22V. Adie 3 has an upper surface provided with a plurality ofsolder pads 30. Thedie 3 is attached to a bottom surface of the circuit board unit 2V by anadhesive layer 27 such that thesolder pads 30 on thedie 3 are exposed via thebore 21V in the circuit board unit 2V. A plurality ofconductive wires 4 extend through thebore 21V and wire-bond thesolder pads 30 to thecontact pads 22V. Alead frame 5 is placed on top of the circuit board unit 2V and has a plurality of leads 50. Aconductive contact layer 51 bonds theleads 50 on thelead frame 5 onto corresponding ones of thecontact pads 22V. Finally, a plasticprotective layer 6 is used to encapsulate the circuit board unit 2V and at least a portion of thelead frame 5. - FIG. 24 illustrates the twenty-second preferred embodiment of this invention, which is based on the twenty-first preferred embodiment. In FIG. 24, unlike the twenty-first preferred embodiment shown in FIG. 23, the
circuit board unit 2W further has opposite side portions formed with a plurality ofpositioning notches 26W that correspond respectively to thecontact pads 22W. Each of theleads 50 on thelead frame 5 has one end inserted into a respective one of thepositioning notches 26W. Aconductive contact layer 51 is used to bond the leads 50 on thelead frame 5 onto corresponding ones of thecontact pads 22W. - FIG. 25 illustrates the twenty-third preferred embodiment of this invention, which is based on the twenty-first preferred embodiment. In FIG. 25, unlike the twenty-first preferred embodiment shown in FIG. 23, the
circuit board unit 2X is further formed with a plurality of electroplatedholes 23X registered respectively with the contact pads 22X and extending through a bottom surface of thecircuit board unit 2X. Thelead frame 5 is placed below thecircuit board unit 2X. Theconductive contact layer 51 is disposed between thelead frame 5 and thecircuit board unit 2X to bond the leads 50 on thelead frame 5 onto the electroplatedholes 23X to establish electrical connection with corresponding ones of the contact pads 22X. - FIG. 26 illustrates the twenty-fourth preferred embodiment of this invention, which is based on the twenty-third preferred embodiment. In FIG. 26, unlike the twenty-third preferred embodiment shown in FIG. 25, there are first and second circuit board units2Y that are identical in construction. Each of the first and second circuit board units 2Y is formed with a plurality of electroplated
holes 23Y registered respectively with thecontact pads 22Y and extending through a bottom surface thereof. Thelead frame 5 is placed between the first and second circuit board units 2Y. Each of two conductive contact layers 51 is disposed between thelead frame 5 and a respective one of the first and second circuit board units 2Y to bond the leads 50 on thelead frame 5 onto respective ones of the electroplatedholes 23Y to establish electrical connection with corresponding ones of thecontact pads 22Y. - While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Claims (90)
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US09/791,137 Expired - Fee Related US6429535B2 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip and method for fabricating the same |
US09/791,082 Abandoned US20010005038A1 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip and method for fabricating the same |
US09/791,076 Expired - Lifetime US6670707B2 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip |
US09/791,077 Expired - Fee Related US6429514B2 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip and method for fabricating the same |
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US09/791,094 Expired - Lifetime US6534344B2 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip and method for fabricating the same |
US09/791,137 Expired - Fee Related US6429535B2 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip and method for fabricating the same |
US09/791,082 Abandoned US20010005038A1 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip and method for fabricating the same |
US09/791,076 Expired - Lifetime US6670707B2 (en) | 1998-10-27 | 2001-02-22 | Integrated circuit chip |
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US5811879A (en) * | 1996-06-26 | 1998-09-22 | Micron Technology, Inc. | Stacked leads-over-chip multi-chip module |
JPH10223819A (en) * | 1997-02-13 | 1998-08-21 | Nec Kyushu Ltd | Semiconductor device |
US6107683A (en) * | 1997-06-20 | 2000-08-22 | Substrate Technologies Incorporated | Sequentially built integrated circuit package |
US6245594B1 (en) * | 1997-08-05 | 2001-06-12 | Micron Technology, Inc. | Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly |
US5899705A (en) * | 1997-11-20 | 1999-05-04 | Akram; Salman | Stacked leads-over chip multi-chip module |
US5998860A (en) * | 1997-12-19 | 1999-12-07 | Texas Instruments Incorporated | Double sided single inline memory module |
US5952611A (en) * | 1997-12-19 | 1999-09-14 | Texas Instruments Incorporated | Flexible pin location integrated circuit package |
-
1998
- 1998-10-27 TW TW087117753A patent/TW368707B/en active
-
1999
- 1999-04-06 JP JP11098712A patent/JP3025685B1/en not_active Expired - Fee Related
- 1999-04-30 US US09/303,142 patent/US6271586B1/en not_active Expired - Fee Related
- 1999-06-28 DE DE19929606A patent/DE19929606A1/en not_active Withdrawn
-
2001
- 2001-02-22 US US09/791,094 patent/US6534344B2/en not_active Expired - Lifetime
- 2001-02-22 US US09/791,137 patent/US6429535B2/en not_active Expired - Fee Related
- 2001-02-22 US US09/791,082 patent/US20010005038A1/en not_active Abandoned
- 2001-02-22 US US09/791,076 patent/US6670707B2/en not_active Expired - Lifetime
- 2001-02-22 US US09/791,077 patent/US6429514B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6498389B1 (en) * | 2001-07-16 | 2002-12-24 | Samsung Electronics Co., Ltd. | Ultra-thin semiconductor package device using a support tape |
US20050250352A1 (en) * | 2002-09-25 | 2005-11-10 | Philippe Maugars | Connector for chip-card |
Also Published As
Publication number | Publication date |
---|---|
US6429535B2 (en) | 2002-08-06 |
JP2000133673A (en) | 2000-05-12 |
US20010008307A1 (en) | 2001-07-19 |
US6429514B2 (en) | 2002-08-06 |
US6670707B2 (en) | 2003-12-30 |
US20010007782A1 (en) | 2001-07-12 |
US20010005045A1 (en) | 2001-06-28 |
JP3025685B1 (en) | 2000-03-27 |
US20010005038A1 (en) | 2001-06-28 |
DE19929606A1 (en) | 2000-05-11 |
TW368707B (en) | 1999-09-01 |
US6534344B2 (en) | 2003-03-18 |
US6271586B1 (en) | 2001-08-07 |
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