US20010008780A1 - Controlling packaging encapsulant leakage - Google Patents
Controlling packaging encapsulant leakage Download PDFInfo
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- US20010008780A1 US20010008780A1 US09/789,892 US78989201A US2001008780A1 US 20010008780 A1 US20010008780 A1 US 20010008780A1 US 78989201 A US78989201 A US 78989201A US 2001008780 A1 US2001008780 A1 US 2001008780A1
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- solder resist
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
- This invention relates generally to packaging electronic components and in particular embodiments to encapsulating laminate packages.
- Laminate packages may be made of alternating core material and conductive layers. The core acts as a stiffener and insulator while the conductive layers are etched to leave a trace for electrical purposes. The laminate structure may have a solder resist selectively screen printed onto specific areas of the structure for solder protection.
- A laminate package may be encapsulated by enclosing the unencapsulated package inside two halves of a mold. At the juncture of the two mold faces, encapsulants sometimes leak forming what is known as flash. The encapsulant leaking between the two mold halves may actually contaminate the electrical components that come in contact with the encapsulant. Generally when this happens, the devices are deemed defective and the entire laminated package is discarded.
- In some cases, the leakage of encapsulant material is a result of the bleeding out of the resin vehicle from the overall epoxy. See, Ireland, James E., “Epoxy Bleeding Out in Ceramic Chip Carriers,” ISHM Journal, Vol. 5, No. 1. Regardless of whether the contamination occurs because of the bleed out of the resin vehicle from the overall adhesive or from the leakage of the overall resin itself, the effects of such leakage on electronic components may be catastrophic.
- Thus, there is a need to prevent flash contamination of the electrical components of electrical packages and particularly for preventing such contamination in the course of encapsulating laminate packages.
- In accordance with one aspect, a process for encapsulating integrated circuits includes defining an encapsulation cavity about an integrated circuit die. The cavity is filled with an encapsulant. The outflow of encapsulant is controlled by providing a collection reservoir proximate to the cavity.
- Other aspects are set forth in the accompanying specification and claims.
- FIG. 1 is a greatly enlarged top plan view of one embodiment of the present invention;
- FIG. 2 is an enlarged cross-sectional view taken generally along the line2-2 in FIG. 1 when the device shown in FIG. 1 is in position within an encapsulation mold;
- FIG. 3 is a greatly enlarged cross-sectional view of a portion of the device shown in FIG. 2 in the process of being molded; and
- FIG. 4 is an enlarged cross-sectional view taken generally along the line2-2 in the embodiment shown in FIG. 1 after the device has been completed by attaching solder balls.
- Referring to FIG. 1, a
laminate package 10 may include an I-shaped core 11 punctuated byalignment openings 12. A centralencapsulated region 14 is bounded on either side by aflash cavity 16 and a plurality ofball pads 20. Each ball pad is situated inside the opening left in a solder resist coating whose extent is defined by theedges 18. Each of thecavities 16 basically provides an effective barrier to encapsulant intended to form theregion 14. However, without the interposition of thecavities 16, encapsulant could extend outwardly from theregion 14 and overflow onto thepads 20. This could result in contamination and possible destruction of thecore 11. - Referring to FIG. 2, the
core 11 may be affixed to an integrated circuit chip or die 30. Any conventional die affixation technique may be utilized. For example, the die 30 may be secured to thecore 11 using adhesive, such as epoxy, adhesive tape such as lead-on-chip (LOC) tape or any other available technique.Wire bond wires 26 may make contact with contacts on thedie 30 and extend upwardly to make electrical contact to corresponding contacts on the upper surface of thecore 11. Thebond wires 26 extend through thepassage 25 which is filled with encapsulant 14. - The
laminate package 10 may be encapsulated between twomold halves parting line 34. Theupper mold half 32 a includes anelliptical chamber 35 which defines theencapsulated region 14. - While in the mold, the
encapsulated region 14 is filled with an encapsulant. The encapsulant pots thebond wires 26 that are bonded on one end to thedie 30 and extend upwardly to contact the upper surface of thecore 11. Thewires 26 make contact with contacts 24 (shown in FIG. 4) situated between acavity 16 and theregion 14. - Referring to FIG. 3, encapsulant “A” from the
region 14 may tend to extend outwardly along theparting line 34. In such case, it flows over the solder resist 18 and into thecavity 16 defined in the solder resist 18. Thus, thecavity 16 provides a reservoir to collect the encapsulant overflow. The encapsulant readily fills thereservoir 16 because of its greater open area which provides pressure relief to the encapsulant which squeezes out between any slight gaps between themold halves parting line 34 when the twomold halves cavity 16 where it may be retained until it solidifies. In this way, the flow in the direction of the arrows A is blocked from extending to thepads 20 to the left in FIG. 3. - Because the
cavity 16 may be simply formed by appropriate patterning of the solder resist 18, the provision of the cavities is relatively inexpensive if not cost free. Since apertures must be defined in the solder resist to form theedges 18 surrounding thebond pads 20, the pattern for thecavities 16 may be included at the same time. That is, thecavity 16 on either side of theencapsulated region 14 may be defined during the process of patterning the solder resist to form the openings that define theedges 18 aroundpads 20. - Referring now to FIG. 4, which shows the device of FIG. 1 in cross-section after
solder balls 28 have been positioned, the die 30 is overlaid by thelaminate package 10 which has thecentral opening 25 which is filled with encapsulant. The upper surface of theencapsulated region 14 may have an elliptical configuration, in one example, because of the shape of theupper mold half 32 a (FIG. 2). As a result, thebond wires 26, which extend from thedie 30 up to thecontacts 24 on the upper surface of thelaminate package 10, are completely potted. - The
mold half 32 b may define acavity 50 for encapsulating thedie 30 as shown in FIG. 2. Theencapsulation 52 then covers thedie 30, as shown in FIG. 4. - The
contacts 24 may electrically communicate, viatraces 22 which extend through thecore 11, withvarious pads 20. Thepads 20 may in turn electrically couple tosolder balls 28 in a conventional flip-chip or ball grid array packaging embodiment. Thus, thesolder balls 28 are capable of communicating with the world outside of thepackage 10. In this way, thelaminate package 10 provides a convenient interconnection medium for allowing thedie 30 to communicate with external devices. - The solder resist includes the openings to define the
edges 18 to allow for the imposition of thesolder balls 28 as well as the openings which define thecavities 16 to receive any overflow of the encapsulant material. By positioning acavity 16 between theencapsulated region 14 and thebond pads 20 for thesolder balls 28, the critical electrical contact areas can be protected from contamination by encapsulant flash. - While non-solder mask defined pads (NSDP) are illustrated, solder mask defined pads (SDP) may be used as well. Although a laminate package is illustrated, other packaging configurations may be used as well including those using an interposer.
- While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/789,892 US6395579B2 (en) | 1999-08-31 | 2001-02-21 | Controlling packaging encapsulant leakage |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/386,971 US6210992B1 (en) | 1999-08-31 | 1999-08-31 | Controlling packaging encapsulant leakage |
US09/789,892 US6395579B2 (en) | 1999-08-31 | 2001-02-21 | Controlling packaging encapsulant leakage |
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US09/386,971 Continuation US6210992B1 (en) | 1999-08-31 | 1999-08-31 | Controlling packaging encapsulant leakage |
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US20010008780A1 true US20010008780A1 (en) | 2001-07-19 |
US6395579B2 US6395579B2 (en) | 2002-05-28 |
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US09/386,971 Expired - Lifetime US6210992B1 (en) | 1999-08-31 | 1999-08-31 | Controlling packaging encapsulant leakage |
US09/679,095 Expired - Lifetime US6521980B1 (en) | 1999-08-31 | 2000-10-04 | Controlling packaging encapsulant leakage |
US09/789,892 Expired - Lifetime US6395579B2 (en) | 1999-08-31 | 2001-02-21 | Controlling packaging encapsulant leakage |
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US09/386,971 Expired - Lifetime US6210992B1 (en) | 1999-08-31 | 1999-08-31 | Controlling packaging encapsulant leakage |
US09/679,095 Expired - Lifetime US6521980B1 (en) | 1999-08-31 | 2000-10-04 | Controlling packaging encapsulant leakage |
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Cited By (4)
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US6963142B2 (en) | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
US20040217389A1 (en) * | 2002-05-24 | 2004-11-04 | Hall Frank L. | Apparatus and method for molding a semiconductor die package with enhanced thermal conductivity |
US20050280143A1 (en) * | 2002-05-24 | 2005-12-22 | Hall Frank L | Apparatus for molding a semiconductor die package with enhanced thermal conductivity |
US7642643B2 (en) * | 2002-05-24 | 2010-01-05 | Micron Technology, Inc. | Apparatus for molding a semiconductor die package with enhanced thermal conductivity |
US20120241956A1 (en) * | 2003-03-11 | 2012-09-27 | Micron Technology, Inc. | Techniques for packaging multiple device components |
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US20060270211A1 (en) * | 2005-05-31 | 2006-11-30 | Shinko Electric Industries Co., Ltd. | Method of fabricating wiring board and method of fabricating semiconductor device |
US8015700B2 (en) * | 2005-05-31 | 2011-09-13 | Shinko Electric Industries Co., Ltd. | Method of fabricating wiring board and method of fabricating semiconductor device |
US8455770B2 (en) | 2005-05-31 | 2013-06-04 | Shinko Electric Industries Co., Ltd. | Method of fabricating wiring board and method of fabricating semiconductor device |
US9155195B2 (en) | 2005-05-31 | 2015-10-06 | Shinko Electric Industries Co., Ltd. | Wiring board and semiconductor device |
Also Published As
Publication number | Publication date |
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US6395579B2 (en) | 2002-05-28 |
US6210992B1 (en) | 2001-04-03 |
US6521980B1 (en) | 2003-02-18 |
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