US 20010009031 A1 Abstract A global routing method acquiring global routing between net terminals of cells placed on a VLSI chip. First, a Steiner tree is generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution. Then, partial correction of the Steiner tree is repeated so as not to increase a line length as far as possible in consideration of constraints such as a prohibiting region, a wiring capacity and layers based on the initial solution of the Steiner tree to obtain the global routing. The Steiner tree is corrected generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of 3 or more branches.
Claims(15) 1. A global routing method obtaining global routing between net terminals of cells placed on a chip comprising the step of:
generating a Steiner tree having been generated without any of constraints as an initial solution: and repeating partial correction of said Steiner tree so as not to increase a line length as far as possible in consideration of said constraints based on said initial solution of said Steiner tree to obtain said global routing. 2. The method of claim 1 in the correcting step, partial correction of said Steiner tree is repeated so as not to increase a line length as far as possible in consideration of a prohibiting region, a wiring capacity and layers. 3. The method of claim 2 generating a path collection obtained by dividing said Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of 3 or more branches; and partially correcting said Steiner tree by correction of a path in consideration of said constraints for said path collection of said Steiner tree. 4. The method of claim 3 5. The method of claim 4 determining whether a start point or end point of a path resides in or a route thereof passes through said prohibiting region; if neither residing in nor passing through said prohibiting region, then terminating the process; if said start point or end point of said path resides in said prohibiting region, then moving said start point or end point to outside said prohibiting region and thereafter, renewing said path collection, or if neither being found outside said prohibiting region, then changing no path and terminating the process; and if said path passes through said prohibiting region, then changing a route thereof so as not pass through said prohibiting region. 6. The method of claim 5 as a first correcting step, when a start point in said prohibiting region is moved to outside thereof, selecting points on branches of said Steiner tree traceable from an original start point as prospective points for a new start point of a movement destination or selecting points on all branches of said Steiner tree traceable from an original end point as prospective points for a new end start of a movement destination, and selecting a prospective point, being outside said prohibiting region, and having the shortest line length among said prospected points as a start point or endpoint to change a path; and as a second correcting step, when a route passes through said prohibiting region, changing a path selecting a route passing through a space outside said prohibiting region without changing both of said start and end points so as not to increase a line length as far as possible. 7. The method of claim 3 8. The method of claim 7 defining a wiring capacity indicating the maximum of the number of wires capable of passing through each of blocks obtained by dividing a wiring region into the blocks each of a prescribed area and a wiring congestion level indicating the number of wires currently passing through each of the blocks; if a wiring congestion level of a block is equal to or less than a wiring capacity thereof, then terminating the process; if a wiring congestion level of a block exceeds a wiring capacity thereof, then changing a first path whose start point and end point are outside a block, and passing through the block to a second path finding a route not passing through said block without changing said start point and end point of said first path, or if no route not passing through said block is found, maintaining said first path as is originally; if one of a start point and end point of a path resides within a block and the other resides outside the block, changing said path finding a terminal point outside said block instead of a terminal point within said block and thereby finding a route not passing through said block, or if neither said terminal point nor said rout is found, maintaining said path as is originally; if both of a start point and end point of a path resides in a block, maintaining said path as is originally; and after said path is corrected, recalculating a wiring congestion level of said block and repeating the process till said wiring congestion level thereof decreases to a value equal to or less than a wiring capacity thereof. 9. The method of claim 8 as a first correcting step, when a start point or end point of a path resides in said block, selecting points on branches of a Steiner tree traceable from an original start point or end point as prospect points for a new start point or new end point of a movement destination, and changing a path selecting a prospect point, being outside said block, and having the shortest line length among said prospective points for said new end point or end point to find a route not to passing through said block; and as a second correcting step, when a rout passes through said block, changing a path selecting a route passing through a space outside said block so as not to increase a line length as far as possible without changing a start point and end point thereof. 10. The method of claim 1 11. The method of claim 10 removing branches belonging to a path to be processed from a Steiner tree to divide said branches into a first tree fraction T 1 which is a collection of branches traceable from a start point and a second tree fraction T2 which is a collection of branches traceable from an end point; generating a first prospective path finding an end point on a branch, having the shortest Manhattan distance, among said branches of said tree fraction T 2 from an original start point of said first tree fraction T1; generating a second prospective path finding a start point on a branch, having the shortest Manhattan distance, among said branches of said tree fraction T 1 from an original end point of said second tree fraction T2; if a distance d 1 of said first prospective path is equal to or less than a distance d2 of said second prospective path and equal to or less than a distance d of said pass to be processed, renewing a path collection with said first prospective path whose end point has been changed as a new path; if a distance d 2 of said second prospective path is equal to or less than a distance d1 of said first prospective path and equal to or less than a distance d of said pass to be processed, renewing said path collection with said second prospective path whose end point has been changed as a new path; and if distances d 1 and d2 of said first and second prospective paths, respectively, are equal to or more than a distance of said path to be processed, maintaining said path as is originally without changing a start point and end point thereof. 12. A global routing apparatus acquiring global routing between net terminals of cells placed on a chip comprising:
a Steiner tree generating unit generating a Steiner tree having been generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution; a path collection generating unit generating a path collection obtained by dividing said Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of three or more branches; and a path correcting unit obtaining global routing repeating partial correction of said Steiner tree with correction of a path in consideration of said constraints so as not to increase a line length as far as possible for said path collection of said Steiner tree. 13. The apparatus of claim 12 a prohibiting region rerouting processing unit changing a path passing through a prohibiting region to a path not passing through said prohibiting region for said path collection of said Steiner tree; a wiring congested region rerouting processing unit changing a path passing through a wiring congested region having the number of wires exceeding a wring capacity to a path not passing through said wiring congested region so as to ensure the number of wires equal to or less than said wiring capacity in said wiring congested region for said path collection of said Steiner tree; and a line length improvement processing unit changing a path so as to improve a line length of said path after partial correction of said Steiner tree under said constraints for said path collection of said Steiner tree. 14. A storage medium, readable by a computer, having a global routing program stored therein, said program acquiring global routing between net terminals of cells placed on a chip, comprising:
a Steiner tree generating module generating a Steiner tree having been generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution; a path collection generating module generating a path collection obtained by dividing said Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of three or more branches; and a path correcting module obtaining global routing repeating partial correction of said Steiner tree with correction of a path in consideration of said constraints so as not to increase a line length as far as possible for said path collection of said Steiner tree. 15. The storage medium of claim 14 a prohibiting region rerouting processing module changing a path passing through a prohibiting region to a path not passing through said prohibiting region for said path collection of said Steiner tree; a wiring congested region rerouting processing module changing a path passing through a wiring congested region having the number of wires exceeding a wring capacity to a path not passing through said wiring congested region so as to ensure the number of wires equal to or less than said wiring capacity in said wire congested region for said path collection of said Steiner tree; and a line length improvement processing module changing a path so as to improve a line length of said path after partial correction of said Steiner tree under said constraints for said path collection of said Steiner tree. Description [0001] The present invention relates to a method and apparatus for global routing performed prior to detailed routing in computer-aided automatic layout design of LSI and VLSI and a storage medium, readable by a computer, having a global routing program stored therein, and particularly, to a method and apparatus for global routing used in order to search the minimum cost routing between net terminals using a Steiner tree and a storage medium, readable by a computer, having a global routing program stored therein. [0002] In a CAD system used for automatically designing a large scale semiconductor integrated circuit such as LSI and VLSI using a computer, firstly, a logical design is performed that determines cells such as AND and OR therebetween and nets connecting the cells therebetween; secondly, an automatic design for cell layout placing the cells on a chip is performed based on a netlist obtained by the logical design and finally, routing is performed that determines wires connecting nets between the cells placed on the chip. The routing is divided into two phases: one is global routing in which net routing is determined without considering timing, delay and so on and the other is detailed routing in which actual routing on the chip is determined in consideration of timing, delay and others. Along with progress in circuit design technology in recent years, improvement on degree of integration in VLSI and increase in circuit scale have been tremendous. For this reason, automatic layout design faces requirement for high speed processing of a large scale circuit. [0003] Simple description will be given, here, of a definition of a global routing problem, an object of the present invention. Consider a region on a grid structure called a grid graph. A grid graph is obtained by a procedure in which a chip region is divided into cell blocks with horizontal and vertical lines and thus formed rectangular cells are represented by vertices and the vertices are connected to form a grid structure, and a terminal of a layout cell is expressed by a black point on a grid structure. Intersections of the horizontal and vertical lines of the grid graph are called grids. A grid size is a total number of grids and in a case where the number of grids in the vertical direction is v counts and the number of grids in the horizontal direction is h counts, the grid size is a value of (h×v). In a case of FIG. 1, h=6 and v=6, so a grid size is 36. A global routing problem is to generate line segments on a grid structure so as to connect terminals t [0004] Concise description will be given of well known ones of global routing methods below: [0005] Typically, a maze method and a line search method are named as first two which are procedures regarding a net with two terminals. The maze method is effected as follows: As shown in FIG. 2, one terminal t [0006] A line search method is such that as in FIG. 3, line segments are generated from the source t [0007] Extended methods of the maze method and the line search method are employed for a multiterminal net with three or more terminals, but such an extended method has a defect of falling into a local solution; therefore, a method using a Steiner tree of FIG. 4 is more excellent in that a high quality solution is obtained. The method using a Steiner tree generates a Sterner tree [0008] In a method dependent on a grid size such as a maze method, a problem arises since a calculation time and a used memory amount are increased in a large scaled circuit. On the other hand, the method using Steiner tree has dependency of a calculation time on the number of net terminals. The number of net terminals is at the most several hundreds in a practical circuit. In contrast to this, a grid size of a wiring region amounts to at least several millions or more. Therefore, the method using a Steiner tree is more advantageous in calculation time and used memory amount compared with the maze method. In a general algorithm for generating a Steiner tree, however, no consideration is given to layers, prohibition, a wiring capacity; therefore, such constraints are left up to detailed routing. In this case, a problem imposed on the detailed routing becomes hard and contrary to the expectation, a possibility arises of increasing a calculation time for all the wiring. [0009] According to the present invention, provided are a method and apparatus for global routing capable of obtaining a high quality solution for global routing that alleviates a load on detailed routing using a Steiner tree, and a storage medium, readable by a computer, having a global routing program stored therein. [0010] The present invention is a global routing method obtaining global routing between net terminals of cells placed on a chip and the method includes: a Steiner tree generating step of generating a Steiner tree having been generated without any of constraints as an initial solution: and a correcting step of repeating partial correction of the Steiner tree so as not to increase a line length as far as possible in consideration of constraints based on the initial solution of the Steiner tree to obtain the global routing, wherein in the Steiner tree generating step, a Steiner tree is generated, as an initial solution, without any of constraints such as layers, prohibition and a wiring capacity and in the correcting step, partial correction of the Steiner tree is repeated so as not to increase a line length as far as possible in consideration of a prohibiting region, a wiring capacity and layers. The present invention can achieve a result of the same quality as global routing by means of a maze method in consideration of an obstacle by performing a partial correction of a Steiner tree while taking constraints on wiring into consideration. Furthermore, calculation required for partial correction of a Steiner tree in the present invention is fundamentally coordinate computation, and a calculation time and a used memory amount are dependent on the number N of net terminals. Therefore, in a large scale circuit, the method of the present invention is more advantageous in calculation time and used memory amount compared with a maze method scanning a wiring region. Herein, the correcting step includes: a path collection generating step of generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of 3 or more branches; and a path correcting step of partially correcting the Steiner tree by correction of a path in consideration of constraints for the path collection of the Steiner tree. In this path collection, when the number of terminals is N, and the number of Steiner points is an (N) order, the number of branches of the Steiner tree is e [0011] I. determining whether a start point or end point of a path resides in or a route thereof passes through a prohibiting region; [0012] II. if neither reside in nor passing through the prohibiting region, then terminating the process; [0013] III. if the start point or end point or the path resides in the prohibiting region, then moving the start point or end point to outside the prohibiting region and thereafter, renewing a path collection, or if neither being found outside the prohibiting region, then changing no path and terminating the process; and [0014] IV. if a path passes through a prohibiting region, then changing a route thereof so as not pass through the prohibiting region. [0015] The prohibiting region rerouting step includes: a first correcting step and a second correcting step. In the first correcting step, when a start point in a prohibiting region is moved to outside the region, points on branches of a Steiner tree traceable from an original start point is selected as prospective points for a new start point of a movement destination or points on all branches of the Steiner tree traceable from an original end point is selected as prospective points for a new end point of a movement destination, and a prospective point, being outside the prohibiting region, and having the shortest line length is selected among the prospected points as a start point or endpoint to change a path. In this case, a calculation time for correcting one path is of O(e [0016] I. defining a wiring capacity indicating the maximum of the number of wires capable of passing through each of blocks obtained by dividing a wiring region into the blocks each of a prescribed area and a wiring congestion level indicating the number of wires currently passing through each of the blocks; [0017] II. if a wiring congestion level of a block is equal to or less than a wiring capacity thereof, then terminating the process; [0018] III. if a wiring congestion level of a block exceeds a wiring capacity thereof, then changing a first path whose start point and end point are outside a block, and passing through the block to a second path finding a route not passing through the block without changing a start point and end point of the first path, or if no route not passing through the block is found, maintaining the first path as is originally; [0019] IV. if one of a start point and endpoint of a path resides within a block and the other resides outside the block, changing the path finding a terminal point outside said block instead of a terminal point within said block and thereby finding a route not passing through the block, or if neither the terminal point nor the rout is found, maintaining the path as is originally; [0020] V. if both of a start point and end point of a path resides in a block, maintaining the path as is originally; and [0021] VI. after a path is corrected, recalculating a wiring congestion level of a block and repeating the process till the wiring congestion level thereof decreases to a value equal to or less than a wiring capacity thereof. [0022] This wiring congested region rerouting step can also includes: a first correcting step and a second correcting step. In the first correcting step, when a start point or end point of a path resides in a wiring congested block, points on branches of a Steiner tree traceable from an original start point or end point are selected as prospect points for a new start point or new end point of a movement destination, and a path is changed selecting a prospect point, being outside the block, and having the shortest line length among the prospective points for the new end point or end point to find a route not to passing through the block. In the second correcting step, when a rout passes through a block, a path is changed selecting a route passing through a space outside the block so as not to increase a line length as far as possible without changing a start point and end point thereof. The path correcting step includes a line length improving step of changing a path so as to improve a line length of the path after partial correction of a Steiner tree under constrains for a path collection of the Steiner tree. The line length improving step has a detailed procedure including the steps of: [0023] I. removing branches belonging to a path to be processed from a Steiner tree to divide the branches into a first tree fraction T [0024] II. generating a first prospective path finding an end point on a branch, having the shortest Manhattan distance, among branches of the tree fraction T [0025] III. generating a second prospective path finding a start point on a branch, having the shortest Manhattan distance, among branches of the tree fraction T [0026] IV. if a distance d [0027] V. if a distance d [0028] VI. If distances d [0029] Furthermore, the present invention provides a global routing apparatus acquiring global routing between net terminals of cells placed on a chip. The global routing apparatus includes: a Steiner tree generating unit generating a Steiner tree having been generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution; a path collection generating unit generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of three or more branches; and a path correcting unit obtaining global routing repeating partial correction of the Steiner tree with correction of a path in consideration of the constraints so as not to increase a line length as far as possible for the path collection of the Steiner tree. The path correcting unit of the global routing apparatus includes: a prohibiting region rerouting processing unit changing a path passing through a prohibiting region to a path not passing through the prohibiting region for a path collection of the Steiner tree; a wiring congested region rerouting processing unit changing a path passing through a wiring congested region having the number of wires exceeding a wring capacity to a path not passing through the wiring congested region so as to ensure the number of wires equal to or less than the wiring capacity in the wiring congested region for the path collection of the Steiner tree; and a line length improvement processing unit changing a path so as to improve a line length of the path after partial correction of said Steiner tree under the constraints for the path collection of the Steiner tree. [0030] Furthermore, the present invention provides a storage medium, readable by a computer, having a global routing program stored therein, the program acquiring global routing between net terminals of cells placed on a chip. The storage medium includes: a Steiner tree generating module generating a Steiner tree having been generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution; a path collection generating module generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of three or more branches; and a path correcting module obtaining global routing repeating partial correction of the Steiner tree with correction of a path in consideration of constraints so as not to increase a line length as far as possible for a path collection of the Steiner tree. Furthermore, the path correcting module of the storage medium includes: a prohibiting region rerouting processing module changing a path passing through a prohibiting region to a path not passing through the prohibiting region for a path collection of a Steiner tree; a wiring congested region rerouting processing module changing a path passing through a wiring congested region having the number of wires exceeding a wring capacity to a path not passing through the wiring congested region so as to ensure the number of wires equal to or less than the wiring capacity in the wire congested region for the path collection of the Steiner tree; and a line length improvement processing module changing a path so as to improve a line length of the path after partial correction of a Steiner tree under the constraints for the path collection of the Steiner tree. [0031] A calculation time for correction of a Steiner tree in such a global routing method of the present invention is only of the order of O{N [0032]FIG. 1 is a descriptive diagram of a global routing problem using a grid graph; [0033]FIG. 2 is a descriptive diagram of a maze method; [0034]FIG. 3 is a descriptive diagram of a line search method; [0035]FIG. 4 is a descriptive diagram of a method using a Steiner tree; [0036]FIG. 5 is a block diagram of a VLSI automatic design system to which the present invention is applied; [0037]FIG. 6 is a functional block diagram of a global routing apparatus of the present invention; [0038]FIG. 7 is a flow chart for a global routing processing of the present invention; [0039]FIG. 8 is a descriptive diagram of a Steiner tree generated as an initial solution in the present invention; [0040]FIG. 9 is a descriptive drawing of a sub-Steiner tree obtained by dividing the Steiner tree into paths each with the Steiner point of FIG. 8; [0041]FIG. 10 is a descriptive table of a path list showing a path collection of FIG. 9; [0042]FIG. 11 is a flow chart for prohibiting region rerouting processing of the present invention; [0043]FIGS. 12A to [0044]FIGS. 13A and 13B are flow charts for wiring congested region rerouting processing of the present invention; [0045]FIGS. 14A to [0046]FIGS. 15A and 15B are flow charts for line length improvement processing of the present invention; [0047]FIGS. 16A to [0048]FIGS. 17A and 17B are descriptive drawings for layer placement processing of the present invention. [0049]FIG. 5 is a block diagram of an automatic design system for LSI and VLSI aided by a computer using a global routing technique of the present invention. This automatic design system includes: a logical design system [0050]FIG. 6 is a functional block diagram of the global routing apparatus [0051]FIG. 7 is a flow chart for global routing processing of the present invention in the global routing apparatus [0052]FIG. 8 shows a Steiner tree Ti of a net Ni generated without any of the constraints in step S [0053] Next, in step S [0054] I. a start point of the path: a Steiner point or a leaf (terminal) of an original Steiner tree; [0055] II. an end point of the path: a Steiner point or a leaf (terminal) of an original Steiner tree; and [0056] III. a route from the start point to the end point: a list of branches. [0057] A subtree collection of FIG. 9 can be divided into five paths p [0058] Herein, a correcting process for the Steiner tree Ti expressed by a path collection of steps S [0059] (Correction Rule 1) [0060] In the correction rule 1, a start point and end point of a path are changed so as not to increase a line length of the path compared with an original Steiner tree. Along with such a change, routing therebetween is also changed. A prospective point for a new start point comes to be one of points (vertices on a grid graph) on branches of all of Steiner trees traceable from an original start point. Similar to this, a prospective point for a new end point comes to be one of points on branches of all of Steiner trees traceable from an original end point. In order not to increase a line length of a path compared with that of the original Steiner tree, selected is a prospective point such as to meet constraints and have the shortest line length among prospective points for a new start point and a new end point. If such a prospective point is not available, selected is a second prospective point meeting the constraints, wherein a line length becomes longer. After correction of a path, Steiner points are altered since a structure of a Steiner tree is also altered; therefore, recalculation is required on all of paths constituting the Steiner tree. A calculation time required for one path in application of the correction rule 1 is O(e [0061] (Correction Rule 2) [0062] In the correction rule 2, a start point and end point of a path are not changed but only routing therebetween is changed so as not to increase a line length of the path compared with an original Steiner tree. In order not to increase a line length of the path owing to change in routing therebetween compared with the original Steiner tree, it is only required that selection is performed of a route passing through a rectangle encircling the start point and end point of the path. If the route cannot pass through the rectangle encircling the start point and end point under constraints such as wiring prohibition, a line length is caused to be longer. A calculation time for application of the correction rule 2 can be restricted to O(1) by predetermining some number of routing patterns in the rectangle encircling the start point and end points. [0063]FIG. 11 is a flow chart for a correction process rerouting a wiring prohibiting region of step S [0064]FIGS. 12A to [0065]FIGS. 13A and 13B are flow charts for correction processing, that is wire congested region rerouting processing, for a Steiner tree in consideration of the wiring congested region of step S [0066]FIGS. 14A to [0067]FIGS. 15A and 15B are flow charts for line length improvement processing of the Steiner tree of step S [0068]FIGS. 16A to [0069]FIGS. 17A and 17C are concrete examples of allotment processing of branches to layers performed after partial correction for and line improvement on a Steiner tree in step S [0070] Note that in the above described embodiment, a partial correction is performed on an initial solution of a Steiner tree having been generated without any of constrains, in consideration of a wiring prohibiting region and a wiring capacity and thereafter subjected to line improvement and finally layer placement is performed, but even when correction of a Steiner tree is performed only in consideration of specific constraints such as rerouting of a wiring prohibiting region or a wiring capacity, a load in the following detailed routing processing can be alleviated. Furthermore, the present invention provides a storage medium, readable by a computer, having a global routing program stored therein, the program being provided with a procedure for global routing processing shown in the above described embodiment. In the global routing program stored in the storage medium, processing functions of respective units of the global routing apparatus [0071] According to the present invention, as described above, by performing partial correction on a Steiner tree as an initial solution in consideration of constraints, a result with the same quality as global routing obtained in consideration of an obstacle in an existing maze method can be obtained as a solution of global routing using a Steiner tree. Thereby, no necessity arises of processing in consideration of constraints such as layers, prohibition and a wiring capacity in a subsequent detailed routing; therefore, a processing load is alleviated in the detailed routing, a calculation time is reduced as a whole, thus enabling realization of a faster automatic design. [0072] Furthermore, a calculation required for partial correction of a Steiner tree of the present invention is coordinate calculation, and a calculation time and a used memory amount is dependent on a number related to a net and is more advantageous in calculation time and used memory amount compared with a maze method whose calculation time and used memory capacity are dependent on a grid size, with a result that global routing with less of a calculation time and less of a used memory amount can be realized in the present invention. Referenced by
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