BACKGROUND OF THE INVENTION

[0001]
1. Field of the Invention

[0002]
The present invention relates to a receiver that detects an approximate value of the power of a reception signal. Especially, the invention relates to a receiver that enables detecting the highly precise approximate value with a high speed.

[0003]
2. Description of the Related Art

[0004]
In, for example, a communication system, it is indispensable to detect the power (level) of a reception signal by a relevant receiver. As an example, in a mobilestation device that is equipped in a radio communication system, the powers of the signals that are received from a plurality of basestation devices that exist in the neighborhood thereof are detected and compared at all times with one another by the receiver. Thereby, the receiver recognizes a basestation device, the power of which signal is maximum, to be an optimum basestation device. According to this recognition, the receiver selects that basestation device as an opponent device for its communication.

[0005]
The abovedescribed detection of the power is ordinarily realized through the execution of an operation process that is made according to the reception signal. Such operation process will hereafter be explained in detail.

[0006]
Incidentally, in the claims of this specification, a component I represents the absolute value of the component I, and a component Q represents the absolute value of the component Q. Also, in the other part of this specification, in the detection (operation)of an approximate value of the power of a reception signal, a component I represents the absolute value of the component I, and a component Q represents the absolute value of the component Q.

[0007]
First, assume that I represents the value of a component I of the reception signal (the absolute value of the component I); and Q represents the value of a component Q (the absolute value of the component Q). Then, theoretically, the power P of the reception signal is given by the following equation no. 1. It is to be noted that the component I and component Q of the reception signal mean two digital demodulated signals, the phase difference between which is 90 degrees. Each of these digital demodulated signals is obtained by demodulating, for example, the reception signal that has been subjected to orthogonal modulation.

[0008]
[Equation No. 1]

P=(I ^{2} +Q ^{2})^{½} (1)

[0009]
However, when attempting to realize the operation process given as the above equation no. 1 with the use of an actual digital circuit, because the operation process contains therein the selfmultiplication operation of, for example, the I or Q, the number of the digits necessary for execution of the operation inconveniently becomes twice as large. Namely, the number of the bits necessary in the digital circuit inconveniently becomes twice as large. For this reason, the circuit becomes large in scale, and in addition the compactness that is loaded upon the circuit inconveniently becomes high in degree. Also, even when executing such operation process with the use of, for example, a DSP (Digital Signal Processor) or a CPU (Central Processing Unit), because there is the abovedescribed selfmultiplication operation, the amount of operation processed, the time length of operation processing, etc. inconveniently becomes very large.

[0010]
On that account, an attempt to use not the strict theoretical equation shown in the above equation no. 1 but an approximate equation for operating the power of the reception signal has hitherto been made. And, an attempt has thereby been made to use only an addition operation instead of the multiplication/addition operation shown in the equation no. 1.

[0011]
Here, an approximate equation that is frequently used is shown below as the equation no. 2. It is to be noted that P represents the power (here, an approximate value) of the reception signal; MAX (I, Q) represents a larger one of the value I and the value Q; and MIN (I, Q) represents a smaller one of the value I and the value Q.

[0012]
[Equation No. 2]

P=({fraction (10/11)})×MAX(I,Q)+({fraction (5/11)})×MIN(I,Q) (2)

[0013]
Also, conventionally, the operation equation shown in the above equation no. 2 is further made approximate to one operation equation that is suitable to the execution of the operation process in a digital circuit. This approximate equation is shown as the following equation no. 3.

[0014]
[Equation No. 3]

P=MAX(I,Q)+(½)×MIN(I,Q) (3)

[0015]
Also, in FIG. 5, illustration is made of an example of the procedure of the power approximateoperation process that is taken when the receiver makes its operation of an approximate value of the power of the reception signal by using the approximate equation shown as the equation no. 3.

[0016]
Namely, in the receiver, first, the component I and component Q of the reception signal are taken in as digital signals (step S21). And the value I and the value Q are compared with each other to determine which one of them is larger or smaller (step S22).

[0017]
As a result of this, if the value I is larger, the value I is set to be c=I. and the value Q is set to be d=Q (step S23). If the value Q is larger, the value Q is set to be c=Q; and the value I is set to be d=I (step S24).

[0018]
Next, in the receiver, the value that is obtained by shifting the value d by 1 bit rightward (i.e. the value that is obtained by multiplying the value d by ½) is set to be d′ (step S25). And, operation of (c+d′) is executed. And, the result of this operation is detected as the approximate value of the power of the reception signal (step S26).

[0019]
However, in the conventional receiver arranged to detect the approximate value of the power of the reception signal by using the one approximate equation shown, for example, by the above equation no.3 (the one that is obtained by being made further approximate to the preceding approximate equation), the error that is produced by that approximate equation is large in value. Therefore, the precision of this approximate value is low. Resultantly, there was the inconvenience that the quality of the communication became deteriorated.

[0020]
As an example, in the mobilestation device that as described above is at all times detecting the power of the reception signal from each of the basestation devices that exist in the neighboring area upon that mobilestation device, because the error made from that detection is too large, the mobilestation device erroneously recognizes the basestation device that is not optimum as being an optimum basestation device. Resultantly, there was the inconvenience that the possibility that the mobilestation device would select that basestation device became high.
SUMMARY OF THE INVENTION

[0021]
The present invention has been made in order to solve the abovedescribed conventional problems and has an object to provide a receiver that enables detecting a highly precise approximate value of the power of the reception signal with a high speed.

[0022]
Another object of the invention is to provide a receiver that comprises a digital circuit enabling highprecision and highspeed detection to be made as a preferred embodiment.

[0023]
To attain the above object, the receiver according to the invention detects an approximate value of the power of the reception signal as follows.

[0024]
Namely, first operation means performs addition of a value, which is obtained by multiplying a smaller one of the component I value and the component Q value of the reception signal by ⅛, and a larger one of them. Second operation means performs addition of a value, which is obtained by multiplying a smaller one of the component I value and the component Q value of the reception signal by ½, and a value that is obtained by multiplying a larger one of them by ⅞. Detection means detects a larger one of the operation result of the first operation means and the operation result of the second operation means as an approximate value of the power of the reception signal.

[0025]
Accordingly, because the abovedescribed operation process does not contain, for example, selfmultiplication operation and therefore suits a digital operation process, it is possible to perform the operation process with a high speed. In addition, as illustrated in, for example, an embodiment as later described, the power of the reception signal can be detected with a high precision (i.e. a highly precise approximate value can be detected) compared to the conventional receiver. Therefore, a high quality of communication can be ensured.

[0026]
Also, in the receiver of the invention, an approximate value of the power of the reception signal is detected by, for example, the following digitalcircuit construction to thereby realize the highly precise and highspeed detection in the same way as has been described above.

[0027]
That is, a first comparator compares a component I and component Q of the reception signal in scale and outputs a larger one of these component values as a first output value. The first comparator simultaneously outputs a small one of them as a second output value. A 3bit shift register multiplies the first output value from the first comparator by ⅛, and a subtractor subtracts the output value from the 3bit shift register from the first output value from the first comparator. A 1bit shift register multiplies a second output value from the first comparator by ½. A 2bit shift register multiplies the output value from the 1bit shift register by ¼. A first adder adds the first output value from the first comparator and the output value from the 2bit shift register. A second adder adds the output value from the subtractor and the output value from the 1bit shift register. A second comparator compares the output value from the first adder and the output value from the second adder and outputs a larger one of these output values as an approximate value of the power of the reception signal.
BRIEF DESCRIPTION OF THE DRAWINGS

[0028]
[0028]FIG. 1 is a view illustrating an example of the construction of a receiver according to an embodiment of the invention;

[0029]
[0029]FIG. 2 is a view illustrating an example of the circuit construction of a power operation processing part;

[0030]
[0030]FIG. 3 is a view illustrating an example of the procedure of a power approximateoperation processing according to the embodiment of the invention;

[0031]
[0031]FIG. 4 is a view illustrating an example of the comparison of a power approximateoperation according to the conventional technique and a power approximateoperation according to the embodiment of the invention; and

[0032]
[0032]FIG. 5 is a view illustrating an example of the procedure of the power approximateoperation process according to the convention technique.
DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033]
An embodiment of the invention will now be described with reference to the drawings.

[0034]
It is to be noted that a description will be made of a case where the invention is applied to a receiver that is equipped in a mobilestation device of, for example, a radio communication system through which a basestation device and the mobilestation device perform radio communication between these two.

[0035]
In FIG. 1, there is illustrated an example of the construction of the receiver according to this embodiment. This receiver comprises an antenna 1 for transmitting and receiving a radio signal, a reception part (RX part) 2 for performing demodulation, etc. of the signal received by the antenna 1 into a component I signal and component Q signal, a baseband signal processing part 3 for performing baseband signal processing of the component I signal and component Q signal that are output from the RX par 2, and a power (POWER) operation processing part 4 for performing operation of an approximate value of the power of the reception signal by the use of the components I and Q that are output from the RX part 2.

[0036]
Here, the featuring portion of the receiver of this embodiment is regarding the construction of the power operation processing part 4 and the process that is executed by this power operation processing part 4. This construction and process will hereafter be explained in detail.

[0037]
In FIG. 2 there is illustrated an example of the construction of a digital circuit of the power operation processing part 4 of this embodiment. The power operation processing part 4 comprises two comparators 11, 18, three shift registers 12, 14, and 15, one subtractor 13, and two adders 16, 17.

[0038]
The first comparator 11 has a function to input an I component and Q component of a reception signal that is output from the RX part 2 and to compare the both components with each other to determine which is larger or smaller. The first comparator 11 has a function to output a larger one of those components to each of a 3bit (3 bits) shift register 12, subtractor 13, and first adder 16 as a first output value. The first comparator 11 has a function to output a smaller one of those components to a 1bit (1 bit) shift register 14 as a second output value.

[0039]
The 3bit shift register 12 has a function to shift the first output value input from the first comparator 11 by 3 bits rightward (i.e. to multiply it by ⅛) and to output the resulting value to the substractor 13.

[0040]
The subtractor 13 has a function to input the first output value from the first comparator 11 and also to input the by⅛multiplied value from the 3bit shift register 12. The substractor 13 performs subtraction of the by⅛multiplied value from the first output value. The substractor 13 has a function to output the result (i.e. a value obtained by multiplying the first output value by ⅞) of this subtraction to the second adder 17.

[0041]
The 1bit shift register 14 has the following function. Namely, the 1bit shift register 14 inputs the second output value that is output from the first comparator and performs 1bit rightward shift of that second output value (i.e. multiplies the second output value by ½). The 1bit shift register 14 outputs the resulting value to the 2bit (2 bits) shift register 15 and the second adder 17.

[0042]
The 2bit shift register 15 has a function to input the by½multiplied value from the 1bit shift register 14, to perform 2bit rightward shift thereof (i.e. to perform ¼ multiplication thereof), and to output the resulting value to the first adder 16.

[0043]
The first adder 16 has the following function. Namely, the first adder 16 inputs the first output value from the first comparator 11 and also inputs the by¼multiplied value (the by⅛multiplied value of the second output value) from the 2bit shift register 15. The first adder 16 adds the first output value and the by¼multiplied value to thereby output the result of addition to the second comparator 18.

[0044]
The second adder 17 inputs the result of subtraction from the subtractor 13 and inputs the by½multiplied value from the 1bit shift register 14. The second adder 17 adds the result of subtraction and the by½multiplied value and outputs the result of this addition to the second comparator 18.

[0045]
The second comparator 18 compares the result of addition that is output from the first adder 16 and the result of addition that is output from the second adder 17, with each other, to determine which is larger or smaller. The second comparator 18 thereby outputs a larger one of the both results of additions as an approximate value of the power of the reception signal.

[0046]
With a circuit construction such as that described above, in the power operation processing part 4 of this embodiment, the value (a larger one of the two results of the abovedescribed additions) that is output from the second comparator 18 is detected as the power (an approximate value) of the reception signal.

[0047]
Here, the addition result P1 that is output from the first adder 16 is given by the following equation no. 4 while the addition result P2 that is output from the second adder 17 is given by the following equation no. 5. It is to be noted that the approximate equation that is given as the equation no. 4 or 5 is suitable for the execution of the digital operation process and so is easy to realize with the use of the digital circuit.

[0048]
[Equation No. 4]

P1=MAX(I,Q)+(⅛)×MIN(I,Q) (4)

[0049]
[Equation No. 5]

P2=({fraction (14/16)})×MAX(I,Q)+(½)×MIN(I,Q) (5)

[0050]
Also, the value that is output as the power (approximate value) P of the reception signal from the second comparator 18 is given as the following equation no. 6. It is to be noted that MAX (P1, P2) represents a larger one of the values P1 and P2.

[0051]
[Equation No. 6]

P=MAX(P1,P2) (6)

[0052]
In FIG. 3, there is illustrated an example of the procedure of the power approximateoperation process executed in the power operation processing part 4 of this embodiment.

[0053]
Namely, in the power operation processing part 4, first, a component I and component Q of the reception signal are taken in as digital signals (step S1). The first comparator 11 then compares the component I and the component Q with each other to determine which one of them is larger or smaller (step S2).

[0054]
As a result of this, if the component I is larger, the component I is set to be, for example, a (the first output value)=I, and the component Q is set to be, for example, b (the second output value)=Q (step S3). If the component Q is larger, the component Q is set to be a=Q, and the component I is set to be b=I (step S4).

[0055]
Next, in the power operation processing part 4, the 3bit shift register 12 outputs a value (i.e. a value obtained by multiplying the a by ⅛) a′ that is obtained by shifting the a by 3 bits rightward (step S5). The subtractor 13 outputs a value a″ (=aa′) that is obtained by subtracting the a′ from the a (step S6). The 1bit shift register 14 outputs a value (i.e. a value obtained by multiplying the b by ½) b′ that is obtained by shifting the b by 1 bit rightward (step S7). The 2bit shift register 15 outputs a value (i.e. a value obtained by multiplying the b′ by ¼) b″ that is obtained by shifting the b′ by 2 bits rightward (step S8).

[0056]
And, in the power operation processing part 4, (a+b″) (the equation (1)) is calculated by the first adder 16, and (a″+b′) (the equation (2)) is calculated by the second adder 17 (step S9). The second comparator 18 compares these two calculation results (addition results) with each other to determine which one of these results is larger or smaller (step S10). And, a larger one of those results is selected and is output as an approximate value of the power of the reception signal (step S11, step S12).

[0057]
In this way, the receiver according to the invention has the feature of performing the calculation of an approximate value of the power of the reception signal by the use of a plurality of the approximate equations.

[0058]
Also, in FIG. 4, there is illustrated an example of the graphic diagram wherein comparison is made between the precision of the power approximateoperation that is executed in the receiver of this embodiment and the precision of the power approximateoperation that is executed in the conventional receiver by the use of the equation no. 3 shown under the item “Description of the Related Art”. The abscissa axis of the graph represents the phase (radian (xπ)), and the ordinate axis represents the power.

[0059]
In the graph illustrated in FIG. 4, there are illustrated the result of the power approximateoperation that is obtained using a general approximate equation, as (a) (general approximate equation), the result of the power approximateoperation that is obtained from the conventional receiver, as (b) (conventional approximate equation), and the result of the power approximateoperation that is obtained from the receiver of this embodiment, as (c) (approximate equation of the invention), respectively. It is to be noted that each of these results is the one that is obtained under the assumption that the power corresponding to the equation (I^{2}+Q^{2})=1 be an ideal value.

[0060]
As illustrated in FIG. 4, in the approximate equation that is used in the conventional receiver, the calculation error is large in value. So, the error that amounts even to 11.8 percent (%) at maximum inconveniently occurs. Further, in, for example, a mobilestation device, it sometimes happens that it becomes necessary to measure the SIR (Signal to Interference Ratio). However, when performing such a measurement, in the conventional receiver it results that a very large error inconveniently occurs because the error of that measurement is added to the abovedescribed calculation error.

[0061]
On the other hand, in the approximate equation used in the receiver of this embodiment, 0.78 percent (%) or less of error only occurs even at maximum. That is, the error is very small in value and therefore the precision is excellent.

[0062]
As described above, according to the receiver of this embodiment, using, for example, the digital circuit that has been constructed of the shift registers, comparator, etc. as illustrated in FIG. 2, a highly precise approximate value of the power of the reception signal can be detected with a high speed. It thereby becomes possible to ensure a high quality of communication.

[0063]
Incidentally, in this embodiment, there is the function of performing an operation of the addition result P1 shown in the equation no. 4 previously referred to by the first comparator 11, 1bit shift register 14, 2bit shift register 15, and first adder 16. By reason of this function, these elements constitute first operation means referred to in the invention.

[0064]
Also, in this embodiment, there is the function of performing an operation of the addition result P2 shown in the equation no. 5 previously referred to by the first comparator 11, 3bit shift register 12, subtractor 13, 1bit shift register 14, and second adder 17. By reason of this function, these elements constitute second operation means referred to in the invention.

[0065]
Also, in this embodiment, there is the function of selecting and detecting a larger one of those two addition results P1 and P2 as an approximate value of the power of the reception signal by the second comparator 18. By reason of this function, this comparator 18 constitutes detection means referred to in the invention.

[0066]
Here, in this embodiment, using the digital circuit construction preferred to realize the operations shown in the equation nos. 4 to 6 referred to as above, this operation has been executed. However, the approximate equation used in the invention is not limited to the embodiment of the equation nos. 4 to 6. If there is the feature of executing operations using, for example, a plurality of approximate equations to thereby calculate a plurality of candidates each becoming an approximate value of the power of the reception signal and thereby detect an excellent one from among a plurality of the candidates as an approximate value of the power of the reception signal, any approximate equations may be used. Also, no particular limitation is imposed on the construction of the receiver according to the invention, either. In the receiver according to the invention, for example, a construction to execute the operations using a DSP, CPU, etc. may also be adopted.

[0067]
Namely, in this embodiment, the respective function means for executing the power approximateoperation process according to the invention have been constructed of the hardware circuit. However, in the invention, it may be arranged that in the hardware material equipped with, for example, a processor, memory, etc. the processor executes a control program stored in the ROM, thereby the process be executed. Also, the invention can also be taken to be a recording medium from that data is readable by a relevant computer, such as a floppy disk or CDROM having stored therein such a control program. This control program can be input from the recording medium to the computer and be executed by the processor, thereby the process according to the invention can be performed.

[0068]
Also, the receiver according to the invention can be applied not only to, for example, a mobilestation device of the radio communication system. The point is that only if a receiver is able to detect the power (an approximate value in case of the invention) of the reception signal, the receiver of the invention can be also applied to, for example, a basestation device, relaystation device, and other communication devices.

[0069]
As has been described above, according to the receiver of the present invention, using, for example, a digital circuit, a value obtained by multiplying a smaller one of the component I and the component Q of the reception signal by ⅛ and a larger one of these two components are added together according to a plurality of approximate equations. A value obtained by multiplying a smaller one of the components I and Q of the reception signal by 1/2 and a value obtained by multiplying a larger one of these components by ⅞ are added together similarly. Of these two addition results, the value of a larger one thereof is detected as an approximate value of the power of the reception signal. Therefore, for example, it is possible to detect a highly precise approximate value compared to the conventional receiver as illustrated in the abovedescribed embodiment. Thereby, a highly precise and highspeed detection of the power can be realized.