FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a method for forming a capacitor structure for inhibiting diffusion of oxygen atoms effectively by forming a conductive plug of platinum (Pt) under a bottom electrode.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly due to downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, there have been proposed several structures for the capacitor, such as a concave type or a pedestal type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing a three-dimensionally arranged capacitor is a long and tedious one and consequently incurs high manufacturing costs. Therefore, there is a strong demand for a new memory device that can reduce the cell area while securing a requisite volume of information without requiring complex manufacturing steps.
To secure the capacitance in a given area, a high dielectric material, e.g., tantalum oxide (Ta2O5), barium strontium titanate (BST) or the like, has been used as a capacitor thin film in place of conventional silicon oxide film or silicon nitride film. And further, platinum (Pt), iridium (Ir), rhodium (Rh), ruthenium (Ru) or the like is employed as an electrode instead of conventional polysilicon.
Referring to FIG. 1, there is provided a cross sectional view of a conventional semiconductor device 100 with a pedestal type capacitor. The process for manufacturing the semiconductor device 100 begins with the preparation of an active matrix 110 including a silicon substrate 102, an isolation region 104, diffusion regions 106, gate oxides 108, gate lines 112, sidewalls 114, a bit line 118, polysilicon plugs 116, and an insulating layer 120. Here, the bit line 118 is electrically connected to one of the diffusion regions 106A to apply an electric potential. Each of the polysilicon plugs 116 is electrically connected to a respective one of the other diffusion regions 106. Although the bit line 118 actually lengthens in right and left directions bypassing the polysilicon plugs 116, the drawing does not show these parts of the bit line 118. Thereafter, a diffusion barrier layer and a first conductive layer are subsequently formed on top of the polysilicon plug 116 and then patterned into a predetermined configuration, thereby obtaining a diffusion barrier 122 and a bottom electrode 124. Finally, a high dielectric layer 126 and a second conductive layer 128 are formed sequentially on the entire surface.
In the conventional semiconductor device 100, the diffusion barrier layer 122 is formed between the polysilicon plug 116 and the bottom electrode 124 because oxygen atoms may diffuse into the polysilicon plug 116 along boundaries of the bottom electrode 124, which is made of Pt, Ir, Ru or the like, in a post thermal treatment with high temperature and oxygen rich ambient. Therefore, if there is no diffusion barrier layer 122 under the bottom electrode 124, the diffused oxygen atoms oxidize the polysilicon plug 116 to form a silicon oxide (SiO2) film on a top surface of the polysilicon plug 116, eventually resulting in an open-circuit between the capacitor and the pass-gate transistor. In particular, when using Pt as the bottom electrode, the diffusion barrier layer 122 helps to prevent the formation of PtSi film due to Si inter-diffusion phenomenon between the polysilicon plug 116 and the bottom electrode 124. The diffusion barrier layer 122 can be made of titanium nitride such as TiN, (Ti,Al)N, (Ti,Si)N, or the like. But, this Ti nitride barrier layer has a limitation in that it is also oxidized above 600° C. in oxygen rich atmosphere. Thus, a low dielectric film such as TiO2, Al2O3 or SiO2 is formed on a surface of the diffusion barrier layer 122 so that the electrical path between the capacitor and the pass-gate transistor is open-circuited.
The phenomenon of oxygen diffusion through the Pt electrode is illustrated in more detail hereinafter. When the oxygen atoms under the bottom electrode diffuse along the boundaries of Pt and reach to a position (XOX
) in the Pt electrode at a temperature (T) for a predetermined time (t), the distance to the position (XOX
) can be described as a function of the temperature (T) and the time (t).
Here, a constant D is the oxygen diffusion coefficient in Pt at the temperature (T), which is varied according to a grain type of Pt. From this equation, it is understood that if the distance (XOX) is greater than the thickness of the Pt electrode, oxidization will occur. On the contrary, if the distance (XOX) is less than the thickness of the Pt electrode, oxidization cannot occur.
Generally, the thickness of the Pt electrode formed by the conventional method is approximately 2,000 Å, when the grain type is a columnar type. Therefore, oxygen atoms may diffuse easily through the Pt electrode.
To overcome the above problem, various studies for inhibiting the oxygen diffusion have been carried out by using a hybrid electrode such as platinum/iridium (Pt/Ir), iridium oxide/iridium (IrO2/Ir), Pt/IrO2/Ir or platinum/ruthenium (Pt/Ru). But, the hybrid electrode has drawbacks in that it is expensive and further, difficult to fabricate, thereby decreasing productivity considerably.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device incorporating a capacitor structure for effectively inhibiting diffusion of oxygen atoms by forming a conductive plug of platinum (Pt) under a bottom electrode.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising steps of
a) preparing an active matrix provided with at least one transistor, conductive plugs electrically connected to the transistor(s) and an insulating layer formed around the conductive plugs;
b) patterning the insulating layer into a first predetermined configuration to form contact holes;
c) forming a diffusion barrier layer on an entire surface including the contact holes;
d) forming a seed layer on top of the diffusion barrier layer;
e) forming a first conductive layer and a conductive plug on top of the seed layer;
f) carrying out a thermal treatment for changing grains of the conductive plug into a granular type;
g) removing the first conductive layer, the diffusion barrier layer and the seed layer until a top surface of the insulating layer is exposed;
h) forming a second conductive layer on the conductive plug and the insulating layer;
i) patterning the second conductive layer into a second predetermined configuration to form a bottom electrode; and
j) forming a dielectric layer and then a third conductive layer on the bottom electrode and the insulating layer.
The process for manufacturing the semiconductor device begins with the preparation of an active matrix 210 including a silicon substrate 202, an isolation region 204, diffusion regions 206, 206A, gate oxides 208, gate lines 212, a sidewall 214, a bit line 218, and an insulating layer 220, as shown in FIG. 2A. The insulating layer 220, which may be made of boron-phosphor-silicate glass (BPSG), is patterned into a predetermined configuration, thereby obtaining contact holes 240, 242. The bit line 218 is electrically connected to one of the diffusion regions 206A to apply an electric potential. Although the bit line 218 actually lengthens in right and left directions bypassing the contact holes 240, 242, the drawing does not show these parts of the contact holes 240, 242.