US20010011917A1

US20010011917A1 - Dual-level voltage shifters for low leakage power

Info

Publication number: US20010011917A1
Application number: US09/779,909
Authority: US
Inventors: Hyungwon Kim; Yibin Ye
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1999-07-16
Filing date: 2001-02-08
Publication date: 2001-08-09
Anticipated expiration: 2019-07-16
Also published as: US6400206B2; WO2001006611A3; AU6107000A; TW480823B; WO2001006611A2; WO2001006611A8

Abstract

A dual level voltage shifter includes several series connections of transistors, and cross coupled pairs of transistors, to provide dual-level voltage shifting with low power consumption and low static current. In another embodiment, a dual level voltage shifter includes an inverter with current limiting diodes, and cross coupled inverters with a pass gate in their feedback loop, also providing low power consumption and low static current.

Description

FIELD

The present invention relates generally to voltage shifters, and more specifically to dual-level voltage shifters.

BACKGROUND

One of the most challenging problems confronting the designer in deep submicron circuits in today's technological society is leakage power which has increasingly become accountable for a significant portion of the total power consumption of such devices. Recent circuit techniques to reduce the leakage power in circuits have employed higher supply voltage to the circuit in an attempt to drive a leakage control device. One common type of leakage reduction technique comprises a sleep transistor whose gate node is driven by the additional supply voltages. A second type of leakage reduction technique changes the application circuit's body bias using the additional supply voltages. To switch between the standby and active modes, the sleep transistor's gate bias in the case of the first type of leakage reduction or the body bias of the circuit in the case of the second type of leakage reduction need to be switched between different voltage levels. This is accomplished through the use of a voltage shifter. Traditional voltage shifters, however, typically flow a significant amount of static current or support only single level voltage shifting.

For example, FIG. 1 shows a

voltage shifter

100 with static current flowing. Voltage shifter 100 comprises a series connection of p-type transistor 102 and n-type transistor 104 in series between voltage V_ccand ground. The gates of

transistors

102 and 104 are connected to each other.

Transistors

106 and 108 are connected in series between V_ppand V_nn, where V_pp=V_cc+ΔV and V_nn=ΔV. The gates of

transistors

106 and 108 connected to each other and to a node 110 between

transistors

102 and 104. An input voltage V_inis supplied to the gates of

transistors

102 and 104, and an output is generated from between

transistors

106 and 108. V_invaries from a logical one (V_cc) to a logical zero (0 V). V_outvaries from V_cc+ΔV to V_cc−ΔV.

When V _inis set to V_cc, transistor 104 is on and transistor 102 is off, but the ground voltage at node 110 is insufficient to completely shut off transistor 106, and a static current flows in path 112. When V_inis set to 0 V, transistor 104 is off and transistor 102 is on, but the voltage V_ccat node 110 is insufficient to completely shut off transistor 108, and a static current flows in path 114. Shifter 100 cannot be used for low power circuits.

Another example of a prior

art voltage shifter

200 is shown in FIG. 2. Voltage shifter 200 comprises p-type transistor 202 and n-type transistor 204 connected in series between voltage V_ppand V_nn, which is ground, and p-type transistor 206 and n-type transistor 208 also connected in series between V_ppand V_nn. (ground). An input voltage V_inis connected to the gate of transistor 204, and through inverter 210 to the gate of transistor 208. The gate of transistor 202 is connected at an output node defined between

transistors

206 and 208. The gate of transistor 206 is connected between transistors 202 and 204.

In this configuration, when V _inis equal to V_cc,

transistors

204 and 206 are on, and transistors 202 and 208 are off, and V_outis pulled to V_pp, which equals V_cc+ΔV, through transistor 206. When V_inis set to 0 V, transistors 202 and 208 turn on, and

transistors

204 and 206 turn off. In this instance, V_outis pulled to V_nn(ground) through transistor 208. In this single level voltage shifter, no static current flows. However, the circuit 200 is only a single level voltage shifter. If Vnn is set to −ΔV to achieve dual-level voltage shifting,

transistors

204 and 208 cannot be fully shut off and static current will flow. Shifter 200 cannot be used for leakage reduction.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a dual-level voltage shifter with no static current flow, and which is capable of use with low power circuits.

SUMMARY

In some embodiments, the invention includes first and second transistors connected in series, and third and fourth transistors connected in series, each series connection between a first potential and a second potential. The gates of the first and third transistors are connected to complementary inputs. Fifth and sixth transistors are also connected in series, and seventh and eighth transistors are also connected in series, each series connection between a third potential and the second potential. The gates of the fourth and sixth transistors are connected to a first node between the first and second transistors, and the gates of the second and eighth transistors are connected to a second node between the third and fourth transistors.

In other embodiments, a level shifter includes a first transistor configured as a diode, a first CMOS inverter, and a second transistor configured as a diode, the first transistor, first inverter, and second transistor connected in series between a first voltage connection and a second voltage connection. Further, a second inverter and a third inverter are connected in parallel between a third voltage connection and a fourth voltage connection. The second and the third inverters are cross coupled, and the output of the first inverter and the input of the second inverter are operatively coupled together. A pass gate is in the feedback loop between the second and the third inverters.

Other embodiments are described and claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a prior art voltage shifter; [0011]
FIG. 2 is a circuit diagram of a second prior art voltage shifter; [0012]
FIG. 3 is a circuit diagram of an embodiment of the present invention; [0013]
FIG. 4 is a diagram showing operation of the embodiment of FIG. 3; [0014]
FIG. 5 is a circuit diagram of an alternative embodiment of the present invention; [0015]
FIG. 6 is a diagram showing operation of the embodiment of FIG. 5; and [0016]
FIG. 7 is a block diagram of an integrated circuit embodiment according to one embodiment of the present invention. [0017]

DESCRIPTION OF EMBODIMENTS

In the following detailed description of the embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. [0018]
FIG. 3 shows an embodiment of a dual-[0019] level voltage shifter 300 of the present invention. Embodiment 300 comprises a first transistor 302 connected in series with a second transistor 304 between a first node 306 which is at a first potential, a second node 308 which is at a second potential, a third transistor 310 and a fourth transistor 312 also connected in series between first node 306 and second node 308, a fifth transistor 314 and a sixth transistor 316 connected in series between a third node 318 at a third potential and the second node 308, and a seventh transistor 320 and an eighth transistor 322 also connected in series between the third node 318 and the second node 308. The gates of first transistor 302 and third transistor 310 are coupled to complementary inputs V_inand V_in*.
A [0020] node 324 is defined at the connection of first transistor 302 and second transistor 304. Node 324 is coupled to the gates of fourth transistor 312 and sixth transistor 316. Another node 326 is defined at the connection of third transistor 310 and fourth transistor 312. Node 326 is coupled to the gates of second transistor 304 and eighth transistor 322. The gate of fifth transistor 314 is coupled to the connection between seventh transistor 320 and eighth transistor 322. The gate of seventh transistor 320 is coupled to an output node 328 defined at the connection between fifth transistor 314 and sixth transistor 316.
[0021] Transistors 302, 310, 314, and 320 are in one embodiment p-type transistor switches which are closed (on) between their source and drain when their gate is at a low potential, and which are open (off) between their source and drain when their gate is at a high potential. Transistors 304, 312, 316, and 322 are in one embodiment n-type transistors transistor switches which are closed (on) between their source and drain when their gate is at a high potential, and which are open (off) between their source and drain when their gate is at a low potential. The input potential V_invaries from a logical one (V_cc) to a logical zero (0 V). Its complement V_in* varies from a logical zero (0 V) to a logical one (V_cc). In the dual-level voltage shifter embodiment 300, first node 306 is at a supply voltage V_cc, second node 308 is at V_nn=−ΔV, and third node 318 is at V_pp=V_cc+ΔV.
In operation, [0022] embodiment 300 functions as follows. When V_inis a logical zero (0 V), transistor 302 turns on, pulling the potential at node 324 to V_cc, turning on transistors 312 and 316. Output node 328 is pulled to V_nnthrough transistor 316. On the transition of V_into V_cc, transistor 302 turns off, and transistor 310 turns on. Node 326 is pulled to V_ccthrough transistor 310, turning transistors 304 and 322 on. Node 324 is pulled to V_nnthrough transistor 304. Node 330 is pulled to V_nnthrough transistor 322, and transistor 314 turns on, pulling output node 328 to V_pp. The transitions of node 324 and output node 328 are fast due to the cross coupled feedback connections between transistors 314 and 320 or 304 and 312.
Since at least one device in every potential static current path of [0023] embodiment 300 is completely shut off, there is no static current flow in embodiment 300. The voltage shifting accomplished by embodiment 300 is dual-level, with output node 328 voltage shifting between V_ppand V_nn. The voltages V_ppand V_nncan be set to virtually any voltages. In one embodiment, V_pp=V_cc+ΔV and V_nn=−ΔV.
A partial timing diagram showing the operation of [0024] embodiment 300 is shown in FIG. 4. As V_inrises from ground (logical zero) to V_cc(logical one), the voltage at node 328 rises from V_nnto V_pp, and the voltage at node 324 drops from V_ccto V_nn.
FIG. 5 shows another embodiment [0025] 500 of a dual-level voltage shifter. Embodiment 500 comprises a first branch comprising first transistor 502 and second transistor 504 connected in series between third transistor 506 and fourth transistor 508, a second branch comprising a fifth transistor 510 and a sixth transistor 512 connected in series and a seventh transistor 514 and an eighth transistor 516 connected in series, and a pass gate 518.
[0026] Transistors 506 and 508 are connected as current limiting diodes, transistor 506 having its gate connected between transistor 506 and transistor 502, and transistor 508 having its gate connected between transistor 508 and transistor 504. The series connection of transistors 506, 502, 504, and 508 is connected between a first node 520 at a first potential, and a second node 522 at a second potential. In one embodiment, node 520 is at V_cc(logic one) and node 522 is at ground (logic zero). The series connections of transistors 510 and 512, and 514 and 516, are connected in parallel between a third node 524 which is at a third potential, and a fourth node 526 which is at a fourth potential. In one embodiment, node 524 is at V_pp=V_cc+ΔV, and node 526 is at −ΔV.
[0027] Pass gate 518 comprises two transistors 530 and 532 connected in parallel. As shown in FIG. 5, transistor 530 is an n-type transistor and transistor 532 is a p-type transistor. The gates of the transistors 530 and 532 are connected to complementary inputs V_enand V_en*, respectively.
[0028] Pass gate 518 is connected between node 534 and node 536. Node 534 is also connected to the gates of transistors 510 and 512, and between transistors 502 and 504. Node 536 is connected between transistors 514 and 516. An output node 538 is defined between transistors 510 and 512, and is also connected to the gates of transistors 514 and 516.
[0029] Transistors 510 and 512 form a first inverter, and transistors 514 and 516 form a second inverter. The first and second inverters are cross coupled, and pass gate 518 is in the feedback loop. Transistors 502 and 504 form an inverter, and transistors 506 and 508 act as current limiting diodes. The pass gate 518 substantially instantaneously disconnects the feedback loop of the cross coupled inverters to avoid large current involved to flip the cross coupled inverters' state.
The operation of the embodiment [0030] 500 is shown in greater detail in FIG. 6. Pass gate 518 is always on when the potential V_enis at logic one. When voltage shifting occurs, pass gate 518 disconnects the feedback loop to avoid the large current involved in flipping the state of the cross coupled inverters. When V_inis logic zero and voltage V_en=logic one, node 534 is initially pulled to near V_ccthrough transistor 502, with current limited by diode 506, while transistor 504 is turned off. Transistor 510 is turned off and transistor 512 is turned on, and node 538 is pulled to V_nnthrough transistor 512. This in turn turns transistor 514 on and transistor 516 off. Node 536 is pulled to V_ppthrough transistor 514. The pass gate 518 passes potential V_ppto node 534. Output node 538 is held at the potential coupled to node 526.
To shift the voltage level of embodiment [0031] 500, V_enis set to logic zero, and V_inis raised to logic one (V_cc). When this occurs, transistor 502 shuts off and transistor 504 turns on. The voltage at node 534 is pulled to V_thabove ground through transistor 504, with current limited by diode 508, and transistor 508 begins to enter its cutoff region. As the potential at node 534 decreases, output voltage at output node 538 approaches V_pp, turning transistor 516 on and turning transistor 514 off. Voltage at node 536 is pulled to V_nnthrough transistor 516. V_enis then raised to logic one, connecting the feedback loop through pass gate 518, pulling the potential at node 534 to V_nn. As the potential at node 534 drops, transistor 510 turns on and transistor 512 turns off, pulling output node 538 to V_ppthrough transistor 510.
When V[0032] _inis lowered to logic zero, transistor 504 shuts off, and transistor 502 turns on. This pulls node 534 to near V_ccthrough transistor 502, with current limited by diode 506. The potential at node 534 turns transistor 510 off and transistor 512 on. Node 538 is pulled to V_nnthrough transistor 512. The potential at node 538 turns transistor 514 on and transistor 516 off, pulling node 536 to V_ppthrough transistor 514. Pass gate 518 passes potential V_ppto node 534, and output node 538 is held at V_nn.
Although [0033] transistor 504 can conduct static current from ground potential 522 to V_nndue to its forward bias when V_inis at logic one, the current is shut off by transistor 508 which is under a reverse bias. Likewise, when V_inis lowered to logic zero, static current flow through transistor 502 is shut off by transistor 506.
No static current flows in embodiment [0034] 500. Embodiment 500 provides dual-level voltage shifting between V_nnand V_ppwith no static current. The input potentials V_enand V_en* coupled to the gates of pass gate transistors 530 and 532, respectively, may be generated from the rising and falling transitions of V_in.
As supply voltage V[0035] _ccto the application circuit is lowered to reduce the active power of the circuits, the threshold voltage is lowered as well to maintain the speed of the circuit. The low threshold voltage drastically increases the leakage current up to a significant portion of the total power consumed by the application circuit. Leakage reduction techniques that shut off leakage current of idling blocks or an entire microchip in standby mode are becoming important. These techniques require low power voltage level shifting to switch the voltage level of the supplies. The voltage level shifters of the present invention provide dual-level voltage shifting required by modem components without generating static current. They are therefore well suited to leakage reduction techniques.
FIG. 7 illustrates a block diagram of an [0036] integrated circuit 700 that comprises an embodiment of the present invention dual-level voltage shifter circuit 704 driving an application integrated circuit 706. The circuit 704 receives an input voltage 702 and its complement 702*, and supply voltages 708, connected to V_pp, and 710, connected to V_nn. The circuit 704 switches its output 716's voltage level between V_ppand V_nn. The application integrated circuit 706 receives the regular supply voltages 712, connected to V_cc, and 714, connected to GND, and receives the shifted voltage 716 from the circuit 704. The dual-level voltage shifter circuit 704 can be arranged as described above with respect to FIGS. 3 and 5. The application integrated circuit may be of any type, including but not limited to a processor, memory, memory controller, or application-specific integrated circuit (ASIC).
As shown in FIG. 7, the [0037] integrated circuit 700 may be part of a computer system 750. Such a system could include a desktop system, a portable system, or the like.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. [0038]

Claims

What is claimed is:

1. A voltage level shifter, comprising:

first and second transistors connected in series between a first and a second

node, and third and fourth transistors connected in series between the first and the second node, the gates of the first and third transistors connected to complementary input connections;

fifth and sixth transistors connected in series between a third node and the

second node, and seventh and eighth transistors connected in series between the third node and the second node, the gates of the fourth and sixth transistors connected to a first internal node between the first and second transistors, and the gates of the second and eighth transistors connected to a second internal node between the third and fourth transistors.

2. The voltage level shifter of

claim 1

, wherein the first, third, fifth and seventh transistors are each a p-type transistor.

3. The voltage level shifter of

claim 1

, wherein the second, fourth, sixth and eighth transistors are each an n-type transistor.

4. The voltage level shifter of

claim 1

, wherein the first node is coupled to a first potential and the second node is coupled to a second potential, and wherein the first potential is higher than the second potential.

5. The voltage level shifter of

claim 1

, wherein the third node is coupled to a third potential higher than the first potential.

6. The voltage level shifter of

claim 1

, wherein the voltage level shifter is in a computer system.

7. A dual-level voltage shifter, comprising:

a first p-type and a second n-type transistor connected in series between a

first node coupled to a first potential and a second node coupled to a second potential, and a third p-type and a fourth n-type transistor connected in series between the first voltage connection and the second node, the gates of the first and third transistors connected to complementary inputs;

a fifth p-type and a sixth n-type transistor connected in series between a third

node coupled to a third potential and the second node, and a seventh p-type and an eighth n-type transistor connected in series between the third node and the second node, the gates of the fourth and sixth transistors connected to a first internal node between the first and second transistors, and the gates of the second and eighth transistors connected to a second internal node between the third and fourth transistors.

8. The dual-level voltage shifter of

claim 6

, wherein the second potential is a predetermined potential below ground.

9. The dual-level voltage shifter of

claim 6

, wherein the third potential is a predetermined potential above the first potential.

10. The dual-level voltage shifter of

claim 6

, wherein the second potential is a predetermined potential below ground potential, and the third potential is the predetermined potential above the first potential.

11. A dual-level voltage shifter, comprising:

a first branch comprising first, second, third, and fourth transistors connected

in series between a first node and a second node, the first and fourth transistors configured as diodes, and the gates of the second and third transistors connected to each other;

a second branch comprising fifth and sixth transistors, and a third section

comprising seventh and eighth transistors, the second and the third sections each connected in series between a third node and a fourth node;

a pass gate connected between a node defined between the second and third

transistors, and between the seventh and eighth transistors;

a node defined between the second and third transistors, and connected to the

gates of the fifth and sixth transistors; and

the gates of the seventh and eighth transistors connected to a node defined

between the fifth and sixth transistors.

12. The voltage shifter of

claim 11

, wherein the pass gate comprises two transistors connected in parallel, one p-type transistor and one n-type transistor, the gates of the pass gate transistors connected to complementary inputs.

13. The voltage shifter of

claim 11

, wherein the first, second, fifth, and seventh transistors are each a p-type transistor.

14. The voltage shifter of

claim 11

, wherein the third, fourth, sixth, and eighth transistors are each an n-type transistor.

15. A dual-level voltage shifter, comprising:

a first transistor configured as a diode, a first CMOS inverter, and a second

transistor configured as a diode, the first transistor, first inverter, and second transistor connected in series between a first node and a second node;

a second inverter and a third inverter connected in parallel between a third

node and a fourth node, the second and the third inverters cross coupled, the output of the first inverter and the input of the second inverter operatively coupled together; and

a pass gate in the feedback loop between the second and the third inverters.

16. The voltage shifter of

claim 15

, wherein the third node is coupled to an output potential and the first node is coupled to a supply potential, the output potential greater than the supply potential.

17. The voltage shifter of

claim 15

, wherein the fourth node is coupled to a second output potential and the second voltage connection is coupled to ground, and wherein the second output potential is lower than ground potential.

18. The voltage shifter of

claim 15

19. The voltage shifter of

claim 15

, wherein the first inverter comprises a pair of transistors, the transistors comprising one p-type transistor and one n-type transistor, the gate of each transistor coupleable to an input voltage.

20. The voltage shifter of

claim 15

, wherein the second inverter comprises a pair of transistors, the transistors comprising one p-type transistor and one n-type transistor.

21. The voltage shifter of

claim 15

, wherein the third inverter comprises a pair of transistors, the transistors comprising one p-type transistor and one n-type transistor.

22. The voltage shifter of

claim 14

, wherein the voltage shifter is in a computer system.

23. A computer system, comprising:

a computer with a motherboard having a processor operatively coupled to the

motherboard; and

the processor having an integrated circuit comprising:

a first input connection for receiving an input voltage signal; and

a dual-level voltage shifter circuit coupled to receive the input voltage signal,

the voltage shifter circuit comprising:

first and second transistors connected in series between a first and a

second node, and third and fourth transistors connected in series between the first and the second node, the gates of the first and third transistors connected to complementary input connections;

fifth and sixth transistors connected in series between a third node and

the second node, and seventh and eighth transistors connected in series between the third node and the second node, the gates of the fourth and sixth transistors connected to a first internal node between the first and second transistors, and the gates of the second and eighth transistors connected to a second internal node between the third and fourth transistors.

24. The computer system of

claim 23

25. The computer system of

claim 23

26. A computer system, comprising:

a computer with a motherboard having a processor operatively coupled to the

motherboard; and

the processor having an integrated circuit comprising:

a first input connection for receiving an input voltage signal; and

the voltage shifter circuit comprising:

a first transistor configured as a diode, a first CMOS inverter, and a

second transistor configured as a diode, the first transistor, first inverter, and second transistor connected in series between a first node and a second node;

a second inverter and a third inverter connected in parallel between a

third node and a fourth node, the second and the third inverters cross coupled, the output of the first inverter and the input of the second inverter operatively coupled together; and

a pass gate in the feedback loop between the second and the third

inverters.

27. The computer system of

claim 26

28. The computer system of

claim 26

, wherein the fourth node is coupled to a second output potential and the second node is coupled to ground, and wherein the second output potential is lower than ground potential.

29. The computer system of

claim 26

30. The computer system of

claim 26

31. The computer system of

claim 26

32. The computer system of

claim 26