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Publication numberUS20010013615 A1
Publication typeApplication
Application numberUS 09/024,601
Publication dateAug 16, 2001
Filing dateFeb 17, 1998
Priority dateFeb 17, 1998
Also published asUS6384446
Publication number024601, 09024601, US 2001/0013615 A1, US 2001/013615 A1, US 20010013615 A1, US 20010013615A1, US 2001013615 A1, US 2001013615A1, US-A1-20010013615, US-A1-2001013615, US2001/0013615A1, US2001/013615A1, US20010013615 A1, US20010013615A1, US2001013615 A1, US2001013615A1
InventorsKuo-Hua Lee, Simon John Molloy, Daniel Joseph Vitkavage
Original AssigneeKuo-Hua Lee, Simon John Molloy, Daniel Joseph Vitkavage
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuit fabrication
US 20010013615 A1
Abstract
An improved method of capacitor formation is disclosed. A dielectric is etched with a etch recipe which creates grooves within an opening. The opening is filled with metal which conforms to the grooves, thereby creating a capacitor's lower plate with increased surface area. The metal is later surrounded with dielectric and metal, which forms respectively the capacitor's dielectric and upper plate.
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Claims(18)
What is claimed:
1. A method of integrated circuit fabrication comprising:
forming a conductive plug having an outer surface with grooves; and
forming a dielectric which fills said grooves; and
forming a conductive material over said dielectric; said conductive plug, said dielectric, and said conductive material together comprising a capacitor.
2. A method of integrated circuit fabrication comprising:
forming a patterned photoresist upon a first material layer; and
etching said first material layer by a process which forms grooves in said photoresist.
3. The method of
claim 2
in which said grooves in said photoresist are transferred to material layer, thereby producing grooves in said material layer.
4. The method of
claim 2
in which said first material layer is a dielectric.
5. The method of
claim 4
in which said material layer is an oxide of silicon.
6. The method of
claim 4
in which an opening defined by a wall is formed in said dielectric, said grooves being present in said wall.
7. The method of
claim 6
in which a second material is formed conformally within said opening, said second material having a wall with grooves.
8. The method of
claim 7
in which a portion of said first material layer is removed, thereby exposing said wall of said second material.
9. The method of
claim 8
in which a third material is formed overlying said wall of said second material.
10. The method of
claim 9
in which a fourth material is conformally formed upon said third material.
11. The method of
claim 10
in which said fourth and second materials are conductive and said third material is dielectric, said second third and fourth materials thereby forming a capacitor.
12. A method of integrated circuit fabrication comprising:
forming a transistor upon a substrate; and
forming a first dielectric overlying said substrate and said transistor; and
forming an opening within said first dielectric; said opening being defined by a wall with grooves; and
forming at least one first conductive material within said opening, said first conductive material having a respective wall with grooves; and
forming a second dielectric covering a portion of said wall of said first conductive material; and
forming a second conductor covering said second dielectric.
13. A method of integrated circuit fabrication comprising:
forming a gate upon a silicon substrate; and
forming a source/drain within said silicon substrate; and
forming a first planarized TEOS dielectric over said gate and said substrate; and
forming a window in said first planarized TEOS dielectric, exposing said source/drain; and
forming a tungsten plug within said window; and
forming a second TEOS dielectric over said first TEOS dielectric; and
forming a window in said second TEOS dielectric, said window being defined by a wall with grooves; and
forming a first layer of titanium within said window, said first titanium layer having an outer wall with grooves; and
forming a first layer of titanium nitride within said window and contacting said layer of titanium; and
forming a tungsten plug within said window and contacting said first layer of titanium nitride; and
forming an opening in said second dielectric exposing said outer wall of said layer of titanium; and
forming a layer of tantalum pentoxide covering said exposed outer wall of said layer of titanium; and
forming a patterned second layer of titanium nitride in contact with said layer of tantalum pentoxide; and
forming a patterned second layer of titanium in contact with said second layer of titanium nitride; and
forming a patterned layer of aluminum in contact with said second patterned layer of titanium.
14. An integrated circuit comprising:
a first conductor having a wall with grooves; and
a dielectric contacting said conductor; and
a second dielectric contacting said dielectric; and
said first and second conductors and said dielectric together comprising a capacitor.
15. The device of
claim 14
in which said first conductor is titanium.
16. The device of
claim 14
in which said dielectric is tantalum pentoxide.
17. The device of
claim 14
in which said second conductor is titanium nitride.
18. An integrated circuit comprising:
a transistor; and
a first dielectric covering said transistor; and
a conductive plug partially embedded in said dielectric: said conductive plug having a top and a wall, said wall having grooves; and
a second dielectric covering said plug top and a portion of said grooved wall; and
a patterned conductive layer covering said second dielectric.
Description
    TECHNICAL FIELD OF THE INVENTION
  • [0001]
    This invention relates to methods of integrated circuit fabrication and the devices produced thereby.
  • BACKGROUND OF THE INVENTION
  • [0002]
    It is becoming increasingly popular in the manufacture of modern integrated circuits to include intergral capacitors within the integrated circuit. For example, many DRAM designs and many analog designs include intergral capacitors within an integrated circuit chip. Often the capacitors are made by trenching into the silicon substrate.
  • [0003]
    Those concerned with the development of integrated circuits have consistently sought new capacitor designs and methods for forming these designs. Of particular interest are fabrication methods which produce capacitors with increased capacitance within small volumes.
  • SUMMARY OF THE INVENTION
  • [0004]
    An improved method of integrated circuit fabrication and an improved integrated circuit address the above concerns.
  • [0005]
    A first illustrative embodiment includes a method of integrated circuit fabrication which includes forming a conductive plug having an outer surface with grooves;
  • [0006]
    forming a dielectric which fills the grooves; and
  • [0007]
    forming a conductive material over the dielectric; the conductive plug, the dielectric, and the conductive material together comprising a capacitor.
  • [0008]
    A second illustrative embodiment includes a method of integrated circuit fabrication which includes forming a patterned photoresist upon a first material layer; and
  • [0009]
    etching the first material layer by a process which forms grooves in the photoresist.
  • [0010]
    A third illustrative embodiment includes a method of integrated circuit fabrication which includes forming a transistor upon a substrate;
  • [0011]
    forming a first dielectric overlying the substrate and the transistor;
  • [0012]
    forming an opening within the first dielectric; the opening being defined by a wall with grooves;
  • [0013]
    forming at least one first conductive material within the opening, the first conductive material having a respective wall with grooves;
  • [0014]
    forming a second dielectric covering a portion of the wall of the first conductive material; and
  • [0015]
    forming a second conductor covering the second dielectric.
  • [0016]
    A fourth illustrative embodiment includes an integrated circuit which includes:
  • [0017]
    a first conductor having a wall with grooves;
  • [0018]
    a dielectric contacting the conductor;
  • [0019]
    a second dielectric contacting the dielectric;
  • [0020]
    the first and second conductors and the dielectric together comprising a capacitor.
  • [0021]
    A fifth illustative embodiment includes an integrated circuit which includes:
  • [0022]
    a transistor;
  • [0023]
    a first dielectric covering the transistor;
  • [0024]
    a conductive plug partially embedded in said dielectric; the conductive plug having a top and a wall, the wall having grooves;
  • [0025]
    a second dielectric covering the plug top and a portion of the grooved wall; and
  • [0026]
    a patterned conductive layer covering the second dielectric.
  • BRIEF DESCRIPTION OF THE DRAWING
  • [0027]
    [0027]FIGS. 1 and 2 are cross-sectional views of an illustrative embodiment of the present invention; and
  • [0028]
    [0028]FIG. 3 is plan view of a portion of the integrated circuit shown in FIG. 2; and
  • [0029]
    [0029]FIGS. 4, 5 and 6 are also partial cross-sectional views of an illustrative embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0030]
    Turning to FIG. 1, reference numeral 11 denotes a substrate which may be silicon, epitaxial silicon, doped silicon, etc. Reference numeral 13 denotes, illustratively a gate which may include spacers 16 and 18, dielectric 14, and conductor 20. Reference numeral 15 denotes a source/drain. Reference numeral 17 denotes a dielectric which may, illustratively be an oxide of silicon, perhaps formed from a chemical precursor such as TEOS. Desirably, the upper surface 21 of dielectric 17 is planarized or considerably smoothed, illustratively by chemical mechanical polishing (CMP), or other means. Reference numeral 19 denotes a conductive material, illustratively a plug contacting source/drain 15. Illustratively, conductor 19 may be a tungsten plug (or a copper plug). Plug 19 may, if desired, be surrounded by layers of titanium or titanium nitride. By way of illustration, dielectric 17 may be approximately 8000 Å thick over source/drain 15, and 6000 Å thick over gate 13. The dimensions of plug may be, for example, 0.24 microns by 0.24 microns. Should the titanium and titanium nitride be utilized with plug 19, illustrative thicknesses are roughly 200 Å of titanium, 600 Å of titanium nitride.
  • [0031]
    Turning to FIG. 2, metal runner 25 is formed on top surface 21 of dielectric 17. By way of illustration, metal runner 25 might be formed from 300 Å of titanium, 600 Å of titanium nitride, with 4500 Å of aluminum, capped with 250 Å of titanium nitride. Dielectric 23 is next deposited over runner 25. Illustratively, dielectric 23 may be an oxide of silicon, perhaps formed by the decomposition of the chemical precursor such as TEOS. Illustratively, the thickness of dielectric 23 may be 0.8 microns.
  • [0032]
    Next, window 27 is opened in dielectric 23. Illustratively, window 27 also partially penetrates dielectric 17 due to over etching of the window. (The over-etched window facilitates contact with later-formed layers 33, 35 and 37 in FIG. 4.) By way of illustration, the dimensions of window 27 may be 0.24 microns by 0.74 microns.
  • [0033]
    Applicants have discovered an etching process which creates a multiplicity of grooves 29 in the sidewall of window 27. (Subsequent processing steps, to be described in later detail below, will show how window 27 is filled with a conductive material which later forms the bottom plate of a capacitor. Thus, the creation of grooves 29 makes it possible to form a capacitor's bottom plate having increased surface area. Consequently, it is possible to form a capacitor with desirably increased capacitance within a small volume.)
  • [0034]
    As mentioned before, dielectric 23 is a oxide of silicon, illustratively formed by the decomposition of a plasma precursor such as TEOS. Illustratively, window 27 is etched in a chemical reactor such as lam 9500, manufactured by Lam Research Corp., Fremont, Calif. A Shipley photoresist, for example that designated SPR 950, manufactured by Shipley Company, Marlborough, Mass. illustratively may be used. A typical exposure time is 500 milliseconds. The thickness of the photoresist may be approximately 7600 Å. A 600 watt bias power maybe applied to the lower electrode and zero watt source power may be used. Etching gases may be CHF3 (170 cc/min.), C2F6 (30 cc/min.) and Ar (120 cc/min.). Typical chamber pressure may be 30 milliTorr, with a range of 20-40 milliTorr being acceptable. Typical window depth may be approximately 1 micron. The tolerance for each of the above parameters is 10%. Applicants have found that the above-described etching process tends to form grooves in the photoresist. These grooves are then transferred to the inside of the dielectric window 27, thus forming grooves 29. It is noticed that preferred processing tends toward thinner photoresist. Thinner photoresist has been observed to be more amenable to groove formation. Photoresist thicknesses above 10,000 Å tend to produce very little or no grooving. More conventional oxide etch chemistries using C4F8 and C2F6 tend to produce smooth walls or at best, insignificant grooves.
  • [0035]
    In addition, opening 31 is also formed over runner 25. (Opening or window 31 also has the above-mentioned grooves since it is formed during the same etching process.)
  • [0036]
    [0036]FIG. 3 shows a top down view of opening 27 with grooves 29. The upper surface of plug 19 protruding into opening 27 is illustrated. Typically, the grooves are characterized by sharp exterior points and depths of 200-500 Å.
  • [0037]
    Turning to FIG. 4, openings 27 and 31 are first filled with, illustratively 200 Å titanium (reference numeral 33); 600 Å titanium nitride (reference numeral 35); and a 4000 Å tungsten plug (reference numeral 37). Other conductors may be used for plug 37 and layers 35 and 33 eliminated. CMP may be utilized to smooth the upper surfaces of tungsten plug 37 (and layers 35 and 33), thereby making it flush with the upper surface of dielectric 23. Titanium layer 33 fills grooves 29 and opening 27, thereby later creating a capacitor's bottom plate with greater surface area than would be obtained if opening 27 had conventional, comparatively smooth sides.
  • [0038]
    Turning to FIG. 5, opening 39 is created by anisotropically etching a trench around tungsten plug 37 together with titanium nitride 35 and titanium 33. Outer surface 103 of titanium layer 33 exhibits grooves defined by its deposition within grooved dielectric 23. Thus, grooved dielectric functions as a mold for the outer surface of titanium layer 33. Of course, the grooves in surface 103 are complementary to grooves 29 in dielectric 23. Opening 39 is filled, illustratively with a dielectric having a high dielectric constant, for example 100 Å of Ta2O5 (in FIG. 6). It will be noted that Ta2O5 layer 43 coats the inside of opening 39 (generally conformal to the grooves in layer 33), covers the top surfaces of tungsten 37, titanium nitride 35, and titanium 33, and also covers a small portion 91 of the upper surface 93 of dielectric 23. Thus, dielectric 43 also exhibits grooves due to its conformal deposition.
  • [0039]
    A variety of single or multi-layer conductors may be deposited over dielectric 43 to form the upper plate of the capacitor. For example, reference numeral 45 may denote, illustratively 1000 Å of titanium nitride (which becomes generally conformal to dielectric 43); reference numeral 47 may denote 300 Å of titanium; reference numeral 49 may denote 600 Å of titanium nitride; and reference numeral 51 may denote 4500 Å of aluminum. Then conductors may also form runner 101.
  • [0040]
    Capacitors formed by applicants' process have been formed to exhibit 30-40% more capacitance per volume than capacitors formed without grooves.
  • [0041]
    It will be noted in FIG. 3 that opening 27 is depicted with a round cross section, although many lithographic reticles have square shaped reticles. However, as those skilled in the art know, the shape of the window produced in an oxide 23 is generally somewhat rounded as shown in FIG. 3. (Of course, as mentioned before, the overall shape of applicant's window is modulated by grooves 29.)
  • [0042]
    The thicknesses of layers of titanium, titanium nitride, tungsten, silicon dioxide, etc. above are ideal and may be expected to vary approximately 10%.
  • [0043]
    Further processing, including the deposition and planarization of additional dielectrics, etc., may take place at this point.
  • [0044]
    The inventive concept may be also adapted by those skilled in the art to damascene processes which may illustratively use copper. For example, the tungsten plug 37 (with or without additional layers such as 35, 33) may be replaced by copper.
  • [0045]
    Other conductors may also be damascene copper (e.g. 45 or 47 or 49).
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6806574 *Jan 31, 2002Oct 19, 2004Samsung Electronics Co., Ltd.Semiconductor device having multilevel interconnections and method of manufacturing the same
US7074712Jul 29, 2004Jul 11, 2006Samsung Electronics Co., Ltd.Semiconductor device having multilevel interconnections and method of manufacturing the same
US20020185740 *Jan 31, 2002Dec 12, 2002Samsung Electronics Co., Ltd.Semiconductor device having multilevel interconnections and method of manufacturing the same
US20050003657 *Jul 29, 2004Jan 6, 2005Samsung Electronics Co., Ltd.Semiconductor device having multilevel interconnections and method of manufacturing the same
Classifications
U.S. Classification257/296, 257/E21.018, 257/E21.649, 257/309
International ClassificationH01L21/8242, H01L21/02
Cooperative ClassificationH01L28/90, H01L27/10855
European ClassificationH01L28/90
Legal Events
DateCodeEventDescription
Jun 8, 1998ASAssignment
Owner name: LUCENT TECHNOLOGIES INC., NEW JERSEY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, KUO-HUA;MOLLOY, SIMON JOHN;VITKAVAGE, DANIEL JOSEPH;REEL/FRAME:009254/0392;SIGNING DATES FROM 19980211 TO 19980225
Nov 3, 2005FPAYFee payment
Year of fee payment: 4
Nov 4, 2009FPAYFee payment
Year of fee payment: 8
Oct 9, 2013FPAYFee payment
Year of fee payment: 12
May 8, 2014ASAssignment
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG
Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031
Effective date: 20140506
Apr 3, 2015ASAssignment
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGERE SYSTEMS LLC;REEL/FRAME:035365/0634
Effective date: 20140804
Feb 2, 2016ASAssignment
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039
Effective date: 20160201
Owner name: LSI CORPORATION, CALIFORNIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039
Effective date: 20160201