Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010013657 A1
Publication typeApplication
Application numberUS 08/915,398
Publication dateAug 16, 2001
Filing dateAug 20, 1997
Priority dateAug 21, 1996
Also published asCN1096116C, CN1174409A, DE69721411D1, DE69721411T2, EP0825646A2, EP0825646A3, EP0825646B1, US6362528, US6500748, US6720658, US20020020918, US20030062625
Publication number08915398, 915398, US 2001/0013657 A1, US 2001/013657 A1, US 20010013657 A1, US 20010013657A1, US 2001013657 A1, US 2001013657A1, US-A1-20010013657, US-A1-2001013657, US2001/0013657A1, US2001/013657A1, US20010013657 A1, US20010013657A1, US2001013657 A1, US2001013657A1
InventorsMinakshisundaran B. Anand
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and method of manufacturing the same
US 20010013657 A1
Abstract
In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.
Images(22)
Previous page
Next page
Claims(13)
1. A semiconductor device having a bonding pad constituted by a conductive member filled in grooves made in an insulating layer having a flat surface, said semiconductor device comprising:
an etching stopper layer formed on said insulating layer and having an opening to expose said bonding pad; and
a passivation layer formed on said etching stopper layer and having an opening to expose said bonding pad.
2. A semiconductor device according to
claim 1
, wherein said grooves in said insulating layer are arranged in a lattice manner, and said bonding pad has a lattice-like shape.
3. A semiconductor device according to
claim 1
, wherein said insulating layer and said passivation layer are made of silicon oxide, and said etching stopper layer is made of silicon nitride.
4. A semiconductor device according to
claim 1
, further comprising wirings filled in said grooves of said insulating layer.
5. A semiconductor device according to
claim 1
, wherein said bonding pad and said wirings are constituted by a first metal layer and a second metal layer made of a metal different from that of the first metal layer, respectively.
6. A semiconductor device according to
claim 1
, wherein the first metal layer is made of titanium and titanium nitride, or silicon titanium nitride, and the second metal layer is made of aluminum, copper or an alloy thereof.
7. A semiconductor device according to
claim 1
, further comprising a wire connected to said bonding pad.
8. A method of manufacturing a semiconductor device, in which a bonding pad is formed by making grooves in an insulating layer having a flat surface and filling the grooves with a conductive material, the method including the stops of:
forming said bonding pad by filling said grooves of said insulating layer with said conductive material;
forming an etching stopper layer on said insulating layer and the bonding pad, said etching stopper layer being made of a material which can be etched selectively with respect to at least a material which is used to form said insulating layer;
forming a passivation layer on said etching stopper layer, said passivation layer being made of a material which can be etched selectively with respect to at least the material used to form said etching stopper layer;
removing only a portion of said passivation layer, which is situated above the bonding pad; and
removing only a portion of said etching stopper layer, which is situated above the bonding pad.
9. A method of manufacturing a semiconductor device, according to
claim 8
, wherein said bonding pad is formed by a step of forming a conductive material on said insulating layer so as to completely fill said grooves therewith, and a step of polishing said conductive material by a CMP technique.
10. A method of manufacturing a semiconductor device, according to
claim 8
, wherein said passivation layer is etched by an RIE technique and said etching stopper layer is etched by an RIE or CDE technique.
11. A method of manufacturing a semiconductor device, according to
claim 8
, wherein said bonding pad and said wirings are formed at the same time by filling said grooves with the conductive material.
12. A method of manufacturing a semiconductor device, according to
claim 8
, wherein said bonding pad and said wirings are formed by a dual damascening process or damascening process.
13. A method of manufacturing a semiconductor device, according to
claim 8
, wherein a wire is connected to said bonding pad in a wire bonding process.
Description
BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device having a multi-layer wiring structure made by a damascening process or a dual damascening process, and a method of manufacturing such a device.

[0002] An ultra-large scale integrated circuit (ULSI) employs a multilayer wiring structure in which wiring layers of three levels or more are formed.

[0003]FIGS. 1 and 2 show a semiconductor device prepared by a conventional wiring process. FIG. 2 is a cross sectional view taken along the line II-II indicated in FIG. 1.

[0004] As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.

[0005] On the semiconductor substrate 11, an insulating layer 15 is formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layer 15 from its surface to be through to the source-drain region 13. On the insulating layer 15, a first-level wiring layer having a plurality of wiring layers 17 is formed. Each of the plurality of wiring layers 17 is connected to the source-drain region 13 of the MOS transistor via the contact hole 16.

[0006] On the insulating layer 15, an insulating layer (interlayer dielectric) 18 is formed so as to completely cover the plurality of wiring layers 17. A contact hole 19 is made in the insulating layer 18 from its surface to be through to the plurality of wirings 17. On the insulating layer (interlayer dielectric) 18, a second-level wiring layer having a plurality of wiring layers 20 is formed. Each of the plurality of wiring layers 20 is connected to the wiring layers 17 of the first-level wiring layers via the contact hole 19.

[0007] On the insulating layer (interlayer dielectric) 18, a bonding pad 21 is formed. Further, on the insulating layer (interlayer dielectric) 18, an insulating layer (passivation dielectric) 22 is formed so as to completely cover the plurality of wiring layers 20 and the bonding pad 21. An opening 23 is made in the insulating film (passivation dielectric) 22 so as to expose the bonding pad 21.

[0008] In a semiconductor device manufactured by the conventional wiring process, a plurality of wirings 17 of the first-level wiring layer, a plurality of wirings 20 of the second-level wiring layer and the bonding pad 21 are formed by a photo engraving process (PEP), in which, a resist pattern is formed, and using the resist pattern as a mask, metal layers are etched by an anisotropic etching (such as RIE).

[0009] However, in an ULSI, the distance between wirings of the same level is becoming very narrow.

[0010] Therefore, the following drawbacks begin to arise.

[0011] First, it is very difficult to accurately pattern the wirings 17 and 20 of the wiring layers. This is because the resolution of the exposing device for forming resist patterns, cannot follow up wiring patterns which are becoming finer as the technology develops.

[0012] Second, it is very difficult to fill grooves resulting between wirings of the same level, with insulating layer, and therefore cavities are inevitably created between the wirings. This is because of a poor step coverage of the insulating layer. Such cavities adversely affect the multilayer wiring technique.

[0013]FIGS. 3 and 4 show a semiconductor device manufactured by a dual damascening process. FIG. 4 is a cross sectional view taken along the line IV-IV indicated in FIG. 3.

[0014] As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.

[0015] On the semiconductor substrate 11, insulating layers 15 and 24 are formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layers 15 and 24 from its surface to be through to the source-drain region 13.

[0016] The insulating layer 25 is formed on the insulating layer 24. In the insulating layer 25, a plurality of grooves 16 b used for forming a first-level wiring layer, is formed. Bottom sections of the plurality of grooves 16 b are made through to the contact hole 16 a.

[0017] A barrier metal 17 a is formed on an inner surface of each of the contact hole 16 a and the grooves 16. Further, on each of the barrier metals 17 a, a metal (or metal alloy) portion 17 b is formed so as to completely fill each of the contact hole 16 a and the grooves 16 b The plurality of wirings which make the first level wiring layer, consist of the barrier metals 17 a and the metal portions 17 b.

[0018] The surface of the insulating layer 25 meets with that of the first-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the first-level wiring layer, is connected to the source-drain region 13 of the MOS transistor.

[0019] On the insulating layer 25 and the first level wiring layer, the insulating layer (interlayer dielectric) 18 and the insulating layer 26 are formed. A contact hole 19 a is formed in the insulating layers 18 and 26 from its surface to be through to the first-level wiring layer.

[0020] An insulating layer 27 is formed on the insulating film 26. A plurality of grooves 19 b used for forming the second-level wiring layer, are formed in the insulating layer 27. Bottom sections of the plurality of grooves 19 b are made through to the contact hole 19 a.

[0021] A barrier metal 20 a is formed on an inner surface of each of the contact hole 19 a and the grooves 19 b. Further, on each of the barrier metals 20 a, a metal (or metal alloy) portion 20 b is formed so as to completely fill each of the contact hole 19 a and the grooves 19 b. The plurality of wirings which make the second level wiring layer, consist of the barrier metals 20 a and the metal portions 20 b.

[0022] The surface of the insulating layer 27 meets with that of the second-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the second-level wiring layer, is connected to the first-level wiring layer.

[0023] In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad 21. The bonding pad 21 is made of a metal (or metal alloy), as in the case of the second-level wiring layer.

[0024] An insulating layer (passivation dielectric) 22 is formed on the insulation layer 27, the second-level wiring layer and the bonding pad 21. An opening 23 is made in the insulating layer 22 so as to expose the bonding pad 21.

[0025] Regarding the semiconductor device manufactured by the dual damascening process as described above, it is able to solve the drawbacks of the conventional wiring process, that is, the wiring pattern becoming out of focus when exposing, and the cavities resulting between wirings.

[0026] However, in the dual damascening process or damascening process, the chemical mechanical polishing (CMP) technique is employed. In the case where a bonding pad 21 is formed by the CMP technique, the central portion of the bonding pad 21 is excessively etched, resulting in dishing, that is, the bonding pad 21 is made into a dish-like shape.

[0027]FIG. 5 illustrates how dishing occurs.

[0028] More specifically, the CMP not only mechanically etch the metal layer 21′, but also chemically etch it. Therefore, in the case where the metal layer 21 (bonding pad) remains in a groove 19 b which has a width sufficiently large as compared to its depth (note that the size of a bonding pad is usually about 100 μm100 μm), the central portion of the metal layer 21 in the groove 19 b is excessively etched mainly by chemical etching.

[0029] Such dishing easily causes a bonding error, that is, a wire cannot be bonded to the bonding pad 21 accurately during a wiring bonding operation, which results in the deterioration of the production yield.

[0030]FIGS. 6 and 7 show a semiconductor device formed by the dual damascening process, which has been proposed to solve the problem of dishing. FIG. 7 is a cross sectional view taken along the line VII-VII indicated in FIG. 6.

[0031] As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.

[0032] On the semiconductor substrate 11, insulating layers 15 and 24 are formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layers 15 and 24 from its surface to be through to the source-drain region 13.

[0033] The insulating layer 25 is formed on the insulating layer 24. In the insulating layer 25, a plurality of grooves 16 b used for forming a first-level wiring layer, are formed. Bottom sections of the plurality of grooves 16 b are made through to the contact hole 16 a.

[0034] A barrier metal 17 a is formed on an inner surface of each of the contact hole 16 a and the grooves 16. Further, on each of the barrier metals 17 a, a metal (or metal alloy) portion 17 b is formed so as to completely fill each of the contact hole 16 a and the grooves 16 b. The plurality of wirings which make the first level wiring layer, consist of the barrier metals 17 a and the metal portions 17 b.

[0035] The surface of the insulating layer 25 meets with that of the first-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the first-level wiring layer, is connected to the source-drain region 13 of the MOS transistor.

[0036] On the insulating layer 25 and the first level wiring layer, the insulating layer (interlayer dielectric) 18 and the insulating layer 26 are formed. A contact hole 19 a is formed in the insulating layers 18 and 26 from its surface to be through to the first-level wiring layer.

[0037] An insulating layer 27 is formed on the insulating film 26. A plurality of grooves 19 b used for forming the second-level wiring layer, are formed in the insulating layer 27. Bottom sections of the plurality of grooves 19 b are made through to the contact hole 19 a.

[0038] A barrier metal 20 a is formed on an inner surface of each of the contact hole 19 a and the grooves 19 b. Further, on each of the barrier metals 20 a, a metal (or metal alloy) portion 20 b is formed so as to completely fill each of the contact hole 19 a and the grooves 19 b. The plurality of wirings which make the second level wiring layer, consist of the barrier metals 20 a and the metal portions 20 b.

[0039] The surface of the insulating layer 27 meets with that of the second-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the second-level wiring layer, is connected to the first-level wiring layer.

[0040] In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad 21. The bonding pad 21 is made of a metal (or metal alloy), as in the case of the second-level wiring layer.

[0041] However, in order to prevent the dishing which may occur during the CMP, the bonding pad 21 is formed to have a lattice-like shape. More specifically, in the bonding pad 21, a plurality of dot-like holes which are arranged in a matrix manner are made.

[0042] An insulating layer (passivation dielectric) 22 is formed on the insulation layer 27 and the second-level wiring layer. An opening 23 is made in the insulating layer 22 so as to expose the bonding pad 21.

[0043] In the semiconductor device manufactured by the dual damascening process, the bonding pad 21 is formed to have a lattice-like shape. Therefore, even in the case where the bonding pad 21 is formed by use of the CMP technique, the necessary portion is not excessively etched, thereby effectively preventing the dishing.

[0044] Next, the method of manufacturing a semiconductor device shown in FIGS. 6 and 7 will be described.

[0045] First, as can be seen in FIG. 8, with the LOCOS method, a field oxide layer 12 is formed on a silicon substrate 11. After that, in an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14 is formed.

[0046] Further, as an alternative, an insulating film (borophospho silicate glass (BPSG) or the like) 15 having a thickness of about 1 μm, which completely covers the MOS transistor, is formed on the silicon substrate 11. The surface of the insulating layer 15 is made flat by the CMP.

[0047] Next, as can be seen in FIG. 9, an etching stopper layer 24 and an insulating layer 25 are formed continuously on the insulating film 15 with the CVD method, for example. The insulating layer 25 is made of, for example, silicon oxide. In the case where the insulating layer 25 is made of silicon oxide, the etching stopper layer 24 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride.

[0048] The thickness of the etching stopper layer 24 is set to about 50 nm, and the thickness of the insulating film 25 is set to the same as that of the wirings which constitute the first-level wiring layer, that is, for example, about 0.6 μm.

[0049] Next, as can be seen in FIG. 10, a plurality of grooves 16 b are formed in the insulating layer 25. The plurality of grooves 16 b are formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 25, the patterning of the resist, the etching of the insulating layer 25 by RIE using the resist as a mask, and the removal of the resist. The etching stopper layer 24 serves as an etching stopper for the RIE.

[0050] It should be noted that the pattern of the plurality of grooves 16 b is made to match with the pattern of the wirings which constitute the first-level wiring layer.

[0051] Next, as can be seen in FIG. 11, a contact hole 16 a is made in the insulating layers 15 and 24. The contact hole 16 a is made also by the photo engraving process as in the formation of the plurality of grooves 16 b. More specifically, the contact hole 16 a is made by applying a resist on the insulating layer 25 and in the grooves 16 b, patterning the resist, etching the insulating layers 15 and 24 by the RIE using the resist as a mask, and removing the resist.

[0052] Then, as can be seen in FIG. 12, a barrier metal 17 a is formed on the insulating layer 25, on an inner surface of the contact hole 16 a and the inner surfaces of the grooves 16 b, by the CVD method or PVD method. The barrier metal 17 a is made of, for example, a lamination of titanium and titanium nitride, or silicon titanium nitride, or the like.

[0053] Next, as can be seen in FIG. 13, a metal (or metal alloy) portion 17′ which completely covers the contact hole 16 a and the grooves 16 b, is formed on the barrier metal 17 a by the CVD or PVD method. The metal portion 17′ is made of, for example, aluminum, copper or an alloy of these metals.

[0054] As the PVD method which is used to form the metal portion 17′, the high temperature PVD method or a PVD method including such a temperature process that can completely fill the contact holes 16 a and the grooves 16 b, is used.

[0055] Next, as can be seen in FIG. 14, the sections of the barrier metal 17 a and the metal portion 17 b, which are situated outside the contact holes 16 a and the grooves 16 b, are etched by the CMP method, so that the barrier metal 17 a and the metal portion 17 b remain only in the contact holes 16 a and the grooves 16 b.

[0056] In this manner, the first-level wiring layer is formed, and at the same time, a contact plug which serves to electrically connect the first-level wiring layer and the diffusion layer (source-drain region) of the substrate to each other, is formed.

[0057] Next, as can be seen in FIG. 15, an insulating layer (for example, silicon oxide) 18 having a thickness of about 1 μm, is formed on the insulating layer 25 and the first-level wiring layer by the CVD method. Further, an etching stopper layer 26 and an insulating layer 27 are formed to be continuous on the insulating film 18 with the CVD method, for example. The insulating layer 27 is made of, for example, silicon oxide. In the case where the insulating layer 27 is made of silicon oxide, the etching stopper layer 26 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride.

[0058] The thickness of the etching stopper layer 26 is set to about 50 nm, and the thickness of the insulating film 27 is set to the same as that of the wirings which constitute the second-level wiring layer, that is, for example, about 0.6 μm.

[0059] Next, as can be seen in FIGS. 16 and 17, a plurality of grooves 19 b and 19 b′ are formed in the insulating layer 25. The plurality of grooves 19 b and 19 b′ are formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 27, the patterning of the resist, the etching of the insulating layer 27 by RIE using the resist as a mask, and the removal of the resist. The etching stopper layer 26 serves as an etching stopper for the RIE.

[0060] It should be noted that the pattern of the plurality of grooves 19 b and 19 b′ is made to match with the pattern of the wirings which constitute the second-level wiring layer. The pattern of the grooves 19 b′ is the same as that of the bonding pad (lattice-like shape) (in the case where the second-level wiring layer is the uppermost layer).

[0061] Further, a contact hole 19 a is made in the insulating layers 18 and 26. The contact hole 19 a is made also by the photo engraving process as-in the formation of the plurality of grooves 19 b and 19 b′. More specifically, the contact hole 19 a is made by applying a resist on the insulating layer 27 and in the grooves 19 b and 19 b′, patterning the resist, etching the insulating layers 18 and 26 by the RIE using the resist as a mask, and removing the resist.

[0062] After that, as can be seen in FIGS. 18 and 19, a barrier metal 20 a is formed on the insulating layer 27, on an inner surface of the contact hole 19 a and the inner surfaces of the grooves 19 b and 19 b′, by the CVD method or PVD method. The barrier metal 20 a is made of, for example, a lamination of titanium and titanium nitride, or silicon titanium nitride, or the like.

[0063] Further, metal (or metal alloy) portions 20 b and 21 which completely cover the contact hole 19 a and the grooves 19 b and 19 b′, are formed on the barrier metal 20 a by the CVD or PVD method. The metal portions 20 b and 21 are made of, for example, aluminum, copper or an alloy of these metals.

[0064] As the PVD method which is used to form the metal portions 20 b and 21, the high temperature PVD method or a PVD method including such a temperature process that can completely fill the contact hole 19 a and the grooves 19 b and 19 b′, is used.

[0065] After that, the sections of the barrier metal 20 a and the metal portions 20 b and 21, which are situated outside the contact hole 19 a and the grooves 19 b and 19 b′, are etched by the CMP method, so that the barrier metal 20 a and the metal portions 20 b and 21 remain only in the contact hole 19 a and the grooves 19 b and 19 b′.

[0066] In this manner, the second-level wiring layer and the bonding pad having a lattice-like shape are formed, and at the same time, a contact plug which serves to electrically connect the first-level wiring layer and the second-level wiring layer to each other, is formed.

[0067] Next, as can be seen in FIG. 20, a passivation layer 22 is formed on the insulating layer 27, the second-level wiring layer and the bonding pad, by, for example, the CVD method. The passivation layer 22 is made of, for example, silicon oxide.

[0068] Next, as can be seen in FIGS. 21 and 22, an opening 23 is formed in the passivation layer 22. The opening 23 is situated so as to the lattice-shaped bonding pad 21, and is formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 22, the patterning of the resist, the etching of the insulating layer 22 by RIE using the resist as a mask, and the removal of the resist.

[0069] In the RIE operation for making the opening 23, usually the insulating layer 27 is etched as well since the insulating layers 22 and 27 are made of the same material (for example, silicon oxide).

[0070] The feature of the semiconductor device manufactured by the above-described dual damascening process or damascening process is that the metal portion itself which gives rise to wirings is not patterned, but the insulating layer is patterned. Since there is no process for filling the sections between wirings with the insulating layer, no cavities are formed between wirings.

[0071] Further, in some cases, copper, which has a low resistance, is used to form wirings; however it is known to be very difficult to perform a patterning on copper. In the dual damascening process or damascening process, the patterning of copper is not carried out, but the wirings are formed by filling grooves of an insulating layer with copper. Thus, the wirings made of copper are realized.

[0072] Further, in the dual damascening process, wirings and contact plugs can be formed at the same time, and therefore the production cost can be reduced.

[0073] However, in the dual damascening process, the RIE operated to make the opening 23 to expose the bonding pad 21, inevitably serves to etch the insulating layer 27 at the same time. This is because the insulating layers 22 and 27 are made of the same material (for example, silicon oxide) as described above.

[0074] In the above-described case, as shown in FIGS. 23 and 24, a wire bonding operation can easily result in that a wire 28 squash the lattice-shaped bonding pad 21, which may cause a bonding error. This is because portions of the lattice-like bonding pad 21 are cavities, which may easily cause the deformation of the bonding pad 21.

BRIEF SUMMARY OF THE INVENTION

[0075] The present invention has been proposed as a solution to the above-described drawback of the conventional technique, and the object thereof is as follows. That is, regarding the semiconductor device manufactured by the dual damascening process or damascening process, the bonding pad is formed to have a lattice shape, and the deformation of the lattice-shaped bonding pad is prevented so as to suppress bonding error, thereby improving the reliability and yield of the product.

[0076] In order to achieve the above-described object, there is provided, according to the present invention, a semiconductor device including: a bonding pad constituted by a conductive member filled in grooves made in an insulating layer having a flat surface; an etching stopper layer formed on the insulating layer and having an opening to expose the bonding pad; and a passivation layer formed on the etching stopper layer and having an opening to expose the bonding pad.

[0077] The grooves of the insulating layer are arranged in a lattice-like shape and the bonding pad has a lattice-like shape. The insulating layer and the passivation layer are made of silicon oxide, and the etching stopper layer is made of silicon nitride.

[0078] Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, in which a bonding pad is formed by making grooves in an insulating layer having a flat surface and filling the grooves with a conductive material, the method including the stops of: forming an etching stopper layer on the insulating layer and the bonding pad, the etching stopper layer being made of a material which can be etched selectively with respect to at least a material which is used to form the insulating layer; forming a passivation layer on the etching stopper layer, the passivation layer being made of a material which can be etched selectively with respect to at least the material used to form the etching stopper layer; removing only a portion of the passivation layer, which is situated above the bonding pad; and removing only a portion of the etching stopper layer, which is situated above the bonding pad.

[0079] The bonding pad is formed by forming a conductive material layer which completely covers the grooves on the insulating layer, followed by polishing the conductive material layer by the CMP. The passivation layer is etched by the RIE and the etching stopper layer is etched by the RIE or CDE.

[0080] As the grooves are filled with the conductive material, the bonding pad and the uppermost wiring layer are formed at the same time.

[0081] Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0082] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, servo to explain the principles of the invention.

[0083]FIG. 1 is a plan view showing a conventional semiconductor device;

[0084]FIG. 2 is a cross sectional view taken along the line II-II indicated in FIG. 1;

[0085]FIG. 3 is a plan view showing a conventional semiconductor device;

[0086]FIG. 4 is a cross sectional view taken along the line IV-IV indicated in FIG. 3;

[0087]FIG. 5 is a diagram showing a dishing phenomenon which may occur in conventional damascening process;

[0088]FIG. 6 is a plan view showing a conventional semiconductor device;

[0089]FIG. 7 is a cross sectional view taken along the line VII-VII indicated in FIG. 6;

[0090]FIG. 8 is a cross sectional view of a device, which illustrate a step of a conventional manufacturing method;

[0091]FIG. 9 is a cross sectional view of a device, which illustrate another step of the conventional manufacturing method;

[0092]FIG. 10 is a cross sectional view of a device, which illustrate still another step of the conventional manufacturing method;

[0093]FIG. 11 is a cross sectional view of a device, which illustrate still another step of the conventional manufacturing method;

[0094]FIG. 12 is a cross sectional view of a device, which illustrate still another step of the conventional manufacturing method;

[0095]FIG. 13 is a cross sectional view of a device, which illustrate still another step of the conventional manufacturing method;

[0096]FIG. 14 is a cross sectional view of a device, which illustrate still another step of the conventional manufacturing method;

[0097]FIG. 15 is a cross sectional view of a device, which illustrate still another step of the conventional manufacturing method;

[0098]FIG. 16 is a plan view of a device, which illustrates a step of the conventional manufacturing method;

[0099]FIG. 17 is a cross sectional view taken along the line XVII-XVII indicated in FIG. 16;

[0100]FIG. 18 is a plan view of a device, which illustrates a step of the conventional manufacturing method;

[0101]FIG. 19 is a cross sectional view taken along the line XIX-XIX indicated in FIG. 18;

[0102]FIG. 20 is a cross sectional view of a device, which illustrates a step of the conventional manufacturing method;

[0103]FIG. 21 is a plan view of a device, which illustrates a step of the conventional manufacturing method;

[0104]FIG. 22 is a cross sectional view taken along the line XXII-XXII indicated in FIG. 21;

[0105]FIG. 23 is a plan view which illustrates a state in which wire bonding is carried out on the device shown in FIG. 6;

[0106]FIG. 24 is a cross sectional view taken along the line XXIV-XXIV indicated in FIG. 23;

[0107]FIG. 25 is a plan view of a semiconductor device according to an embodiment of the present invention;

[0108]FIG. 26 is a cross sectional view taken along the line XXVI-XXVI indicated in FIG. 25;

[0109]FIG. 27 is a cross sectional view of a device, which illustrates a step of a manufacturing method according to an embodiment of the present invention;

[0110]FIG. 28 is a cross sectional view of a device, which illustrates another step of a manufacturing method according to the embodiment of the present invention;

[0111]FIG. 29 is a cross sectional view of a device, which illustrates still another step of a manufacturing method according to the embodiment of the present invention;

[0112]FIG. 30 is a cross sectional view of a device, which illustrates still another step of a manufacturing method according to the embodiment of the present invention;

[0113]FIG. 31 is a cross sectional view of a device, which illustrates still another step of a manufacturing method according to the embodiment of the present invention;

[0114]FIG. 32 is a cross sectional view of a device, which illustrates still another step of a manufacturing method according to the embodiment of the present invention;

[0115]FIG. 33 is a cross sectional view of a device, which illustrates still another step of a manufacturing method according to the embodiment of the present invention;

[0116]FIG. 34 is a cross sectional view of a device, which illustrates still another step of a manufacturing method according to the embodiment of the present invention;

[0117]FIG. 35 is a plan view of a device, which illustrates a step of a manufacturing method according to an embodiment of the present invention;

[0118]FIG. 36 is a cross sectional view taken along the line XXXVI-XXXVI indicated in FIG. 35;

[0119]FIG. 37 is a plan view of a device, which illustrates a step of a manufacturing method according to an embodiment of the present invention;

[0120]FIG. 38 is a cross sectional view taken along the line XXXVIII-XXXVIII indicated in FIG. 37;

[0121]FIG. 39 is a cross sectional view of a device, which illustrates a step of a manufacturing method according to an embodiment of the present invention;

[0122]FIG. 40 is a plan view of a device, which illustrates a step of a manufacturing method according to the embodiment of the present invention;

[0123]FIG. 41 is a cross sectional view taken along the line XLI-XLI indicated in FIG. 40;

[0124]FIG. 42 is a plan view of a device, which illustrates a step of a manufacturing method according to an embodiment of the present invention;

[0125]FIG. 43 is a cross sectional view taken along the line XLIII-XLIII indicated in FIG. 42;

[0126]FIG. 44 is a plan view which illustrates a state in which wire bonding is carried out on the device shown in FIG. 25; and

[0127]FIG. 45 is a cross sectional view taken along the line XLV-XLV indicated in FIG. 44.

DETAILED DESCRIPTION OF THE INVENTION

[0128] Semiconductor devices of the present invention and methods of manufacturing the same will now be described in detail with reference to embodiments thereof shown in accompanying drawings.

[0129]FIGS. 25 and 26 show a semiconductor device formed by the dual damascening process according to an embodiment of the present invention. FIG. 26 is a cross sectional view taken along the line XXVI-XXVI indicated in FIG. 25.

[0130] As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.

[0131] On the semiconductor substrate 11, insulating layers 15 and 24 are formed so as to completely cover the MOS transistor. A contact hole 16 a is made in the insulating layers 15 and 24 from its surface to be through to the source-drain region 13.

[0132] The insulating layer 25 is formed on the insulating layer 24. In the insulating layer 25, a plurality of grooves 16 b used for forming a first-level wiring layer, are formed. Bottom sections of the plurality of grooves 16 b are made through to the contact hole 16 a.

[0133] A barrier metal 17 a is formed on an inner surface of each of the contact hole 16 a and the grooves 16. Further, on each of the barrier metals 17 a, a metal (or metal alloy) portion 17 b is formed so as to completely fill each of the contact hole 16 a and the grooves 16 b. The plurality of wirings which make the first level wiring layer, consist of the barrier metals 17 a and the metal portions 17 b.

[0134] A contact plug used for connecting the first level wiring layer and the source-drain region 13 of the MOS transistor to each other, also consists of the barrier metal 17 a and the metal portion 17 b. The surface of the insulating layer 25 meets with that of the first-level wiring layer, and the surface is made flat.

[0135] On the insulating layer 25 and the first level wiring layer, the insulating layer (interlayer dielectric) 18 and the insulating layer 26 are formed. A contact hole 19 a is formed in the insulating layers 18 and 26 from its surface to be through to the first-level wiring layer.

[0136] An insulating layer 27 is formed on the insulating film 26. A plurality of grooves 19 b used for forming the second-level wiring layer, are formed in the insulating layer 27. Bottom sections of the plurality of grooves 19 b are made through to the contact hole 19 a.

[0137] A barrier metal 20 a is formed on an inner surface of each of the contact hole 19 a and the grooves 19 b. Further, on each of the barrier metals 20 a, a metal (or metal alloy) portion 20 b is formed so as to completely fill each of the contact hole 19 a and the grooves 19 b. The plurality of wirings which make the second level wiring layer, consist of the barrier metals 20 a and the metal portions 20 b.

[0138] A contact plug used for connecting the first-level wiring layer and the second-level wiring layer to each other, also consists of the barrier metal 20 a and the metal portion 20 b. The surface of the insulating layer 27 meets with that of the second-level wiring layer, and the surface is made flat.

[0139] In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad 21. The bonding pad 21 is made of a metal (or metal alloy), as in the case of the second-level wiring layer. However, in order to prevent the dishing which may occur during the CMP, the bonding pad 21 is formed to have, for example, a lattice-like shape.

[0140] Further, an etching stopper layer 29 is formed on the insulating layer 27 and the second-level wiring layer, and a passivation layer (passivation dielectric) 22 is formed on the etching stopper layer 29.

[0141] The etching stopper layer 29 is made of a material which can be etched selectively with respect to the material used for the insulating layer 27 and the passivation layer 22. For example, in the case where the insulating layer 27 and the passivation layer 22 are made of silicon oxide, the etching stopper layer 29 is made of silicon nitride. The etching stopper layer 29 is formed to have a thickness of about 50 nm.

[0142] An opening 23 is made in the passivation layer 22 and the etching stopper layer 29 so as to expose the bonding pad 21.

[0143] In the semiconductor device manufactured by the dual damascening process, the bonding pad 21 is formed to have a lattice-like shape. Therefore, even in the case where the bonding pad 21 is formed by use of the CMP technique, the necessary portion thereof is not excessively etched, thereby effectively preventing the dishing.

[0144] Further, the bonding pad 21 having a lattice shape is completely filled with the insulating layer 27. With this structure, the bonding pad 21 is not squashed or deformed when the wire is bonded thereto by compression by wire bonding. Therefore, the occurrence of bonding errors is suppressed, thus contributing the improvement of the reliability and the yield of the product.

[0145] Furthermore, directly underneath the passivation layer 22, the etching stopper layer 29 is located, which is made of a material which can be etched selectively with respect to the material used for forming the passivation layer 22 and the insulating layer 27. With this structure, the portions of the insulating layer 27, which are situated in the lattice-like formations of the bonding pad 21, are not etched when the opening 23 is made in the passivation layer 22.

[0146] Next, the method of manufacturing a semiconductor device shown in FIGS. 25 and 26 will be described.

[0147] First, as can be seen in FIG. 27, with the LOCOS method, a field oxide layer 12 is formed on a silicon substrate 11. After that, in an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14 is formed.

[0148] Further, as an alternative, an insulating film (borophospho silicate glass (BPSG) or the like) 15 having a thickness of about 1 μm, which completely covers the MOS transistor, is formed on the silicon substrate 11. The surface of the insulating layer 15 is made flat by the CMP.

[0149] Next, as can be seen in FIG. 28, an etching stopper layer 24 and an insulating layer 25 are formed continuously on the insulating film 15 with the CVD method, for example. The insulating layer 25 is made of, for example, silicon oxide. In the case where the insulating layer 25 is made of silicon oxide, the etching stopper layer 24 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride.

[0150] The thickness of the etching stopper layer 24 is set to about 50 nm, and the thickness of the insulating film 25 is set to the same as that of the wirings which constitute the first-level wiring layer, that is, for example, about 0.6 μm.

[0151] Next, as can be seen in FIG. 29, a plurality of grooves 16 b are formed in the insulating layer 25. The plurality of grooves 16 b are formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 25, the patterning of the resist, the etching of the insulating layer 25 by RIE using the resist as a mask, and the removal of the resist. The etching stopper layer 24 serves as an etching stopper for the RIE.

[0152] It should be noted that the pattern of the plurality of grooves 16 b is made to match with the pattern of the wirings which constitute the first-level wiring layer.

[0153] Next, as can be seen in FIG. 30, a contact hole 16 a is made in the insulating layers 15 and 24. The contact hole 16 a is made also by the photo engraving process as in the formation of the plurality of grooves 16 b. More specifically, the contact hole 16 a is made by applying a resist on the insulating layer 25 and in the grooves 16 b, patterning the resist, etching the insulating layers 15 and 24 by the RIE using the resist as a mask, and removing the resist.

[0154] Then, as can be seen in FIG. 31, a barrier metal 17 a is formed on the insulating layer 25, on an inner surface of the contact hole 16 a and the inner surfaces of the grooves 16 b, by the CVD method or PVD method. The barrier metal 17 a is made of, for examples a lamination of titanium and titanium nitride, or silicon titanium nitride, or the like.

[0155] Next, as can be seen in FIG. 32, a metal (or metal alloy) portion 17′ which completely covers the contact hole 16 a and the grooves 16 b, is formed on the barrier metal 17 a by the CVD or PVD method. The metal portion 17′ is made of, for example, aluminum, copper or an alloy of these metals.

[0156] As the PVD method which is used to form the metal portion 17′, the high temperature PVD method or a PVD method including such a temperature process that can completely fill the contact holes 16 a and the grooves 16 b, is used.

[0157] Next, as can be seen in FIG. 33, the sections of the barrier metal 17 a and the metal portion 17 b, which are situated outside the contact holes 16 a and the grooves 16 b, are etched by the CMP method, so that the barrier metal 17 a and the metal portion 17 b remain only in the contact holes 16 a and the grooves 16 b.

[0158] In this manner, the first-level wiring layer is formed, and at the same time, a contact plug which serves to electrically connect the first-level wiring layer and the diffusion layer (source-drain region) of the substrate to each other, is formed.

[0159] Next, as can be seen in FIG. 34, an insulating layer (for example, silicon oxide) 18 having a thickness of about 1 μm, is formed on the insulating layer 25 and the first-level wiring layer by the CVD method. Further, an etching stopper layer 26 and an insulating layer 27 are formed to be continuous on the insulating film 18 with the CVD method, for example. The insulating layer 27 is made of, for example, silicon oxide. In the case where the insulating layer 27 is made of silicon oxide, the etching stopper layer 26 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride.

[0160] The thickness of the etching stopper layer 26 is set to about 50 nm, and the thickness of the insulating film 27 is set to the same as that of the wirings which constitute the second-level wiring layer.

[0161] Next, as can be seen in FIGS. 35 and 36, a plurality of grooves 19 b and 19 b′ are formed in the insulating layer 25. The plurality of grooves 19 b and 19 b′ are formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 27, the patterning of the resist, the etching of the insulating layer 27 by RIE using the resist as a mask, and the removal of the resist. The etching stopper layer 26 serves as an etching stopper for the RIE.

[0162] It should be noted that the pattern of the plurality of grooves 19 b and 19 b′ is made to match with the pattern of the wirings which constitute the second-level wiring layer. The pattern of the grooves 19 b′ is the same as that of the bonding pad (lattice-like shape) (in the case where the second-level wiring layer is the uppermost layer).

[0163] Next, as can be seen in FIGS. 37 and 38, a contact hole 19 a is made in the insulating layers 18 and 26. The contact hole 16 a is made also by the photo engraving process as in the formation of the plurality of grooves 19 b and 19 b′. More specifically, the contact hole 19 a is made by applying a resist on the insulating layer 27 and in the grooves 19 b and 19 b′, patterning the resist, etching the insulating layers 18 and 26 by the RIE using the resist as a mask, and removing the resist.

[0164] After that, a barrier metal 20 a is formed on the insulating layer 27, on an inner surface of the contact hole 19 a and the inner surfaces of the grooves 19 b and 19 b′, by the CVD method or PVD method. The barrier metal 20 a is made of, for example, a lamination of titanium and titanium nitride, or silicon titanium nitride, or the like.

[0165] Next, metal (or metal alloy) portions 20 b and 21 which completely cover the contact hole 19 a and the grooves 19 b and 19 b′, are formed on the barrier metal 20 a by the CVD or PVD method. The metal portions 20 b and 21 are made of, for example, aluminum, copper or an alloy of these metals.

[0166] As the PVD method which is used to form the metal portions 20 b and 21, the high temperature PVD method or a PVD method including such a temperature process that can completely fill the contact hole 16 a and the grooves 19 b and 19 b′, is used.

[0167] Next, the sections of the barrier metal 20 a and the metal portions 20 b and 21, which are situated outside the contact hole 19 a and the grooves 19 b and 19 b′, are etched by the CMP method, so that the barrier metal 20 a and the metal portions 20 b and 21 remain only in the contact hole 19 a and the grooves 19 b and 19 b′.

[0168] In this manner, the second-level wiring layer and the bonding pad having a lattice-like shape are formed, and at the same time, a contact plug which serves to electrically connect the first-level wiring layer and the second-level wiring layer to each other, is formed.

[0169] Next, as can be seen in FIG. 39, an etching stopper layer 29 and a passivation layer 22 are formed to be continuous, on the insulating layer 27, the second-level wiring layer and the bonding pad, by, for example, the CVD method.

[0170] The passivation layer 22 is made of, for example, silicon oxide. In the case where the passivation layer 22 is made of silicon oxide, the etching stopper layer 29 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride. The thickness of the etching stopper layer 29 is set to about 50 nm.

[0171] Next, as can be seen in FIGS. 40 and 41, an opening 23 is formed in the passivation layer 22. The opening 23 is situated so as to the lattice-shaped bonding pad 21, and is formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 22, the patterning of the resist, the etching of the insulating layer 22 by RIE using the resist as a mask, and the removal of the resist.

[0172] In the RIE operation for making the opening 23, the insulating layer 27 is not etched in the presence of the insulating layer 27.

[0173] Then, as can be seen in FIGS. 42 and 43, only the etching stopper layer 29 remaining in the bottom of the opening 23 of the passivation layer 22 is removed. The removal of the etching stopper layer 29 can be achieved by anisotropic etching such as RIE, or isotropic etching such as chemical dry etching (CDE).

[0174] As described above, the semiconductor device shown in FIGS. 25 and 26 is completed.

[0175] The feature of the above-described method is that the etching stopper layer 29 is provided directly underneath the passivation layer 22. With this structure, in the RIE operation carried out to made the opening 23 in the bonding pad 21, the sections of the insulating layer 27 formed in the lattice-like pattern of the bonding pad 21 are not etched.

[0176] More specifically, as can be seen in FIGS. 44 and 45, the recessed pattern of the lattice-shaped bonding pad 21 is filled with the insulating layer 27. With this structure, even if the wire bonding is carried out, the wire 28 does not squash or deform the lattice-shaped bonding pad 21.

[0177] Therefore, the bonding error can be avoided, thereby making it possible to improve the reliability and yield of the product.

[0178] As described above, with the semiconductor device and the method of manufacturing such a device, according to the present invention, the following effect can be obtained.

[0179] That is, directly underneath the passivation layer, an etching stopper layer is provided. Therefore, in the RIE operation for making an opening to expose the bonding pad, the portions of the insulating layer, which are situated at the recessed portions of the lattice shape, are not etched. Consequently, each section between adjacent recessed portions is filled with the insulation layer. With this structure, if a wire bonding is carried out, the wire cannot squash or deform the bonding pad having a lattice-like shape. Thus, the bonding error can be prevented, thereby making it possible to improve the reliability and yield of the product.

[0180] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6873053 *Feb 14, 2002Mar 29, 2005Sanyo Electric Co., Ltd.Semiconductor device with smoothed pad portion
US7358185 *Sep 23, 2005Apr 15, 2008Micron Technology, Inc.Device having contact pad with a conductive layer and a conductive passivation layer
US7692315Feb 11, 2005Apr 6, 2010Fujitsu Microelectronics LimitedSemiconductor device and method for manufacturing the same
US7785947 *Apr 25, 2006Aug 31, 2010Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing semiconductor device comprising the step of forming nitride/oxide by high-density plasma
US7919864 *Mar 2, 2004Apr 5, 2011Stmicroelectronics S.A.Forming of the last metallization level of an integrated circuit
US7935979 *Sep 19, 2008May 3, 2011Bridgelux, Inc.Wire bonding to connect electrodes
US8034703Dec 18, 2009Oct 11, 2011Fujitsu Semiconductor LimitedSemiconductor device and method for manufacturing the same
US8089162Aug 10, 2009Jan 3, 2012Fujitsu Semiconductor LimitedSemiconductor device and method for manufacturing the same
US8736067Jul 27, 2011May 27, 2014Panasonic CorporationSemiconductor device having a pad
Legal Events
DateCodeEventDescription
May 13, 2014FPExpired due to failure to pay maintenance fee
Effective date: 20140326
Mar 26, 2014LAPSLapse for failure to pay maintenance fees
Nov 1, 2013REMIMaintenance fee reminder mailed
Aug 26, 2009FPAYFee payment
Year of fee payment: 8
Sep 2, 2005FPAYFee payment
Year of fee payment: 4
Aug 20, 1997ASAssignment
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANAND, MINAKSHISUNDARAN BALASUBRAMANIAN;REEL/FRAME:008755/0055
Effective date: 19970813