Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010014499 A1
Publication typeApplication
Application numberUS 09/816,525
Publication dateAug 16, 2001
Filing dateMar 23, 2001
Priority dateDec 11, 1996
Also published asUS6150211, US6222215, US6358812, US6399981
Publication number09816525, 816525, US 2001/0014499 A1, US 2001/014499 A1, US 20010014499 A1, US 20010014499A1, US 2001014499 A1, US 2001014499A1, US-A1-20010014499, US-A1-2001014499, US2001/0014499A1, US2001/014499A1, US20010014499 A1, US20010014499A1, US2001014499 A1, US2001014499A1
InventorsJohn Zahurak
Original AssigneeZahurak John K.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry
US 20010014499 A1
Abstract
Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one aspect of the invention, a first insulating layer is formed over a semiconductive material layer. A conductive gate is formed over the semiconductive material layer. A second insulating layer is formed over the gate and thereafter etched to form a capacitor container. In one implementation, such etch is conducted to outwardly expose the semiconductive material layer. In another implementation, such etch continues into the semiconductive material layer. In yet another implementation, such etch is conducted completely through the semiconductive material layer and into the first insulating layer. In a preferred implementation, a storage capacitor is formed within the capacitor container which extends both elevationally above and elevationally below the gate. According to another aspect of the invention, adjacent word lines are formed over the first insulating layer and source/drain diffusion regions are formed within the semiconductive material laterally outward of the word lines. Respective capacitor containers are etched into the diffusion regions and capacitors are formed within the etched containers. In a preferred implementation, storage node material which constitutes part of the capacitors is in electrical contact with the respective diffusion regions and comprises part of a DRAM memory cell.
Images(11)
Previous page
Next page
Claims(51)
1. A method of forming a capacitor comprising:
forming a semiconductive material layer over a first insulating layer;
forming a conductive gate over the semiconductive material layer;
forming a second insulating layer over the gate;
etching a capacitor opening into the second insulating layer laterally adjacent the gate and into the semiconductive material layer; and
forming a capacitor within the capacitor opening.
2. The method of forming a capacitor of
claim 1
, wherein the etching comprises etching entirely through the semiconductive material layer and into the first insulating layer, and the forming of the capacitor comprises forming the capacitor at least partially within the first insulative layer.
3. The method of forming a capacitor of
claim 1
, comprising forming the capacitor opening and the capacitor to extend both elevationally above and elevationally below the gate.
4. The method of forming a capacitor of
claim 1
further comprising prior to the etching of the second insulating layer, forming a masking layer comprising polysilicon atop the second insulating layer at least a portion of which is etched during the etching.
5. The method of forming a capacitor of
claim 1
further comprising:
after the forming of the conductive gate, forming a source/drain diffusion region within the semiconductive material layer, the diffusion region extending through the semiconductive material layer and contacting the underlying first insulating layer; and
wherein the etching comprises etching a) entirely through the semiconductive material layer, b) entirely through at least a portion of the source/drain diffusion region, and c) into the underlying first insulating layer.
6. The method of forming a capacitor of
claim 1
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising rugged polysilicon within at least a portion of the capacitor opening.
7. The method of forming a capacitor of
claim 1
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising selective hemispherical grain polysilicon within at least a portion of the capacitor opening.
8. The method of forming a capacitor of
claim 1
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising cylindrical grain polysilicon within at least a portion of the capacitor opening.
9. The method of forming a capacitor of
claim 1
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising hemispherical grain polysilicon within at least a portion of the capacitor opening.
10. A method of forming a capacitor comprising:
forming a semiconductive material layer over an insulating layer;
forming a gate over the semiconductive material layer;
removing a portion of the insulating layer elevationally below the gate which is laterally displaced from the gate to form at least a portion of a capacitor opening;
forming a capacitor within the capacitor opening; and
forming a conductive diffusion region within the semiconductive material layer in electrical connection with the capacitor.
11. The method of forming a capacitor of
claim 10
further comprising after the forming of the gate, forming a second insulating layer over the gate and removing a portion of the second insulating layer to form at least a portion of the capacitor opening.
12. The method of forming a capacitor of
claim 10
, wherein the forming of the capacitor comprises forming rugged polysilicon within the capacitor opening.
13. The method of forming a capacitor of
claim 10
, wherein the forming of the capacitor comprises forming cylindrical grain polysilicon within the capacitor opening.
14. The method of forming a capacitor of
claim 10
, wherein the forming of the capacitor comprises forming hemispherical grain polysilicon within the capacitor opening.
15. The method of forming a capacitor of
claim 10
, wherein the forming of the capacitor comprises forming selective hemispherical grain polysilicon within the capacitor opening.
16. The method of forming a capacitor of
claim 10
, wherein:
the forming of the conductive diffusion region takes place prior to the capacitor opening being formed; and
the removing of the portion of the insulating layer comprises etching through overlying semiconductive material and through at least a portion of the conductive diffusion region.
17. A method of forming a capacitor comprising:
forming a semiconductive material layer over an insulating layer;
forming a gate over the semiconductive material layer;
forming a source/drain diffusion region within the semiconductive material layer and operatively associated with the gate;
etching a capacitor opening into the diffusion region of the semiconductive material layer; and
forming a capacitor within the capacitor opening.
18. The method of forming a capacitor of
claim 17
, wherein the forming of the capacitor comprises forming conductive material within the capacitor opening laterally adjacent and in electrical contact with the diffusion region.
19. The method of forming a capacitor of
claim 17
, wherein the forming of the capacitor comprises forming conductively doped polysilicon material within the capacitor opening laterally adjacent and in electrical contact with the diffusion region, and further comprising outdiffusing conductivity enhancing impurity from the polysilicon material into the diffusion region.
20. The method of forming a capacitor of
claim 17
, wherein the etching of the capacitor opening comprises etching completely through the semiconductive material layer.
21. The method of forming a capacitor of
claim 17
, wherein the etching of the capacitor opening comprises etching completely through the semiconductive material layer and into the insulating layer.
22. The method of forming a capacitor of
claim 17
, wherein the forming of the source/drain diffusion region comprises forming the diffusion region to extend elevationally completely through the semiconductive material and connect with the insulating layer.
23. The method of forming a capacitor of
claim 17
, wherein:
the forming of the source/drain diffusion region comprises forming the diffusion region to extend elevationally completely through the semiconductive material and connect with the insulating layer; and
the etching of the capacitor opening comprises etching into the insulating layer.
24. The method of forming a capacitor of
claim 17
further comprising forming a second insulating layer over the gate, and
wherein the etching of the capacitor opening comprises etching portions of the second insulating layer.
25. A method of forming a capacitor comprising:
forming a semiconductive material layer over an insulating layer;
forming an electrically conductive diffusion region within the semiconductive material layer;
etching a capacitor opening into the diffusion region of the semiconductive material layer; and
forming a capacitor within the capacitor opening.
26. The method of forming a capacitor of
claim 25
, wherein the forming of the electrically conductive diffusion region comprises forming the diffusion region to extend completely through the semiconductive material layer and connect with the insulating layer.
27. The method of forming a capacitor of
claim 25
, wherein prior to the forming of the electrically conductive diffusion region:
forming two laterally spaced apart transistor gates over the insulating layer;
the forming of the electrically conductive diffusion region comprising forming at least two electrically conductive diffusion regions, individual transistor gates being operably associated with individual diffusion regions; and
the etching of the capacitor opening comprising etching into two of the individual diffusion regions with which the individual transistor gates are operably associated to form a pair of capacitor openings.
28. The method of forming a capacitor of
claim 25
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising rugged polysilicon within the capacitor opening.
29. The method of forming a capacitor of
claim 25
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising cylindrical grain polysilicon within the capacitor opening.
30. The method of forming a capacitor of
claim 25
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising hemispherical grain polysilicon within the capacitor opening.
31. The method of forming a capacitor of
claim 25
, wherein the forming of the capacitor comprises forming a capacitor storage node layer comprising selective hemispherical grain polysilicon within the capacitor opening.
32. A method of forming DRAM cells comprising:
forming a semiconductive material layer over a first insulating layer;
forming two adjacent word lines over the first insulating layer;
forming a first source/drain diffusion region within the semiconductive material layer between the two word lines and second and third source/drain diffusion regions within the semiconductive material layer laterally outward of the two word lines;
etching respective capacitor openings into the second and third source/drain diffusion regions;
forming capacitors within the respective capacitor openings; and
forming a bit line in ohmic electrical connection with the first source/drain diffusion region.
33. The method of forming DRAM cells of
claim 32
, wherein the forming of the first, second and third source/drain diffusion regions comprises forming the regions to extend completely through the semiconductive material layer.
34. The method of forming DRAM cells of
claim 32
, wherein the etching of the respective capacitor openings comprises etching completely through the semiconductive material layer to expose portions of the first insulating layer.
35. The method of forming DRAM cells of
claim 32
, wherein the etching of the respective capacitor openings comprises etching completely through the semiconductive material layer and into the first insulating material.
36. The method of forming DRAM cells of
claim 32
further comprising:
forming a second insulating layer over the word lines and the diffusion regions; and
the etching of the respective capacitor openings comprises etching through portions of the second insulating layer.
37. The method of forming DRAM cells of
claim 32
further comprising:
forming a second insulating layer over the word lines and the diffusion regions; and
the etching of the respective capacitor openings comprises etching a) through portions of the second insulating layer, and b) completely through the semiconductive material layer to expose portions of the first insulating layer.
38. The method of forming DRAM cells of
claim 32
further comprising:
forming a second insulating layer over the word lines and the diffusion regions; and
the etching of the respective capacitor openings comprises etching a) through portions of the second insulating layer, and b) completely through the semiconductive material layer and into the first insulating material.
39. A method of forming a memory cell comprising:
forming a gate over semiconductive material;
forming a capacitor storage node laterally adjacent the gate which extends both into and above the semiconductive material; and
forming a pair of source/drain diffusion regions within the semiconductive material which are operatively associated with the gate, with one region of said pair being in electrical connection with the storage node.
40. The method of forming a memory cell of
claim 39
, wherein the forming of the capacitor storage node comprises:
forming an insulating material layer over the gate;
etching a capacitor opening into the insulating material layer and into the semiconductive material; and
forming a storage node material layer within the capacitor opening.
41. The method of forming a memory cell of
claim 39
, wherein the forming of the capacitor storage node comprises:
forming an insulating material layer over the gate;
etching a capacitor opening into the insulating material layer and into the semiconductive material; and
forming a storage node material layer comprising rugged polysilicon within the capacitor opening.
42. The method of forming a memory cell of
claim 39
, wherein the forming of the capacitor storage node comprises:
forming an insulating material layer over the gate;
etching a capacitor opening into the insulating material layer and into the semiconductive material; and
forming a storage node material layer comprising cylindrical grain polysilicon within the capacitor opening.
43. The method of forming a memory cell of
claim 39
, wherein the forming of the capacitor storage node comprises:
forming an insulating material layer over the gate;
etching a capacitor opening into the insulating material layer and into the semiconductive material; and
forming a storage node material layer comprising hemispherical grain polysilicon within the capacitor opening.
44. The method of forming a memory cell of
claim 39
, wherein the forming of the capacitor storage node comprises:
forming an insulating material layer over the gate;
etching a capacitor opening into the insulating material layer and into the semiconductive material; and
forming a storage node material layer comprising selective hemispherical grain polysilicon within the capacitor opening.
45. The method of forming a memory cell of
claim 39
, wherein the forming of the capacitor storage node comprises:
forming an insulating layer over the gate and laterally adjacent semiconductive material;
forming a masking material layer comprising polysilicon over the insulating layer;
selectively removing masking material to define a capacitor mask opening;
etching the insulating layer through the capacitor mask opening using the masking material layer as an etch mask to form a capacitor opening; and
forming a conductive storage node material layer within the capacitor opening.
46. A method of forming DRAM cells comprising:
forming a first insulating layer over a silicon-containing substrate, the first insulating layer having an elevational thickness from about 1000 to 20,000 Angstroms;
forming a semiconductive material layer over the first insulating layer, the semiconductive material layer having an elevational thickness from about 200 to 10,000 Angstroms;
forming two adjacent word lines over the first insulating layer;
forming a first source/drain diffusion region within the semiconductive material layer between the two word lines and second and third source/drain diffusion regions within the semiconductive material layer laterally outward of the two word lines, the diffusion regions extending through the semiconductive material and connecting with the first insulating layer;
forming a second insulating layer over the word lines and the semiconductive material layer;
forming a masking layer comprising polysilicon over the second insulating layer;
patterning and etching the masking layer to define masking layer openings through which capacitor openings are to be etched;
forming a layer comprising polysilicon over the masking layer and within the masking layer openings;
removing at least some of the polysilicon layer within the masking layer openings to outwardly expose portions of the second insulating layer, the removing serving to narrow the masking layer openings through which the capacitor openings are to be etched;
etching capacitor openings a) through the exposed portions of the second insulating layer, b) through underlying portions of the semiconductive material, and c) at least into the first insulating layer, the etching through the underlying portions of the semiconductive material etching into and through portions of the second and third source/drain diffusion regions;
forming a layer of capacitor storage node material within individual capacitor openings, node material in the individual openings being in electrical contact with respective second and third source/drain diffusion regions;
planarizing the capacitor storage node material to isolate node material within the capacitor openings;
forming capacitor dielectric material over the storage node material with the capacitor openings;
forming a cell plate structure at least within the capacitor openings and in operative association with the dielectric material; and
forming a bit line in ohmic electrical connection with the first source/drain diffusion region.
47. An integrated circuitry memory device comprising:
a substrate comprising semiconductive material;
a transistor gate disposed over the semiconductive material;
a pair of diffusion regions received within the semiconductive material and operably associated with the transistor gate; and
a capacitor storage node received within the semiconductive material and supported by the substrate laterally adjacent the transistor gate, the storage node electrically connecting with one region of said pair of diffusion regions.
48. The integrated circuitry memory device of
claim 47
, wherein:
the substrate comprises a pair of insulating layers, one of said pair of insulating layers being disposed elevationally below the semiconductive material, another of said pair being disposed elevationally above the semiconductive material; and
wherein the capacitor storage node is received within the insulating layer which is elevationally below the semiconductive material.
49. The integrated circuitry memory device of
claim 47
, wherein:
the substrate comprises a pair of insulating layers, one of said pair of insulating layers being disposed elevationally below the semiconductive material, another of said pair being disposed elevationally above the semiconductive material; and
wherein the capacitor storage node is received within the insulating layer which is elevationally above the semiconductive material.
50. The integrated circuitry memory device of
claim 47
, wherein:
the substrate comprises a pair of insulating layers, one of said pair of insulating layers being disposed elevationally below the semiconductive material, another of said pair being disposed elevationally above the semiconductive material; and
wherein the capacitor storage node is received within both of the insulating layers.
51. Dynamic random access memory circuitry comprising:
a semiconductive substrate;
a first insulating layer disposed over the semiconductive substrate and having an elevational thickness from about 1000 to 20,000 Angstroms;
a semiconductive material layer disposed over the first insulating layer and having an elevational thickness from about 200 to 10,000 Angstroms;
a pair of laterally spaced apart word lines disposed over the semiconductive material layer;
a first source/drain diffusion region received within the semiconductive material layer generally between the word lines, the first source/drain diffusion region extending completely through the semiconductive material layer and connecting with the first insulating layer;
second and third source/drain diffusion regions received within the semiconductive material layer and disposed respectively generally laterally outward of the two word lines, the second and third source/drain diffusion regions extending completely through the semiconductive material and connecting with the first insulating layer;
a second insulating layer disposed over the word lines and the semiconductive material layer;
a pair of capacitor openings received within the second insulating layer and extending elevationally downward therefrom a) through the second insulating layer, b) completely through the semiconductive material layer and associated second and third source/drain diffusion regions therein, and c) into the first insulating layer;
a layer of storage node material disposed within individual capacitor openings and in electrical contact with respective second and third source/drain diffusion regions;
a capacitor dielectric layer disposed over the storage node material;
cell plate structure operatively disposed relative to the capacitor dielectric layer, the storage node material, capacitor dielectric layer and cell plate structure constituting respective capacitor constructions which extend both elevationally above and elevationally below the word lines; and
a bit line disposed laterally between at least a portion of the individual capacitor constructions and in ohmic electrical contact with the first source/drain diffusion region.
Description
    TECHNICAL FIELD
  • [0001]
    This invention relates to methods of forming storage capacitors in integrated circuitry memory cells and related integrated circuitry.
  • BACKGROUND OF THE INVENTION
  • [0002]
    As integrated circuitry memory cells become increasingly smaller, it becomes more difficult to realize desired memory cells which have enough cell capacitance to store information for a reasonable amount of time. The industry has approached the challenge of providing cell capacitance from two different directions.
  • [0003]
    According to a first direction, storage capacitors are fabricated over a semiconductor wafer. Such capacitors, known as container capacitors, are typically formed by etching into an insulating layer which is formed over a wafer outer surface. One disadvantage of this approach is that as the memory cells continue to decrease in size, the capacitors have to become narrower and taller in construction in order to maintain a desirable capacitance. Accordingly, the topology of the wafer becomes worse from the standpoint of its impact on several processing steps such as lithography, etching, and mechanical substrate abrading such as chemical mechanical polishing.
  • [0004]
    According to a second direction, trenches are etched into a substrate and capacitors are formed within the trenches. Such capacitors are known as trench capacitors. A major disadvantage of this approach is that very deep, high aspect ratio trenches must be etched into the substrate. Additionally, complicated strapping mechanisms must be employed to ground the cell.
  • [0005]
    This invention grew out of concerns associated with increasing cell capacitance while reducing topography and strapping requirements.
  • SUMMARY OF THE INVENTION
  • [0006]
    Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one aspect of the invention, a first insulating layer is formed over a semiconductive material layer. A conductive gate is formed over the semiconductive material layer. A second insulating layer is formed over the gate and thereafter etched to form a capacitor container. In one implementation, such etch is conducted to outwardly expose the semiconductive material is layer. In another implementation, such etch continues into the semiconductive material layer. In yet another implementation, such etch is conducted completely through the semiconductive material layer and into the first insulating layer.
  • [0007]
    In a preferred implementation, a storage capacitor is formed within the capacitor container which extends both elevationally above and elevationally below the gate. According to another aspect of the invention, adjacent word lines are formed over the first insulating layer and source/drain diffusion regions are formed within the semiconductive material laterally outward of the word lines. Respective capacitor containers are etched into the diffusion regions and capacitors are formed within the etched containers. In a preferred implementation, storage node material which constitutes part of the capacitors is in electrical contact with the respective diffusion regions and comprises part of a DRAM cell.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • [0009]
    [0009]FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention.
  • [0010]
    [0010]FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1.
  • [0011]
    [0011]FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 2.
  • [0012]
    [0012]FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 3.
  • [0013]
    Is FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 4.
  • [0014]
    [0014]FIG. 6 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 5.
  • [0015]
    [0015]FIG. 7 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 6.
  • [0016]
    [0016]FIG. 8 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 7.
  • [0017]
    [0017]FIG. 9 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 8.
  • [0018]
    [0018]FIG. 10 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 9.
  • [0019]
    [0019]FIG. 11 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 10.
  • [0020]
    [0020]FIG. 12 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 11.
  • [0021]
    [0021]FIG. 13 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 12.
  • [0022]
    [0022]FIG. 14 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 13.
  • [0023]
    [0023]FIG. 15 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 14.
  • [0024]
    [0024]FIG. 16 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 15.
  • [0025]
    [0025]FIG. 17 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 16.
  • [0026]
    [0026]FIG. 18 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 17.
  • [0027]
    [0027]FIG. 19 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 18.
  • [0028]
    [0028]FIG. 20 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 19.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0029]
    This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
  • [0030]
    Referring to FIG. 1, a semiconductor wafer fragment in process is indicated generally at reference numeral 10. Fragment 10 preferably comprises a semiconductive substrate 12. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. A first insulating layer 14 is formed over substrate 12 and has a preferred thickness from about 1000 to 20,000 Angstroms. A preferred material for first insulating layer 14 is oxide.
  • [0031]
    Referring to FIG. 2, a semiconductive material layer 16 is formed over first insulating layer 14 to an elevational thickness from preferably about 200 to 10,000 Angstroms. Preferably, layer 16 comprises silicon doped with a p-type material.
  • [0032]
    Referring to FIG. 3, a layer of patterned masking material 18 is formed over layer 16, an example masking material comprises photoresist.
  • [0033]
    Referring to FIG. 4, unmasked portions of semiconductive material layer 16 are etched downwardly to first insulating layer 14 to a degree sufficient to expose underlying layer 14 portions.
  • [0034]
    Referring to FIG. 5, with masking layer 18 having been suitably stripped away, a layer of insulating material 20 is formed over substrate 12. A suitable material is borophosphosilicate glass (BPSG). Although not specifically shown, a thin oxide layer formed from decomposition of tetraethyl orthosilicate (TEOS) can be formed over the substrate in advance of forming insulating material 20.
  • [0035]
    Referring to FIG. 6, insulating material layer 20 is planarized as by suitable mechanical abrasion of the substrate to leave behind individual isolation material/regions 20 on either side of semiconductive material layer 16. Such provides isolation regions over the semiconductor wafer. The FIG. 6 construction constitutes a semiconductive material-on-insulator substrate. In the preferred embodiment, such constitutes a silicon-on-insulator substrate. Accordingly, semiconductive material layer 16 constitutes a semiconductive active area and insulating material layers 20 on either side thereof constitute isolation regions which separate similarly formed active areas over wafer fragment 10. Isolation can also be provided through utilization of LOCOS (LOCal Oxidation of Silicon) techniques.
  • [0036]
    Referring to FIGS. 7 and 8, a plurality of layers are formed over substrate 12 including a thin oxide layer 22, a conductively doped polysilicon layer 23, a silicide layer 24, a thin oxide layer 25, and a masking layer 26, preferably of nitride. Such layers are subsequently patterned and etched (FIG. 8) to form conductive lines 28, 30, 32, and 34. The layered constitution of conductive lines 28, 30, 32, and 34 is but one example of a conductive line construction. Other layered constructions are possible. Conductive lines 28 and 34 overlie insulating material layer of regions 20, while conductive lines 30, 32 overlie the active area defined by semiconductive material layer 16. Accordingly, conductive lines 30, 32 constitute two laterally adjacent transistor gate or word lines which are formed over first insulating layer 14. Following the formation of conductive lines 28, 30, 32, and 34, n-type diffusion regions 44, 46, and 48 can be formed. Diffusion region 46 constitutes a first source/drain diffusion region which is formed within semiconductive material layer 16 and generally between conductive lines 30, 32. Diffusion region 44 constitutes a second source/drain diffusion region which is formed generally laterally outward of conductive lines 30, 32. Similarly, diffusion region 48 constitutes a third source/drain diffusion region which is formed generally laterally outward of conductive lines 30, 32.
  • [0037]
    In the illustrated and preferred embodiment, diffusion regions 44, 46, and 48 are formed within semiconductive material layer 16 and extend completely through the semiconductive material layer and contact or connect with underlying first insulating layer 14. The illustrated source/drain diffusion regions are operatively associated with respective transistor gates 30, 32 to form, in the illustrated and preferred embodiment, what will be a pair of dynamic random access memory (DRAM) cells 50 (FIG. 9).
  • [0038]
    Referring to FIG. 9, sidewall spacers 42 are formed over the respective sidewalls of conductive lines 28, 30, 32, and 34.
  • [0039]
    Referring to FIG. 10, a second insulating layer 52 is formed over the substrate including conductive lines 28, 30, 32, and 34 and semiconductive material layer 16. A preferred material for layer 52 comprises BPSG.
  • [0040]
    Referring to FIG. 11, a masking layer 54 is formed over or atop second insulating layer 52. In accordance with one aspect of the invention, masking layer 54 can comprise polysilicon, the utilization of which reduces polymer formation during subsequent etching to be described just below. A much more preferred material for masking layer 54 is photoresist which can be suitably patterned to define masking openings 58, 60 (FIG. 12). In the event that processing takes place utilizing the preferred photoresist material for layer 54, the etching of the capacitor container openings described below can take place essentially as described with reference to FIGS. 16-20 below. Of course, other masking materials can be utilized.
  • [0041]
    Referring to FIG. 12, a photoresist layer 56 is formed over masking material layer 54 and patterned to define mask openings 58, 60 elevationally over diffusion regions 44, 48 respectively.
  • [0042]
    Referring to FIG. 13, masking material layer 54 is etched or otherwise removed through openings 58, 60 to form masking layer openings or capacitor container mask openings also designated 58, 60. The masking layer openings are defined by respective sidewalls of masking material layer 54 which are not specifically designated. Photoresist layer 56 has been suitably stripped in the FIG. 13 construction.
  • [0043]
    Referring to FIG. 14, a layer 62 comprising polysilicon is formed over masking material layer 54 and within masking layer openings 58, 60.
  • [0044]
    Referring to FIG. 15, portions of polysilicon layer 62 are removed, preferably by anisotropically etching the layer in a manner sufficient to provide polysilicon sidewall spacers 64 over the respective associated sidewall portions of masking material layer 54. Accordingly, such serves to narrow openings 58, 60.
  • [0045]
    Referring to FIG. 16, exposed portions of second insulating layer 52 are etched through the capacitor container mask openings and elevationally downward to form capacitor container openings, also designated 58, 60. The illustrated etch into insulating layer 52 uses masking material layer 54 and sidewalls 64 as an etch mask and preferably extends elevationally downward to laterally adjacent conductive lines 30, 32. Preferably, such etch continues into at least a portion of semiconductive material layer 16, as shown. Accordingly, such etch extends into associated portions of respective diffusion regions 44, 48 which are disposed or received within the semiconductive material layer. In the illustrated and preferred embodiment, such etching continues completely through semiconductive material layer 16 to expose portions of first insulating layer 14. Even more preferably, such etching continues elevationally downward and into first insulating layer 14 to a desired depth which is intermediate the layer's elevational thickness. Accordingly, such etch is conducted entirely through associated portions of source/drain diffusion regions 44, 48 and provides a capacitor container opening which extends both elevationally above and below conductive lines 30, 32 and semiconductive material 16. It will be understood that a bit line contact opening can be formed intermediate conductive lines 30, 32 and through at least insulating layer 52 in connection with the formation of the capacitor container openings just described. Accordingly, formation of an associated bit line contact or contact plug within such bit line contact opening could take place after formation of the storage capacitors described just below.
  • [0046]
    Different etching regimes can, of course, be utilized to effectuate the above described etching of the capacitor containers. For example, a first oxide etch can be conducted which is suitable for etching BPSG layer 52. Upon exposure of associated diffusion regions 44, 48, such etch can be modified to etch the silicon-containing material from which layer 16 is formed. Subsequently, upon exposure of layer 14, such etch can be modified to a second oxide etch which is suitable for etching the material from which layer 14 is formed.
  • [0047]
    Referring to FIG. 17, a layer 66 of capacitor storage node material is formed within individual capacitor container openings 58, 60 and within the container defined thereby. In the illustrated and preferred embodiment, layer 66 is conductive and is formed within the individual capacitor container openings laterally adjacent and in electrical contact with respective second and third source/drain diffusion regions 44, 48. Suitable conductive materials include conductively doped chemical vapor deposited (CVD) polysilicon. Other preferred materials can include rugged polysilicon. Examples of rugged polysilicon include doped cylindrical grain polysilicon, doped hemispherical grain polysilicon, and selective hemispherical grain polysilicon, all of which can be used in connection with a separately provided conductively doped- CVD polysilicon layer. In a preferred implementation, the conductive material from which storage node layer 66 is formed serves as a source of conductivity enhancing dopants for respective diffusion regions 44, 48, with out diffusion therefrom serving to render the diffusion regions even more or suitably conductive. Such effectively provides respective conductively doped source regions for conductive lines 30, 32 which serve as access transistor gates for the illustrated DRAM cells.
  • [0048]
    Referring to FIG. 18, substrate 12 is planarized as by suitable mechanical abrasion thereof in a manner which is sufficient to isolate node material 66 within the respective capacitor container openings 58, 60. Formation of storage capacitors proceeds in accordance with known processing principles.
  • [0049]
    Referring to FIG. 19, capacitor dielectric material 67 is formed over storage node material 66 and within capacitor container openings 58, 60. Subsequently, cell plate structure 68 is formed within the capacitor containers and in operative association with the dielectric material to form capacitor constructions which are, in the preferred embodiment, disposed both elevationally above and elevationally below conductive lines or gates 30, 32. Patterning of layers 67 and 68 occurs over diffusion region 46 for subsequent isolated bit line contact formation.
  • [0050]
    Referring to FIG. 20, an insulating layer 69 is formed over the substrate and a contact opening is subsequently patterned and etched over diffusion region 46. The contact opening is thereafter filled with conductive material to provide bit line contact 70.
  • [0051]
    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Classifications
U.S. Classification438/253, 257/E21.653, 257/E27.112, 257/E27.094, 257/E21.648, 257/E21.651, 257/E21.019
International ClassificationH01L21/02, H01L27/108, H01L21/8242, H01L27/12
Cooperative ClassificationH01L27/10867, H01L28/91, H01L27/10852, H01L27/1087, H01L27/10835, H01L27/1203, H01L27/10861
European ClassificationH01L27/108F8S
Legal Events
DateCodeEventDescription
Apr 29, 2003CCCertificate of correction
Nov 14, 2005FPAYFee payment
Year of fee payment: 4
Nov 4, 2009FPAYFee payment
Year of fee payment: 8
Jan 10, 2014REMIMaintenance fee reminder mailed
Jun 4, 2014LAPSLapse for failure to pay maintenance fees
Jul 22, 2014FPExpired due to failure to pay maintenance fee
Effective date: 20140604