Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010015009 A1
Publication typeApplication
Application numberUS 09/024,940
Publication dateAug 23, 2001
Filing dateFeb 17, 1998
Priority dateFeb 26, 1997
Also published asUS6389689
Publication number024940, 09024940, US 2001/0015009 A1, US 2001/015009 A1, US 20010015009 A1, US 20010015009A1, US 2001015009 A1, US 2001015009A1, US-A1-20010015009, US-A1-2001015009, US2001/0015009A1, US2001/015009A1, US20010015009 A1, US20010015009A1, US2001015009 A1, US2001015009A1
InventorsYoung Wook Heo
Original AssigneeYoung Wook Heo
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of fabricating semiconductor package
US 20010015009 A1
Abstract
A method of fabricating a semiconductor package is provided, which realizes a small-size semiconductor package without performance deterioration, to meet a tendency to miniaturization of electronic products in which semiconductor packages are mounted, such as communication apparatus and computer, provides a new type of compact multi-pin semiconductor package as large as a semiconductor chip mounted thereon, and accomplishes a semiconductor package having multi-function to minimize its mounting area on an electronic product, resulting in minimizing of the products.
Images(6)
Previous page
Next page
Claims(14)
What is claimed is:
1. A method of fabricating a semiconductor package, comprising the steps of:
(a) providing a circuit board sheet constructed in such a manner that a nonconductive material is coated on at least one side of a copper sheet, opposite to a side on which a semiconductor chip is mounted, a plurality of repetitive same circuit patterns having a plurality of bond fingers and solder ball lands are formed on the nonconductive material, at least one rectangular opening is formed in each of the circuit patterns, and a solder mask covers the circuit patterns to protect them, externally exposing the bond fingers and solder ball lands, the bond fingers being arranged on the surfaces of portions of the circuit board sheet, which lie adjacent to the longer sides of the rectangular opening;
(b) attaching the semiconductor chip using adhesive means, to expose a bond pad of the semiconductor chip through the opening formed in each of the plurality of repetitive circuit patterns formed on the circuit board sheet;
(c) electrically connecting the bond pad of the semiconductor chip to the circuit patterns of the circuit board sheet with a wire;
(d) dispensing a sealant and hardening it, to protect the bond fingers, wire and bond pad of the semiconductor chip from external environments;
(e) fusing solder balls on the solder ball lands formed on the circuit board sheet as input/output ports; and
(f) cutting the circuit board sheet in the same size as that of the semiconductor chip, dividing it into chip size packages.
2. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein the rectangular opening formed in the circuit board sheet provided at step (a) is formed at the center of each of the plurality of repetitive circuit patterns.
3. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein the rectangular opening formed in the circuit board sheet provided at step (a) is formed on at least two sides of each of the plurality of repetitive circuit patterns, each opening being shared by neighboring circuit patterns.
4. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein the circuit board sheet is constructed in such a manner that a prepreg of a nonconductive material is located on both sides of the copper sheet, a thin copper foil is laminated on a prepreg located on a side where the circuit patterns to be formed, the circuit patterns are formed in the copper foil through exposure and development processes using a dry film for photoresist and a photomask having a circuit pattern, and the solder mask is coated to protect the circuit patterns.
5. The method of fabricating a semiconductor package as claimed in
claim 2
, wherein a semiconductor chip having bond pads for transmitting signals, which are arranged at the center of its upper surface, is used as the semiconductor chip attached to the circuit board sheet.
6. The method of fabricating a semiconductor package as claimed in
claim 3
, wherein a semiconductor chip having bond pads for transmitting signals, which are arranged in regions adjacent to at least two opposite sides on its upper surface, is used as the semiconductor chip attached to the circuit board sheet.
7. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein the upper surface of the circuit patterns, where the solder ball lands and bond fingers are exposed, are plated with nickel or gold.
8. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein the adhesive means used at step (b) includes an epoxy adhesive or adhesive film.
9. The method of fabricating a semiconductor package as claimed in
claim 1
or
8
, wherein the adhesive means for attaching the semiconductor chip are coated using a screen printer or dispenser.
10. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein at step (b) only semiconductor chip judged as good one by a test which is carried out to semiconductor chips in wafer state is selectively attached.
11. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein the sealant uses a material selected from a group including an epoxy coating liquid, polyimide coating liquid and epoxy encapsulation material.
12. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein at step (e) the solder ball is fused in a manner that a flux is coated on the solder ball land, and reflow is carried out using an oven or furnace at a high temperature of above 150 C. while the solder ball is mounted on the solder ball land.
13. The method of fabricating a semiconductor package as claimed in
claim 12
, wherein a cleaning process is performed after the fusing of the solder ball, to remove unnecessary flux remnants.
14. The method of fabricating a semiconductor package as claimed in
claim 1
, wherein at step (f) the plurality of repetitive same circuit patterns are divided into each pattern using a sawing apparatus, laser or wire cutting apparatus.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of fabricating a semiconductor package and, more particularly, to a method of fabricating a semiconductor package, which forms the semiconductor package as large as a semiconductor chip to reduce its size and make it compact, and attaches all kinds of semiconductor chips, such as a type in which a bond pad is located at the edge of the surface of semiconductor chip or a type in which the bond pad is formed at the center of the surface of semiconductor chip, in an area array form, to form the input/output ports of the semiconductor package, realizing a high-integration and high-performance semiconductor package.

[0003] 2. Discussion of Related Art

[0004] In general, semiconductor packages include a resin sealed package, TCP package, glass sealed package and metal sealed package. These semiconductor packages are divided into an insertion type and surface mount technology (SMT) type according to the packaging method. A typical insertion type includes a dual in-line package (DIP) and pin grid array (PGA), and typical SMT type includes a quad flat package (QFP), plastic leaded chip carrier (PLCC), ceramic leaded chip carrier (CLCC) and ball grid array (BGA). As electronic products become compact, the SMT-type semiconductor package rather than the insertion type is being widely used in order to increase the packing density of components of a print circuit board.

[0005] Conventional QFP and BGA are explained below with reference to FIGS. 1 and 2. FIG. 1 shows a structure of a conventional QFP, constructed of a semiconductor chip 1 in which electronic circuits are integrated, a mounting board 8 a to which semiconductor chip 1 is attached by an epoxy 3, a plurality of leads 8 externally transmitting a signal of semiconductor chip 1, a wire 4 connecting semiconductor chip 1 to leads 8, and sealant 5 covering semiconductor chip 1 and other peripheral components to protect them from external oxidation and corrosion. With this QFP, a signal output from semiconductor chip 1 is transmitted to leads 8 through wire 4, to be sent to a peripheral circuit through a mother board connected to leads 8. A signal generated by the peripheral circuit is transmitted to semiconductor chip 1 through a path opposite to the above one. However, as the performance of the semiconductor chip is improved, the number of pins of the QFP increases but the distance between the pins is technically difficult to reduce below a specific size. Thus, allowing the QFP to hold a lot of pins enlarges the package.

[0006] To overcome this problem, the BGA package has been proposed, which employs a solder ball fused on one side of semiconductor package as its input/output means. Accordingly, the BGA package can process input/output signals larger than those processed by the QFP and it is fabricated smaller than the QFP. Referring to FIG. 2, the BGA is constructed of a circuit board 2 on which a circuit pattern 2 a is formed and a solder mask 2 b is coated to protect circuit pattern 2 a, a semiconductor chip 1 which includes electronic circuits integrated therein and is attached to the center of the surface of circuit board 2, a wire 4 connecting semiconductor chip 1 to circuit pattern 2 a of circuit board 2, to transmit signals, a solder ball 6 fused on circuit pattern 2 a of circuit board 2 to externally transmit signals, and a sealant 5 covering semiconductor chip 1 and other peripheral components to protect them from external oxidation and corrosion.

[0007] With the BGA constructed as above, a signal output from semiconductor chip 1 is transmitted to circuit pattern 2 a through wire 4, and then sent to a mother board through solder ball 6 fused to circuit pattern 2 a, to be supplied to a peripheral circuit. A signal generated by the peripheral circuit is transmitted to semiconductor chip 1 through a path opposite to the above one. However, because the BGA package is larger than the semiconductor chip included therein by several times, there is a limit to reduce the size of electronic products employing the package. Furthermore, the circuit board of the BGA package is expensive, increasing the cost of the products. Moreover, moisture may permeates the package through the circuit board, creating cracks.

SUMMARY OF THE INVENTION

[0008] Accordingly, the present invention is directed to a method of fabricating a semiconductor package that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0009] An object of the present invention is to provide a method of fabricating a semiconductor package, which realizes a small-size semiconductor package without performance deterioration, to meet a tendency to miniaturization of electronic products in which semiconductor packages are mounted, such as communication apparatus and computer, provides a new type of compact multi-pin semiconductor package as large as a semiconductor chip mounted thereon, and accomplishes a semiconductor package having multi-function to minimize its mounting area on an electronic product, resulting in minimizing of the products.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention:

[0012] In the drawings:

[0013]FIGS. 1 and 2 are cross-sectional views showing structures of conventional semiconductor package and BGA package;

[0014]FIGS. 3A to 3G are cross-sectional views showing a method of fabricating a semiconductor package according to the present invention;

[0015]FIG. 4 is a plan view of a circuit board sheet according to an embodiment of the present invention;

[0016]FIG. 5 is a plan view of a circuit board sheet according to another embodiment of the present invention;

[0017]FIG. 6 is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention; and

[0018]FIG. 7 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

[0019] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0020] A method of fabricating a semiconductor package according to the present invention, comprises the steps of (a) providing a circuit board sheet 20 constructed in such a manner that a nonconductive material 22 is coated on at least one side of a copper sheet 21, opposite to a side on which a semiconductor chip is mounted, a plurality of repetitive same circuit patterns 23 having a plurality of bond fingers 26 and solder ball lands 25 are formed on nonconductive material 22, at least one rectangular opening 27 is formed in each of circuit patterns 23, and a solder mask 24 covers circuit patterns 23 to protect them, externally exposing bond fingers 26 and solder ball lands 25, bond fingers 26 being arranged on the surfaces of portions of circuit board sheet 20, which lie adjacent to the longer sides of rectangular opening 27; (b) attaching semiconductor chip 10 using adhesive means 30, to expose a bond pad 11 of semiconductor chip 10 through opening 27 formed in each of the plurality of repetitive circuit patterns 23 formed on circuit board sheet 20; (c) electrically connecting bond pad 11 of semiconductor chip 10 to circuit patterns 23 of circuit board sheet 20 with a wire 40; (d) dispensing a sealant 50 and hardening it, to protect bond fingers 26, wire 40 and bond pad 11 of semiconductor chip 10 from external environments; (e) fusing solder balls 60 on solder ball lands 25 formed on circuit board sheet 20 as input/output ports; and (f) cutting circuit board sheet 20 in the same size as that of semiconductor chip 10, dividing it into chip size packages.

[0021] Circuit board sheet 20 is fabricated in such a manner that prepreg 22 of a nonconductive material is located on both sides of copper sheet 21, thin copper foil 23 a is laminated on prepreg 22 placed on a side where circuit patterns 23 to be formed, circuit pattern 23 is formed in copper foil 23 a through exposure and development processes using a dry film for photoresist and a photomask having a circuit pattern thereon, and solder mask 24 is coated to protect circuit pattern 23. Circuit board sheet 20 includes an opening 27 for opening a region where bond pad 11 of semiconductor chip 10 is located.

[0022]FIGS. 3A to 3G are cross-sectional views illustrating a method of fabricating a semiconductor package according to the present invention. Referring to FIG. 3A showing raw materials for fabricating circuit board sheet 20, prepreg 22 is located on both sides of copper sheet 21, and thin copper foil 23 a is laminated on prepreg 22 placed on a side where circuit pattern 23 to be formed. Copper sheet 21 is formed of copper which easily emits heat. FIG. 3B shows the lamination of copper 21, prepreg 22 and copper foil 23 a. The lamination uses a lamination press which is able to increase temperature above than 150 C. FIG. 3C shows that circuit pattern 23 is formed in laminated copper foil 23 a to fabricate circuit board sheet 20. Referring to FIG. 3C, circuit pattern 23 is formed in such a manner that the dry film for photoresist is attached on copper foil 23 a, and exposure and development processes are carried out using the photomask having a circuit pattern thereon, to form a desired circuit pattern. Then, solder mask 24 is coated thereon to protect circuit patterns 23.

[0023] Circuit pattern 23 consists of the same patterns repeated in vertical and horizontal directions. Opening 27 is formed in a region where bond pad 11 of semiconductor chip 10 is located. Portions of solder mask 24, through which solder ball 60 will be fused on circuit pattern 23 and bond pad 11 of semiconductor chip 10 will be connected to circuit pattern 23 with wire 40, are opened to form solder ball lands 25 and bond fingers 26. Solder ball lands 25 are arranged in an array form. Portions of circuit pattern 23, exposed through solder ball lands 25 and bond fingers 26, are plated with nickel or gold, to improve bonding strength in case of fusing of solder ball 60 or connection of wire 40.

[0024]FIG. 3D shows the coating of adhesive means 30 on a side of circuit board sheet 20, opposite to the one on which circuit pattern 23 is formed. Adhesive means 30 are formed in a manner that an epoxy adhesive or adhesive film is coated using a screen printer or dispenser. FIG. 3E shows the adhesion of semiconductor chip 10 on circuit board sheet 20. Referring to FIG. 3E, semiconductor chip 10 is adhered to circuit board sheet 20 on which adhesive means 30, and the epoxy adhesive or adhesive film forming adhesive means 30 is hardened at a high temperature of above 100 C. Here, bond pad 11 of semiconductor chip 10 is exposed through opening 27 of circuit board sheet 20, and each semiconductor chip 10 is attached to each of the same circuit patterns 23 repeated in vertical and horizontal directions. Furthermore, only semiconductor chip 10 judged as a good one by a test which is carried out to semiconductor chips in wafer state is selectively attached to circuit board sheet 20, preventing a poor semiconductor package.

[0025]FIG. 3F shows that circuit pattern 23 of circuit board sheet 20 is connected to bond pad 11 of semiconductor chip 10 through wire 40, a sealant 50 covers them, and solder ball 60 is fused on circuit pattern 23. Bond pad 11 of semiconductor chip 10, externally exposed through opening 27 of circuit board sheet 20, and bond finger 26 of circuit pattern 23 are connected with wire 40 using a wire bonder. In this state, a coating liquid, such as epoxy and polyimide, or epoxy type encapsulation material is coated on wire 40 and semiconductor chip 10, and then hardened, to form sealing portion 50, protecting the surfaces of wire 40 and semiconductor chip 10. Then, solder ball 60 is fused on solder ball land 25.

[0026] Sealant 50 sealing opening 27 is hardened at an oven or furnace at approximately 150 C. (the fusing point is about 175 C.). To form solder ball 60, first of all, a flux is coated on solder ball land 25, and solder ball 60 is mounted thereon. Thereafter, solder ball 60 undergoes reflow process using an oven or furnace at a high temperature of above 150 C., to be fused on solder ball land 25. After this, a cleaning process is performed to remove unnecessary remnant of the flux. Referring to FIG. 3G showing a step of cutting circuit board sheet 20, circuit board sheet 20 is cut using a sawing apparatus 70, laser or wire cutting apparatus, to divide the same circuit patterns 23 repeated in vertical and horizontal directions into each piece, obtaining the package having the same size as that of semiconductor chip 10.

[0027]FIG. 4 is a plan view showing circuit board sheet 20 in which opening 27 is formed for bond pad 11 formed on semiconductor chip 10 to use a semiconductor chip arranged at the center of the upper surface of semiconductor chip 10. FIG. 5 is a plan view showing circuit board sheet 20 in which opening 27 is formed for bond pad 11 formed on semiconductor chip 10 to use a semiconductor chip arranged at the edge of the upper surface of semiconductor chip 10. FIGS. 6 and 7 are cross-sectional views of the semiconductor package fabricated by the method of the present invention. Referring to FIGS. 6 and 7, the semiconductor package includes: semiconductor chip 10 having electronic circuits integrated thereon, on which bond pad 11 externally transmitting signals from the electronic circuits is formed; an unit circuit board 20′ which is attached on a portion of semiconductor chip 10, other than bond pad 11, with adhesive means 30, and includes copper sheet 21, the upper and lower sides of copper sheet 21 being coated with a nonconductive material, circuit pattern 23 being formed on the upper side; wire 40 for transmitting a signal between bond pad 11 of semiconductor chip 10 and circuit pattern 23; sealant 50 covering the wire bonded area to protect it from external oxidation and corrosion; and solder ball 60 fused on circuit pattern 23, to externally transmit a signal of semiconductor chip 10 sent through wire 40.

[0028] Bond pad 11 formed on semiconductor chip 10 may be arranged at the center of the upper surface of semiconductor chip 10, as shown in FIG. 6. Otherwise, as shown in FIG. 7, bond pad 11 may be arranged at the edges of the upper surface of semiconductor chip 10. The semiconductor package of the present invention is a chip size package which has the same size as that of semiconductor chip 10. With this package, a signal output from semiconductor chip 10 is transmitted to circuit pattern 23 through wire 40, and then supplied to a mother board through solder ball 60 fused on circuit pattern 23, to be sent to a peripheral device. A signal generated by the peripheral device is transmitted to semiconductor chip 10 through a transmission path opposite to the above one.

[0029] According to the present invention, only semiconductor chips judged as good ones by a test which is carried out to semiconductor chips in wafer state are selectively attached to the circuit board sheet, to fabricate the semiconductor package, thereby preventing the generation of poor semiconductor chip and realizing a compact multi-pin semiconductor package.

[0030] It will be apparent to those skilled in the art that various modifications and variations can be made in the method of fabricating a semiconductor package of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6784024 *Sep 25, 2001Aug 31, 2004Micron Technology, Inc.Die attach curing method for semiconductor device
US8051557 *Jul 9, 2008Nov 8, 2011Princo Corp.Substrate with multi-layer interconnection structure and method of manufacturing the same
Legal Events
DateCodeEventDescription
Nov 21, 2013FPAYFee payment
Year of fee payment: 12
Nov 23, 2009FPAYFee payment
Year of fee payment: 8
Jan 3, 2006ASAssignment
Owner name: AMKOR TECHNOLOGY, INC., ARIZONA
Free format text: TERMINATION & RELEASE OF PATENT SECURITY AGREEMENT;ASSIGNOR:CITICORP NORTH AMERICA, INC.;REEL/FRAME:017388/0868
Effective date: 20051128
Owner name: BANK OF AMERICA, N.A., TEXAS
Free format text: SECURITY AGREEMENT;ASSIGNOR:AMKOR TECHNOLOGY, INC.;REEL/FRAME:017379/0630
Effective date: 20051123
Nov 21, 2005FPAYFee payment
Year of fee payment: 4
Nov 2, 2004ASAssignment
Owner name: CITICORP NORTH AMERICA, INC. AS "AGENT", NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:AMKOR TECHNOLOGY, INC.;GUARDIAN ASSETS, INC.;REEL/FRAME:015942/0521
Effective date: 20041027
Owner name: CITICORP NORTH AMERICA, INC. AS "AGENT" 390 GREENW
Free format text: SECURITY AGREEMENT;ASSIGNORS:AMKOR TECHNOLOGY, INC. /AR;REEL/FRAME:015942/0521
Jul 16, 2004ASAssignment
Owner name: AMKOR TECHNOLOGY, INC., PENNSYLVANIA
Free format text: RELEASE OF LIEN ON PATENTS;ASSIGNOR:CITICORP USA, INC. AS COLLATERAL AGENT;REEL/FRAME:015603/0572
Effective date: 20040629
Owner name: AMKOR TECHNOLOGY, INC. 1345 ENTERPRISE DRIVE GOSHE
Free format text: RELEASE OF LIEN ON PATENTS;ASSIGNOR:CITICORP USA, INC. AS COLLATERAL AGENT /AR;REEL/FRAME:015603/0572
Jul 6, 2004ASAssignment
Owner name: CITICORP NORTH AMERICA, INC. AS ADMINISTRATIVE AGE
Free format text: SECURITY AGREEMENT;ASSIGNORS:AMKOR TECHNOLOGY, INC.;GUARDIAN ASSETS, INC.;REEL/FRAME:014885/0691
Effective date: 20040629
Free format text: SECURITY AGREEMENT;ASSIGNORS:AMKOR TECHNOLOGY, INC. /AR;REEL/FRAME:014885/0691
Apr 23, 2003ASAssignment
Owner name: CITICORP USA, INC. AS "COLLATERAL AGENT", DELAWARE
Free format text: SECURITY INTEREST;ASSIGNORS:AMKOR TECHNOLOGY, INC.;GUARDIAN ASSETS, INC.;REEL/FRAME:013974/0893
Effective date: 20030422
Owner name: CITICORP USA, INC. AS "COLLATERAL AGENT" 2 PENNS W
Sep 26, 2002ASAssignment
Owner name: AMKOR TECHNOLOGY, INC., ARIZONA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMKOR TECHNOLOGY KOREA, INC.;REEL/FRAME:013323/0853
Effective date: 20020913
Owner name: AMKOR TECHNOLOGY, INC. 1900 SOUTH PRICE ROADCHANDL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMKOR TECHNOLOGY KOREA, INC. /AR;REEL/FRAME:013323/0853
Aug 14, 2002ASAssignment
Owner name: AMKOR TECHNOLOGY KOREA, INC., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANAM SEMICONDUCTOR, INC.;REEL/FRAME:013193/0683
Effective date: 20000502
Owner name: AMKOR TECHNOLOGY KOREA, INC. 280-8, 2-GA SUNGSU-DO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANAM SEMICONDUCTOR, INC. /AR;REEL/FRAME:013193/0683
Apr 16, 2001ASAssignment
Owner name: CITICORP USA, INC., NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:SOCIETE GENERALE;GUARDIAN ASSETS, INC.;REEL/FRAME:011682/0416
Effective date: 20010330
Owner name: CITICORP USA, INC. 390 GREENWICH STREET NEW YORK N
Owner name: CITICORP USA, INC. 390 GREENWICH STREETNEW YORK, N
Free format text: SECURITY INTEREST;ASSIGNORS:SOCIETE GENERALE /AR;REEL/FRAME:011682/0416
Nov 15, 2000ASAssignment
Owner name: SOCIETE GENERALE, NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:AMKOR TECHNOLOGY, INC.;GUARDIAN ASSETS, INC.;REEL/FRAME:011491/0917
Effective date: 20000428
Owner name: SOCIETE GENERALE 1 FINANCIAL SQUARE, 30TH FLOOR S.
Aug 24, 1998ASAssignment
Owner name: AMKOR TECHNOLOGY, INC., ARIZONA
Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:ANAM INDUSTRIAL CO., LTD.;AMKOR ELECTRONICS, INC.;REEL/FRAME:009411/0215;SIGNING DATES FROM 19980320 TO 19980414
Owner name: ANAM SEMICONDUCTOR INC., KOREA, REPUBLIC OF
Feb 17, 1998ASAssignment
Owner name: AMKOR ELECTRONICS, INC., ARIZONA
Owner name: ANAM INDUSTRIAL CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEO, YOUNG WOOK;REEL/FRAME:009043/0040
Effective date: 19980210