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Publication numberUS20010016398 A1
Publication typeApplication
Application numberUS 09/328,763
Publication dateAug 23, 2001
Filing dateJun 9, 1999
Priority dateJun 9, 1999
Also published asCN1354889A, EP1186028A1, US6426254, WO2000075984A1
Publication number09328763, 328763, US 2001/0016398 A1, US 2001/016398 A1, US 20010016398 A1, US 20010016398A1, US 2001016398 A1, US 2001016398A1, US-A1-20010016398, US-A1-2001016398, US2001/0016398A1, US2001/016398A1, US20010016398 A1, US20010016398A1, US2001016398 A1, US2001016398A1
InventorsStephan Kudelka, Alexander Michaelis, Dirk Tobben
Original AssigneeStephan Kudelka, Alexander Michaelis, Dirk Tobben
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for expanding trenches by an anisotropic wet etch
US 20010016398 A1
Abstract
In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.
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Claims(29)
What is claimed is:
1. A method for expanding trenches comprising the steps of:
forming a trench in a substrate;
preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface; and
anisotropically wet etching the silicon surface of the trench to expand the trench.
2. The method as recited in
claim 1
, wherein the step of preparing surfaces within the trench includes the step of preparing the surface by wet etching the surfaces with hydrogen fluoride.
3. The method as recited in
claim 1
, wherein the step of anisotropically wet etching the trench to expand the trench includes the step of anisotropically wet etching the trench by employing ammonium hydroxide.
4. The method as recited in
claim 1
, wherein the step of anisotropically wet etching the trench to expand the trench includes the step of anisotropically wet etching the trench at temperatures of between about 10° C. to about 80° C.
5. The method as recited in
claim 1
, wherein the step of anisotropically wet etching the trench to expand the trench includes the step of anisotropically wet etching the trench in a batch process.
6. The method as recited in
claim 1
, wherein the step of anisotropically wet etching forms rectangular trenches.
7. The method as recited in
claim 1
, wherein the substrate is comprised of monocrystalline silicon and the step of anisotropically wet etching includes the step of expanding the trench according to crystallographic surfaces of the substrate.
8. The method as recited in
claim 7
, wherein the step of anisotropically wet etching forms a trench with a rectangle shape and the step of expanding the trench according to crystallographic surfaces includes the step of expanding the trench to (110) surfaces.
9. The method as recited in
claim 1
, wherein anisotropically wet etching includes providing a surface planarity of less than 15 nm for sidewalls along a depth of the trench.
10. A method for forming expanded deep trenches for semiconductor devices comprising the steps of:
forming a trench in a substrate;
forming a collar in an upper portion of the trench;
anisotropically etching a lower portion of the trench selective to the collar by:
preparing a surface of the lower portion of the trench by providing a hydrogen terminated surface on the lower portion of the trench; and
anisotropically wet etching the lower portion of the trench to expand the trench.
11. The method as recited in
claim 10
, further comprising the step of forming a buried plate electrode prior to the anisotropic wet etch.
12. The method as recited in
claim 10
, further comprising the step of forming a buried plate electrode following to the anisotropic wet etch.
13. The method as recited in
claim 10
, wherein the step of preparing a surface of the lower portion includes the step of preparing the surface by wet etching the surfaces with hydrogen fluoride.
14. The method as recited in
claim 10
, wherein the step of anisotropically etching includes the step of anisotropically etching by employing ammonium hydroxide.
15. The method as recited in
claim 10
, wherein the step of wet etching includes the step of wet etching the lower portion of the trench at temperatures of between about 10° C. to about 80° C.
16. The method as recited in
claim 10
, wherein the step of anisotropically wet etching includes the step of wet etching the trench in a batch process.
17. The method as recited in
claim 10
, wherein the step of anisotropically wet etching forms rectangular trenches.
18. The method as recited in
claim 10
, wherein the substrate is comprised of monocrystalline silicon and the step of anisotropically wet etching includes the step of expanding the trench according to crystallographic surfaces of the substrate.
19. The method as recited in
claim 18
, wherein the anisotropically wet etching forms a trench with a rectangle shape and the step of expanding the trench according to crystallographic surfaces includes the step of expanding the trench to (110) surfaces.
20. The method as recited in
claim 10
, wherein the wet etching has a selectivity ratio of greater than 1000:1 between the substrate and the collar.
21. The method as recited in
claim 10
, wherein the step of anisotropically wet etching includes providing a surface planarity of less than 15 nm for sidewalls along a depth of the trench.
22. A method for forming expanded deep trenches for semiconductor devices comprising the steps of:
forming a trench in a monocrystalline silicon substrate;
forming an oxide collar in an upper portion of the trench;
preparing a surface of a lower portion of the trench by wet etching the surface with hydrogen fluoride, the surface being prepared to provide a hydrogen terminated surface on the lower portion of the trench; and
anisotropically wet etching with an ammonium hydroxide etchant the lower portion of the trench selective to the collar to expand crystallographic surfaces of the substrate in the lower portion of the trench.
23. The method as recited in
claim 22
, further comprising the step of forming a buried plate electrode prior to the anisotropic wet etch.
24. The method as recited in
claim 22
, further comprising the step of forming a buried plate electrode following to the anisotropic wet etch.
25. The method as recited in
claim 22
, wherein the step of anisotropically wet etching includes the step of wet etching the lower portion of the trench at temperatures of between about 10° C. to about 80° C.
26. The method as recited in
claim 22
, wherein the step of anisotropically wet etching includes the step of wet etching the trench in a batch process.
27. The method as recited in
claim 22
, wherein the anisotropically wet etching forms a trench with a rectangle shape and the trench is expanded to (110) surfaces of the substrate.
26. The method as recited in
claim 22
, wherein the anisotropically wet etching has a selectivity ratio of greater than 1000:1 between the substrate and the collar.
27. The method as recited in
claim 22
, wherein anisotropically wet etching includes providing a surface planarity of less than 15 nm for sidewalls along a depth of the trench.
Description
BACKGROUND

[0001] 1. Technical Field

[0002] This disclosure relates to semiconductor fabrication and more particularly, to a method for forming bottle shaped trench capacitors for semiconductor memories by employing an anisotropic wet etch process.

[0003] 2. Description of the Related Art

[0004] The extendability of deep trench based memory devices is limited by the storage capacitance of the deep trench as the ground rules shrink. Since the capacitance that can be stored in the deep trench is a linear function of the surface area of the deep trench, the formation of a larger trench is beneficial. However, widening a deep trench has a large impact on layout area of a semiconductor chip.

[0005] Attempts have been made to increase the surface area of a deep trench below an insulating collar which is formed within the deep trench. The region below the insulating collar is not as limited in available area as an upper portion of the deep trench. To expand the region below the collar, an isotropic silicon reactive ion etch (RIE) process can be employed. The RIE process recesses a silicon substrate below the insulating collar to provide increased surface area. The RIE process suffers from many disadvantages. These disadvantages include:

[0006] 1. Low selectivity to oxide. With the reactive ion etch process the insulating collar is also etched thereby reducing the thickness of the insulating collar. The insulating collar is, for example, a LOCOS oxide or a deposited oxide. When this oxide is thinned vertical leakage currents may occur.

[0007] 2. Expensive process. The RIE tools are expensive and have a low throughput due to the need for single wafer processing.

[0008] 3. Collateral damage. The RIE process leaves polymer deposits in etched areas which may have a detrimental effect on component performance. The RIE process may cause surface damage to etched areas and undesirable side pockets may be formed in etched areas.

[0009] Therefore, a need exists for an improved method for increasing surface area of deep trench capacitors. A further need exists for a more economical method of increasing the surface area of the deep trench capacitors.

SUMMARY OF THE INVENTION

[0010] In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to substantially remove native oxide (create an H-terminated surface) from the surfaces within the trench and anisotropically wet etching the surfaces of the trench to expand the trench.

[0011] A method for forming expanded deep trenches for semiconductor devices includes the steps of forming a trench in a substrate, forming a collar in an upper portion of the trench, anisotropically etching a lower portion of the trench selective to the collar by: preparing a surface of the lower portion of the trench by providing a hydrogen terminated surface on the lower portion of the trench and wet etching the lower portion of the trench with a basic solution to expand the trench.

[0012] Another method for forming expanded deep trenches for semiconductor devices includes the steps of forming a trench in a monocrystalline silicon substrate, forming an oxide collar in an upper portion of the trench, preparing a surface of a lower portion of the trench by etching the surface with hydrogen fluoride, the surface being prepared to provide a hydrogen terminated surface on the lower portion of the trench and anisotropically wet etching, with an ammonium hydroxide etchant, the lower portion of the trench being etched selective to the collar to expand the trench to crystallographic surfaces of the substrate in the lower portion of the trench.

[0013] In alternate embodiments, the step of preparing surfaces within the trench may include the step of preparing the surface by etching the surfaces with hydrogen fluoride. The step of anisotropically wet etching the trench to expand the trench may include the step of anisotropically wet etching the trench by employing ammonium hydroxide. The step of anisotropically wet etching the trench to expand the trench may also include the step of anisotropically wet etching the trench at temperatures of between about 10° C. to about 80° C. The step of anisotropically wet etching the trench to expand the trench may further include the step of anisotropically wet etching the trench in a batch process. The step of anisotropically wet etching preferably forms rectangular trenches. The substrate is preferably comprised of monocrystalline silicon, and the step of anisotropically wet etching may include the step of removing silicon from the trench according to crystallographic surfaces of the substrate. The anisotropic wet etching preferably forms a trench with a rectangle shape, and the step of removing may include the step of expanding surfaces of the trench to (110) surfaces. The wet etching preferably provides smoother surfaces than conventional methods of etching. For example, a surface planarity is 15 nm or less over a depth of a trench. The steps of forming a buried plate electrode prior to the anisotropic etch or after the anisotropic etch may be included. The step of wet etching preferably has a selectivity ratio of greater than 1000:1 between the substrate and the collar. The present invention also improves surface roughness of the silicon substrate surface over the surface roughness for RIE processes.

[0014] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0015] This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:

[0016]FIG. 1 is a cross-sectional view of a conventional semiconductor device having a trench formed therein for processing in accordance the present invention;

[0017]FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 having a buried plate being formed therein by employing a dopant source layer for processing in accordance the present invention;

[0018]FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2 having a buried plate formed therein for processing in accordance the present invention;

[0019]FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 having a dielectric layer formed therein for preparing the trench for collar formation for processing in accordance the present invention;

[0020]FIG. 5 is a cross-sectional view of a semiconductor device showing a dopant source stack in an alternate method for forming a buried strap for processing in accordance the present invention;

[0021]FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5 showing the buried strap and a collar formed for processing in accordance the present invention;

[0022]FIG. 7 is a cross-sectional view of the semiconductor device of FIGS. 4 or 6 showing the lower portion of the trench prepared in accordance with the present invention;

[0023]FIG. 8 is a cross-sectional view of the semiconductor device of FIG. 7 showing the lower portion of the trench anisotropically wet etched in accordance with the present invention;

[0024]FIG. 9 is a cross-sectional view of a semiconductor device showing a lower portion of the trench lined with a barrier layer and filled with a resist for processing in accordance with the present invention;

[0025]FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9 showing the lower portion of the trench prepared in accordance with the present invention;

[0026]FIG. 11 is a cross-sectional view of the semiconductor device of FIG. 10 showing the lower portion of the trench anisotropically wet etched in accordance with the present invention;

[0027]FIG. 12 is a cross-sectional view of the semiconductor device of FIG. 11 showing the lower portion of the trench gas doped to form a buried strap in accordance with the present invention;

[0028]FIG. 13 is a cross-sectional view of a semiconductor substrate showing trenches formed in accordance with the prior art;

[0029]FIG. 14 is a top view of the semiconductor substrate of FIG. 13 showing trenches formed in accordance with the prior art;

[0030]FIG. 15 is a cross-sectional view of the semiconductor substrate of FIGS. 13 and 14 showing trenches anisotropically wet etched to expand the trenches below a collar formed in the trenches in accordance with the present invention; and

[0031]FIG. 16 is a cross-sectional view taken along section line 16-16 of FIG. 15 showing rectangular shaped trench cross-sections and miller indices for (110) crystal surfaces of the substrate in accordance with the present invention; and

[0032]FIG. 17 is a cross-sectional view of a semiconductor substrate showing trenches anisotropically wet etched to expand the trenches along the entire depth of the trenches in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0033] The present invention relates to semiconductor fabrication and more particularly, to a method for forming bottle shaped trench capacitors for semiconductor memories by employing an anisotropic wet etch process. To increase the capacitance of a single storage cell of a deep trench memory device, the deep trench needs to be expanded to increase surface area. A reactive ion etch (RIE) process may be used to form a bottle shaped trench, but suffers from a high cost single wafer process, polymer residuals left as a result of this type of etching, surface roughness and poor selectivity to a LOCOS collar oxide.

[0034] To overcome these disadvantages, the present invention includes a basic (pH greater than 7) chemistry wet etch, which may be performed in a batch tank process. The method of the present invention is advantageously selective to oxide and nitride, and smooths surfaces where etching occurs. The present invention also preferably creates a rectangular shaped deep trench which provides increased surface area as compared to the RIE process which forms round trenches.

[0035] Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 1, a memory device 100 includes a substrate 102 having a pad stack 101 formed thereon. Memory device 100 may include a dynamic random access memory (DRAM), synchronous DRAM, static RAMs, and read only memories or other memory integrated circuits. Substrate 102 is preferably a monocrystalline silicon substrate, however other substrates may be employed, for example a silicon on insulator substrate. Pad stack 101 may include various layers of materials used to further process memory device 100. In a preferred embodiment, pad stack 101 includes an oxide layer 104 and a nitride layer 106. A hard mask layer 108 is deposited on pad stack 101. Hard mask 108 is patterned using lithographic techniques known to those skilled in the art. For example, a resist layer may be deposited on hardmask layer 108, exposed and developed to open up holes at locations where trenches 110 will be formed. Formation of trench 110 is preferably formed by employing an anisotropic etch, such as a reactive ion etch (RIE). Trench 110 is etched into substrate 102.

[0036] In an alternate embodiment, trench 110 is widened using a wet anisotropic etch process as described herein below in accordance with the present invention. In this alternate approach, hardmask 108 or an equivalent is employed to locate trenches 110 and after trench 110 is formed the entire trench is widened by the wet etch process. (See FIG. 17).

[0037] It is to be understood that a buried plate may be formed prior to or after the expansion of the trenches in accordance with the present invention. Referring to FIG. 2, a method for forming buried plate 112 (FIG. 3) before expansion of the trench may be employed. After removing hardmask 108, trench 110 may preferably be lined with arsenic silicate glass (ASG) layer 111 (other dopant sources may be employed as well), serving as a dopant source for forming buried plate 112. A resist layer 103 (or equivalent) may be formed over ASG layer 111 to fill trench 110. Resist layer 103 is etched back and ASG layer 111 is etched such that ASG layer 111 lines trench 110 at a lower portion only. Resist layer 103 is then removed.

[0038] Referring to FIG. 3, a buried plate 112 is formed by annealing device 100 to drive dopants into substrate 102 from ASG layer 112. Buried plate 112 functions as one of the two capacitor electrodes employed in a trench capacitor. ASG layer 111 is removed.

[0039] Referring to FIG. 4, a nitride layer 119 is deposited to preferably about 50 A in thickness. A resist material (not shown) is deposited within trench 110 and recessed to mark a location where a collar is to be formed in later steps. Exposed portions of layer 119 are removed, and then the remaining resist material is removed from trench 110. A collar 116 is formed in an upper portion of trench 110. Collar 116 is formed on substrate 102 preferably by performing an oxidation process(for example a local oxidation of silicon (LOCOS)) of the silicon in substrate 102. Layer 119, preferably a nitride, protects lower portions of trench 110 from this oxidation (since nitride acts as a barrier). Other processes may be employed to form collar 116 as well. For example, a TEOS deposition process may be employed. Collar 116 is formed to prevent parasitic leakage currents from discharging the trench capacitor in operation. Remaining portions of layer 119 are removed selective to collar 116. Collar 116 may be annealed to densify the oxide material.

[0040] Referring to FIG. 5, a self-aligned method for forming buried plate 112 (FIG. 6) prior to expanding the trench may be employed. After removing hardmask 108 (FIG. 1), trench 110 may be lined with arsenic silicate glass (ASG)/TEOS stack 105, serving as a dopant source for forming buried plate 112 (FIG. 6). The thin TEOS layer(or equivalent) may be formed over the ASG layer (or other dopant source material) to form stack 105. A nitride liner 107 is then deposited, and trench 110 is filled with a resist 121. Resist 121 is etched back to define a lower portion of a collar to be formed in a later step. Stack 105 and layer 107 are removed to the defined lower position where the collar will be formed. Resist 121 is then removed.

[0041] Referring to 6, a buried plate 112 and collar 116 are formed by oxidizing device 100 to drive dopants into substrate 102 from ASG of stack 105 to form buried plate 112. Buried plate 112 functions as one of the two capacitor electrodes employed in a trench capacitor. The ASG/TEOS/nitride layer as described in FIG. 5 is formed to line trench 110. The nitride material of layer 107 is formed to protect surfaces of substrate 102 in trench 110 from oxidation during collar formation. A collar 116 is formed in an upper portion of trench 110. Collar 116 is formed on substrate 102 preferably by performing an oxidation (LOCOS) of the silicon in substrate 102. Layer 107 protects lower portions of trench 110 from this oxidation since nitride acts as a barrier. Other processes may be employed to form collar 116 as well. For example, a TEOS deposition process may be employed. Collar 116 is formed to prevent parasitic leakage currents from discharging the trench capacitor in operation. Remaining portions of stack 105 and layer 107 are removed selective to collar 116. Collar 116 may be annealed to densify the oxide material.

[0042] Referring to FIG. 7, the two alternative paths (FIG. 4 and FIG. 6) for forming a buried plate 112 prior to expanding the trench provide the structure of FIG. 7. Collar 116 protects an upper portion of trench 110. The lower portion of trench 110 is now processed in accordance with the invention. An anisotropic wet etch process in accordance with the present invention is preferably preceded by a preparation step. The preparation step may employ a wet etch, a dry etch or other process steps capable of removing native oxygen from a surface 120. In a preferred embodiment, the preparation step employs a diluted hydrofluoric (200 to 1) wet etch of surface 120 to prepare surface for further processing. The preparation step may include other processes, such as an HF vapor etch or an H2 bake, for example. The preparation step creates a hydrogen terminated surface. By reacting HF with Si, hydrogen atoms remain at surface 120. The HF preparation process is preferably performed for between about 60 seconds to about 180 seconds (for 200:1, parts water to parts HF), however other times and concentrations may be used depending on the design and circumstances. Other preparation processes are contemplated provided a hydrogen terminated silicon surface is provided. The preparation step may be omitted in some embodiments if native oxide is removed in conjunction with other process steps.

[0043] Referring to FIG. 8, the preparation step is followed by an anisotropic etch process. A wet etchant is employed to anisotropically etch away silicon of substrate 102. The wet etchant preferably includes a basic solution. In a preferred embodiment, ammonium hydroxide (NH4OH) is employed as an etchant (NH4OH may be diluted in water, for example 180 parts water to 1 part NH4OH), although other preferred solutions may include potassium hydroxide or other bases, i.e., solutions with a pH greater than 7). The etching process is more uniform due to the hydrogen terminated surface created by the preparation step. The etching is preferably performed at a temperature of between about 10° C. to about 80° C., although other temperature conditions may be used depending on the circumstances. The wet etching process may be performed for between about 60 seconds to about 300 seconds depending on the amount of etching desired, the temperature conditions and the concentration of the etchant. If ammonium hydroxide is employed a selectivity of greater than 1000:1 is achieved relative to collar 116.

[0044] Crystallographic directions of substrate 102 advantageously affect the etching process. In one embodiment, a (100) silicon surface gets etched faster than a (110) silicon surface. This is advantageous since the (110) surfaces may be oriented in a direction where expansion of trenches 110 is less desirable, for example, expansion in a direction toward another trench. In addition, lower surface roughness and higher surface planarity are achieved due to the wet etching process. For example, by employing the wet etch process surface planarity is reduced to below 15 nm, and preferably below 4 nm over the depth of a trench (e.g., 6 microns or deeper). Other surface features may benefit from the present invention as well. This dramatically is improved over the surface planarity of about 20 nm achieved by conventional RIE processes.

[0045] Trenches 110 are positioned to orient the direction of the silicon crystal in accordance with the expansion etch rates most advantageous to the design. The dopant density may also be adjusted in buried plate 112 to affect etch rates for the etch process in accordance with the invention. In addition, since crystal directions affect the etch rates, rectangular lower portions 125 of trenches 110 are achieved. This results in an area increase for trench 110 of up to about 80% or higher. Also, the etch process of the present invention leaves collar 116 substantially untouched by the etching process. Further, the wet etch process lends itself to inexpensive batch processing with high throughput and employs inexpensive chemistry.

[0046] After expansion of trench 110, a nitride dielectric is deposited to line trench 110, a storage node (not shown) is formed within trench 110 using methods known to those skilled in the art. Storage node is preferably formed by depositing polysilicon in trench 110. This may be performed in steps or all in a single process.

[0047] Referring to FIG. 9, an alternate method of the present invention forms a buried plate after the anisotropic wet etch process to expand the trench. After the structure in FIG. 1 is provided, a nitride liner 114 is deposited in trench 110. A resist 130 is formed in trench 110 and recessed to a location where an insulating collar will be formed in later steps. Recessing resist 130 exposes a portion of nitride liner 114. The exposed portions of nitride liner 114 are removed preferably by a wet etch process.

[0048] Referring to FIG. 10, a collar 116 is formed in an upper portion of trench 110. Collar 116 is formed on substrate 102 preferably by performing an oxidation (LOCOS) of the silicon in substrate 102. Liner 114 (FIG. 9) protects lower portions of trench 110 from this oxidation since nitride acts as a barrier. Remaining portions of liner 114 are removed selective to collar 116. Collar 116 may be annealed to densify the oxide material. A surface 131 may be prepared using the preparation step as described above with reference to FIG. 7.

[0049] Referring to FIG. 11, the anisotropic wet etch process which may include the preparation step and an etch as described above with reference to FIGS. 7 and 8 is performed to expand a lower portion 127 of trench 110 below collar 116.

[0050] Referring to FIG. 12, since a buried plate was not formed prior to the wet etch, buried plate 112 is formed by a gas doping process. Gas doping provides dopants in a gaseous form which adsorb onto an exposed surface substrate 102 and diffuse into substrate to form buried plate 112. Gas doping may include arsenic or other dopants included in a hot gas introduced into trench 110.

[0051] After formation of buried plate 112, a nitride dielectric is deposited to line trench 110, a storage node (not shown) is formed within trench 110 using methods known to those skilled in the art. Storage node is preferably formed by depositing polysilicon in trench 110. This may be performed in steps or all in a single process.

[0052] Referring to FIGS. 13 and 14, a cross-sectional view of a silicon semiconductor substrate 200 is shown. Substrate 200 includes trenches 202 formed in accordance with the prior art. Trenches 202 represent trenches which have been formed by conventional methods and are to be expanded in accordance with the present invention. As shown in FIG. 14, deep trenches have a generally circular shape. (110) crystallographic surfaces extend vertically and horizontally as indicated in FIG. 14.

[0053] Referring to FIG. 15, trenches 202 (FIGS. 13 and 14) include a portion which is to be widened or expanded below a collar 208. In one illustrative embodiment, lower portions 206 of trenches 202 may be laterally recessed beyond collar 208 by more than about 50 nm as indicated by “D”. Other dimensions are contemplated as well.

[0054] Referring to FIG. 16, a cross-sectional view of substrate 200 taken along section line 16-16 of FIG. 15 is shown. Rectangular shapes are shown for expanded portions 206 of trenches 202. (110) crystal surfaces are indicated. Due to the anisotropic nature of the wet etch process in accordance with the present invention, all crystallographic surfaces are expanded outward at a faster rate than the expansion of (110) crystal surfaces. For example, the wet etching process in accordance with the present invention etches (100) surfaces faster than (110) surfaces to provide the rectangular shapes shown. Once the rectangular shape is achieved corresponding to (110) surfaces, etching may be continued at a slower rate for (110) surfaces while maintaining the rectangular shape. The length and width of the trenches are advantageously aligned to the (110) surfaces and circular trenches are advantageously expanded to (110) surfaces.

[0055] Referring to FIG. 17, trenches 202 (FIGS. 13 and 14) may alternately by expanded along the entire depth “T” of the trench by employing the wet anisotropic etch process of the present invention. Expanded trenches 210 are thereby formed in substrate 200.

[0056] Although described in several illustrative embodiments, the present invention is not limited by these examples. Other processes and materials may be used. For example, the insulating collar may be formed using different processes or made from different compounds, e.g., TEOS. Further, the invention is not limited to deep trenches and may be applicable to widening any trenches formed in substrates. Also, HF and NH4OH may be employed as etchants in different combinations, substituted by other materials or used in combination with other etchants or compounds. The invention provides an anisotropic wet etch to form bottle shaped trenches or widen trenches, with at least the following advantages.

[0057] 1. High selectivity towards oxide and nitride: no collar thinning.

[0058] 2. Inexpensive process: wet batch process with high throughput and inexpensive chemistry employed.

[0059] 3. Higher storage capacitance: a rectangular shaped trench is formed, that has higher capacitance than a round shaped trench of the same depth.

[0060] 4. Lower surface roughness: due to the anisotropic nature of the etching, only one crystallographic orientation is prepared, which gives a very smooth surface and better than 15 nm surface planarity.

[0061] Having described preferred embodiments for a method for expanding trenches by an anisotropic wet etch (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6417063 *Jun 22, 2000Jul 9, 2002Infineon Technologies Richmond, LpFolded deep trench capacitor and method
US6969648 *Jun 25, 2003Nov 29, 2005International Business Machines CorporationMethod for forming buried plate of trench capacitor
US7115934 *Mar 26, 2004Oct 3, 2006International Business Machines CorporationMethod and structure for enhancing trench capacitance
US7157382 *Feb 9, 2005Jan 2, 2007Infineon Technologies AgMethod for expanding a trench in a semiconductor structure
US7294554 *Feb 10, 2006Nov 13, 2007International Business Machines CorporationMethod to eliminate arsenic contamination in trench capacitors
US7521748Oct 19, 2007Apr 21, 2009International Business Machines CorporationMethod to eliminate arsenic contamination in trench capacitors
US7569490 *Mar 15, 2005Aug 4, 2009Wd Media, Inc.Etchant solution comprising dilute acid and adsorbate comprising 2-benzimidazole proprionic acid, generating electric field within etchant solution, and anisotropically etching pattern in NiP surface; discrete track recording pattern
US8236710 *Oct 7, 2010Aug 7, 2012International Business Machines CorporationTechnique to create a buried plate in embedded dynamic random access memory device
US8563446May 18, 2012Oct 22, 2013International Business Machines CorporationTechnique to create a buried plate in embedded dynamic random access memory device
US20120086103 *Oct 7, 2010Apr 12, 2012International Business Machines CorporationTechnique to create a buried plate in embedded dynamic random access memory device
US20140061868 *Jul 17, 2013Mar 6, 2014Fuji Electric Co., Ltd.Method of manufacturing a semiconductor device and a semiconductor device
DE10317151B4 *Apr 14, 2003Aug 11, 2011Qimonda AG, 81739Ätzprozess zum Einsenken von Polysilizium in Grabenstrukturen einer DRAM-Speicherzelle
DE102004006545B3 *Feb 10, 2004Aug 11, 2005Infineon Technologies AgVerfahren zum Aufweiten eines Grabens in einer Halbleiterstruktur
Classifications
U.S. Classification438/427, 438/422, 257/E21.223, 257/E21.651, 438/749, 438/751
International ClassificationH01L21/308, H01L21/306, H01L21/8242, H01L27/108
Cooperative ClassificationH01L27/10861, H01L21/30608
European ClassificationH01L27/108M4B6, H01L21/306B3
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