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Publication numberUS20010018252 A1
Publication typeApplication
Application numberUS 09/751,388
Publication dateAug 30, 2001
Filing dateJan 2, 2001
Priority dateDec 30, 1999
Also published asUS6426300
Publication number09751388, 751388, US 2001/0018252 A1, US 2001/018252 A1, US 20010018252 A1, US 20010018252A1, US 2001018252 A1, US 2001018252A1, US-A1-20010018252, US-A1-2001018252, US2001/0018252A1, US2001/018252A1, US20010018252 A1, US20010018252A1, US2001018252 A1, US2001018252A1
InventorsWon Park, Phil Kong, Ho Lee, Dong Lee
Original AssigneePark Won Soung, Kong Phil Goo, Lee Ho Seok, Lee Dong Duk
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for fabricating semiconductor device by using etching polymer
US 20010018252 A1
Abstract
The present invention discloses a method for fabricating a semiconductor device using an etch-resistant polymer. The method includes a step for the in-situ generation of a polymer layer on the exposed surfaces of a photoresist film pattern, a pad oxide film, and a hard mask layer. This polymer acts as a protective film and prevents photoresist erosion during trench etching processes and improves the etch selectivity. As a result, trench structures can be formed more easily and with improved dimensional control.
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Claims(10)
What is claimed is:
1. A method for fabricating a semiconductor device using an etching polymer, comprising the steps of:
forming an insulating film having a stacked structure comprising a pad oxide film and a hard mask layer on a semiconductor substrate;
forming a photoresist film pattern on the insulating film, the photoresist pattern exposing a predetermined device isolation region on the insulating film;
etching the insulating film using the photoresist film pattern as a mask to form an insulating film pattern, the insulating film pattern exposing predetermined regions of the semiconductor substrate;
forming a polymer layer on the exposed surfaces of the photoresist film pattern and the insulating film pattern;
etching the exposed regions of the semiconductor substrate to open a trench for device isolation in the semiconductor substrate; and
filling the trench with a device isolation film.
2. The method according to
claim 1
, wherein forming the polymer layer further comprises adjusting plasma parameters in a high density plasma chemical vapor deposition system to induce the formation and redeposition of a polymer.
3. The method according to
claim 2
, wherein the plasma parameters further comprise a pressure between 10 and 50 mTorr, a source power between 600 and 2000 W, and a bias power of not more than 100 W.
4. The method according to
claim 2
, wherein forming the polymer layer further comprises injecting a main gas into the high density plasma chemical vapor deposition system, the main gas comprising at least one gas selected from the group consisting of Cl2, HBr, SF6 and CF4.
5. The method according to
claim 4
, wherein the main gas is injected at a flow rate of between 10 and 100 SCCM.
6. The method according to
claim 4
, wherein the main gas is injected at a flow rate of between 30 and 70 SCCM.
7. The method according to
claim 4
, wherein forming the polymer layer further comprises injecting an auxiliary gas into the high density plasma chemical vapor deposition system, the auxiliary gas comprising at least one gas selected from the group consisting of O2, N2 and an inert gas.
8. The method according to
claim 1
, wherein forming the polymer layer further comprises reacting carbon from the photoresist film pattern, halogen from the main gas, and silicon from the insulating film to form a polymer.
9. A semiconductor device fabricated according to the method of
claim 1
.
10. A method for fabricating a semiconductor device using an etching polymer, comprising the steps of:
forming an insulating film on a semiconductor substrate;
forming a photoresist film pattern on the insulating film, the photoresist pattern exposing predetermined regions on the insulating film;
etching the insulating film using the photoresist film pattern as a mask to remove predetermined regions of the insulating film and expose the underlying regions of the semiconductor substrate;
forming a polymer layer on the exposed surfaces of the photoresist film pattern and the insulating film; and
etching the exposed regions of the semiconductor substrate.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a method for fabricating a semiconductor device by using an etching polymer and, in particular, to an improved method suitable for a process having a small photoresist margin during the trench etching process, by generating a polymer on a surface of a photoresist film pattern used as an etching mask. By generating this polymer on the surface of the photoresist before the trench etching process, and employing the polymer as a protective film for preventing photoresist erosion during the etching process, the present method improves the etching resistance of the photoresist.
  • [0003]
    2. Description of the Background Art
  • [0004]
    When a semiconductor device is fabricated using a method having a design rule below 0.10 μm, the increase in trench depth and reduction in design rule require that the thickness of the photoresist mask is reduced in the shallow trench isolation (STI) process. Accordingly, the etching margin for the photoresist mask becomes excessively small in a trench etching process. In some cases, the photoresist film will be eroded during the trench etching process, making it impossible to etch the desired pattern into the semiconductor substrate while maintaining the desired degree of dimensional control.
  • SUMMARY OF THE INVENTION
  • [0005]
    Accordingly, an object of the present invention is to provide a method for fabricating a semiconductor device by using an etching polymer which can improve the etch selectively or etch ratio with respect to a photoresist, by generating a polymer on the photoresist surface, and employing this polymer as a protective film for preventing photoresist erosion during the trench etch process, particularly for semiconductor devices fabricated using methods with a design rule below 0.10 μm.
  • [0006]
    In order to achieve the above-described object of the present invention, a method for fabricating a semiconductor device by using an etching polymer, includes the steps of: forming an insulating film having a stacked structure comprising a pad oxide film and a hard mask layer on a semiconductor substrate; forming a photoresist film pattern that exposes a device isolation region on the insulating film; etching the insulating film using the photoresist film pattern as an etching mask to expose the semiconductor substrate; forming a polymer layer on the surfaces of the photoresist film pattern and the insulating film pattern; form a trench for device isolation, by etching the exposed semiconductor substrate using the polymer layer as an etching mask; and forming a device isolation film in the trench.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    The present invention will become better understood with reference to the accompanying figures. These figures are provided by way of illustration only and thus should not be understood to limit the scope of the present invention unnecessarily.
  • [0008]
    [0008]FIGS. 1 through 4 are cross-sectional diagrams illustrating sequential steps of a trench formation process of a method for fabricating a semiconductor device by using an etching polymer according to the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0009]
    A method for fabricating a semiconductor device by using an etching polymer in accordance with the present invention will now be described in detail with reference to the accompanying figures.
  • [0010]
    As illustrated in FIG. 1, a pad oxide film 21 and a hard mask layer 22 are formed on a semiconductor substrate 10. Here, the hard mask layer 22 may comprise a Si3N4 film, SiON film or an oxide film.
  • [0011]
    A photoresist film pattern 30 is then formed on the hard mask layer 22. The photoresist film pattern 30 is formed in a conventional manner by coating a photoresist film over the hard mask layer 22 and then exposing the photoresist to form a device isolation pattern.
  • [0012]
    As shown in FIG. 2, an insulating film 20 having a stacked structure of the hard mask layer 22 and the pad oxide film 21 is then etched using the photoresist film pattern 30 as a mask, to expose the surface of the semiconductor substrate 10.
  • [0013]
    Referring to FIG. 3, a polymer layer 40 is then formed over the resultant structures formed on the semiconductor substrate 10.
  • [0014]
    Specifically, the polymer layer 40 is formed by injecting a main gas, preferably Cl2, HBr, SF6 or CF4, into an etching system before etching the semiconductor substrate 10 and inducing polymerization of the resist layer by controlling the plasma parameters within the etching system. The main gas is injected in a flow rate of 10 to 100 SCCM, preferably 30 to 70 SCCM. In addition, during the formation of the polymer layer 40, at least one gas selected from the group consisting of O2, N2 and an inert gas is also injected into the etching system as an auxiliary gas, thereby enhancing adhesion of the polymer.
  • [0015]
    The etching system is generally a high density plasma chemical vapor deposition (HDPCVD) system. The plasma parameters for forming the polymer layer before the etching process are set up so that pressure is between 10 and 50 mTorr, the source power is between 600 and 2000 W, and the bias power is not more than 100 W.
  • [0016]
    As depicted in FIG. 4, the semiconductor substrate 10 is then etched using the polymer layer as a mask, to form trench 40.
  • [0017]
    In a succeeding process, the polymer layer 40 and the photoresist film pattern 30 are removed, and a device isolation film (not shown) that fills trench 50 is formed.
  • [0018]
    The principle of generating the polymer layer 40 will now be described in more detail.
  • [0019]
    When the power is low and pressure is high in the etching system, reactive ion etching (RIE) by ion bombardment decreases and etching by-products are redeposited on the wafer being etched. That is to say, when the plasma parameters in the etching system are adjusted in order to form the polymer, carbon and perhaps other organic components from the photoresist film pattern 30, silicon from the insulating film 20, and halogen atoms from the main gas are plasma polymerized and redeposited as a polymer layer on the surfaces of the photoresist film pattern 30 and the insulating film 20. This redeposited polymer layer is very resistant to plasma etch and thus efficiently protects the photoresist. In addition, once formed, the polymer layer 40 does not tend to chemically react with plasma consisting of halogen groups, but is physically eroded by high energy ions generated within the plasma. Therefore, etching selectivity between polymer and silicon substrate is higher than that between photoresist and silicon substrate.
  • [0020]
    When the polymer layer 40 is formed, at least one gas selected from the group consisting of O2, N2 and an inert gas is injected into the etching system as an auxiliary gas. The auxiliary gas serves to enhance adhesion of the polymer, thus improving the etch resistance of the polymer layer 40.
  • [0021]
    When the photoresist is subjected to the trench etch process without generating the polymer layer, the maximum etch depth is about 2500 Å. However, when the photoresist having the polymer layer is subjected to the trench etch process, the photoresist etching selection ratio is dramatically increased, thereby allowing the maximum etch depth to be increased to 5000 Å.
  • [0022]
    Moreover, the present invention can also be applied to a trench capacitor etching process for forming a trench type capacitor.
  • [0023]
    As discussed earlier, in accordance with the present invention in the trench etching process, the use of a thin photoresist film is made possible by improving the photoresist selection ratio, and a photoresist margin is increased by forming a deep trench. In addition, using the hard mask layer as an etching mask simplifies the process, thereby improving productivity.
  • [0024]
    Using the present method, even on semiconductor devices that are highly integrated with design rules below 0.10 μm, and the thickness of the photoresist film is below 0.30 μm for fine pattern formation processes, conventional etching processes can still be used largely as is, thereby saving the expense of new systems and additional process development work.
  • [0025]
    As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the particular details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims. Therefore, all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7279397 *Jul 27, 2004Oct 9, 2007Texas Instruments IncorporatedShallow trench isolation method
US7407597 *Sep 14, 2006Aug 5, 2008Lam Research CorporationLine end shortening reduction during etch
US7491343Jan 10, 2007Feb 17, 2009Lam Research CorporationLine end shortening reduction during etch
US7589024 *Nov 9, 2006Sep 15, 2009Elpida Memory, Inc.Process for producing semiconductor integrated circuit device
US8476168Jan 26, 2011Jul 2, 2013International Business Machines CorporationNon-conformal hardmask deposition for through silicon etch
US8668805Jun 30, 2008Mar 11, 2014Lam Research CorporationLine end shortening reduction during etch
US20060024909 *Jul 27, 2004Feb 2, 2006Manoj MehrotraShallow trench isolation method
US20070111373 *Nov 9, 2006May 17, 2007Elpida Memory, Inc.Process for producing semiconductor integrated circuit device
US20080087637 *Sep 14, 2006Apr 17, 2008Lam Research CorporationLine end shortening reduction during etch
US20080087639 *Jan 10, 2007Apr 17, 2008Lam Research CorporationLine end shortening reduction during etch
US20080268211 *Jun 30, 2008Oct 30, 2008Lam Research CorporationLine end shortening reduction during etch
Classifications
U.S. Classification438/286, 257/E21.259, 257/E21.035, 257/E21.038, 438/287, 257/E21.232, 257/E21.037, 257/E21.546, 257/E21.234, 257/E21.235, 257/E21.027
International ClassificationH01L21/3065, H01L21/302, H01L21/027, H01L21/762, H01L21/336, H01L21/76, H01L21/308, H01L21/033, H01L21/312, H01L21/306
Cooperative ClassificationH01L21/312, H01L21/0335, H01L21/0274, H01L21/76224, H01L21/3085, H01L21/0337, H01L21/0332, H01L21/3086, H01L21/3081, H01L21/02126, H01L21/02274, H01L21/02118
European ClassificationH01L21/308D4, H01L21/033D, H01L21/308B, H01L21/308D2, H01L21/027B6B, H01L21/033F4, H01L21/762C, H01L21/312, H01L21/033F2
Legal Events
DateCodeEventDescription
Apr 9, 2001ASAssignment
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARK, WON SOUNG;KONG, PHIL GOO;LEE, HO SEOK;AND OTHERS;REEL/FRAME:011671/0731
Effective date: 20010315
Jan 6, 2006FPAYFee payment
Year of fee payment: 4
Jan 7, 2010FPAYFee payment
Year of fee payment: 8
Mar 7, 2014REMIMaintenance fee reminder mailed
Jul 30, 2014LAPSLapse for failure to pay maintenance fees
Sep 16, 2014FPExpired due to failure to pay maintenance fee
Effective date: 20140730