US 20010018759 A1 Abstract A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
Claims(21) 1. A method for routing nets in an integrated circuit design, said method comprising the following steps:
a. Dividing the integrated circuit design with lines in a first direction and lines in a second direction; b. forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction; c. routing nets as a function of said routing graph with parallel processors operating substantially simultaneously; d. determining the relative wire congestion among different areas in the integrated circuit design; e. rerouting nets passing though areas with a relatively high wire congestion. 2. The method of claim 1 3. The method of claim 1 ^{k }predetermined units apart. 4. The method of claim 3 5. The method of claim 3 f. dividing the integrated circuit design with additional lines in the first direction such that lines in the first direction are spaced 2
^{k−1 }units apart; g. forming a second routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction;
h. rerouting nets as a function of said routing graph with parallel processors operating substantially simultaneously.
6. The method of claim 5 7. The method of claim 6 8. The method of claim 7 9. The method of claim 8 10. The method of claim 8 11. A apparatus for routing nets in an integrated circuit design, said apparatus comprising:
a. means for dividing the integrated circuit design with lines in a first direction and lines in a second direction; b. means for forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction; c. means for routing nets as a function of said routing graph with parallel processors operating substantially simultaneously; d. means for determining the relative wire congestion among different areas in the integrated circuit design; e. means for rerouting nets passing though areas with a relatively high wire congestion. 12. The apparatus of claim 1 13. The apparatus of claim 1 ^{k }predetermined units apart. 14. The apparatus of claim 3 15. The apparatus of claim 3 f. means for dividing the integrated circuit design with additional lines in the first direction such that lines in the first direction are spaced 2
^{k−1 }units apart; g. means for forming a second routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction;
h. means for rerouting nets as a function of said routing graph with parallel processors operating substantially simultaneously.
16. The apparatus of claim 5 17. The apparatus of claim 6 18. The apparatus of claim 7 19. The apparatus of claim 8 20. The apparatus of claim 8 21. A computer encoded storage medium with instructions thereon for routing nets in an integrated circuit design, said storage medium comprising:
a. a computer encoded instruction for dividing the integrated circuit design with lines in a first direction and lines in a second direction; b. a computer encoded instruction for forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction; c. a computer encoded instruction for routing nets as a function of said routing graph with parallel processors operating substantially simultaneously; d. a computer encoded instruction for determining the relative wire congestion among different areas in the integrated circuit design; e. a computer encoded instruction for rerouting nets passing though areas with a relatively high wire congestion. Description [0001] 1. Field of the Invention [0002] The present invention generally relates to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of processing high fanout nets for purposes of routing integrated circuit chips. [0003] 2. Description of Related Art [0004] An integrated circuit chip (hereafter referred to as an “IC” or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells. [0005] A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. [0006] A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected. A netlist is a list of nets for a chip. [0007] Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers. [0008] The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. [0009] During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design. [0010] Currently, the minimum geometric feature size of a component is on the order of 0.2 microns. However, it is expected that the feature size can be reduced to 0.1 micron within the next few years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements. [0011] Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. [0012] The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality. [0013] An exemplary integrated circuit chip is illustrated in FIG. 1 and generally designated by the reference numeral [0014] The integrated circuit [0015] The cells [0016] The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction. [0017] 1. Partitioning. [0018] A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore it is normally partitioned by grouping the components into blocks such as subcircuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks. [0019] The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks. [0020] 2. Floor planning and placement. [0021] This step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor planning is a critical step as it sets up the ground work for a good layout. Floor planning is discussed in U.S. Pat. No. 4,918,614, entitled “Hierarchical Floorplanner” issued to Modarres on Apr. 17, 1990. Said patent is incorporated herein as though set forth in full. During placement, the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications. One particular placement process is described in U.S. Patent Application of R. Scepanovic et al., entitled “Advanced Modular Cell Placement System With Neighborhood System Driven Optimization”, Ser. No. 08/647,605, filed Jun. 28, 1996. Said patent application is incorporated herein by this reference as though set forth in full. [0022] 3. Routing. [0023] The objective of the routing phase is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel. [0024] Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space. [0025] Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes the exact channel routing of wires. [0026] 4. Compaction. [0027] Compaction is the task of compressing the layout in all directions such that the total area is reduced. By making the chips smaller, wire lengths are reduced which in turn reduces the signal delay between components of the circuit. At the same time a smaller area enables more chips to be produced on a wafer which in turn reduces the cost of manufacturing. Compaction must ensure that no rules regarding the design and fabrication process are violated. [0028] Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer (film) of light-sensitive material, such as photoresist. Using a patterned mask or reticle, the wafer is exposed to projected light, typically actinic light, which manifests a photochemical effect on the photoresist, which is subsequently chemically etched, leaving a pattern of photoresist “lines” on the wafer corresponding to the pattern on the mask. [0029] A “wafer” is a thin piece of semiconductor material from which semiconductor chips are made. The four basic operations utilized to fabricate wafers include (1) layering, (2) patterning, (3) doping and (4) heat treatments. [0030] The layering operation adds thin layers of material, including insulators, semiconductors, and conductors, to a wafer surface. During the layering operation, layers are either grown or deposited. Oxidation involves growing a silicon dioxide (an insulator) layer on a silicon wafer. Deposition techniques include, for example, chemical vapor deposition, evaporation, and sputtering. Semiconductors are generally deposited by chemical vapor deposition, while conductors are generally deposited with evaporation or sputtering. [0031] Patterning involves the removal of selected portions of surface layers. After material is removed, the wafer surface has a pattern. Such a pattern may include the wires that connect cells. Where the present invention is utilized, the wiring patterns will be formed as a function of the output of the present invention. The wiring patterns will be a material removed may form a hole or an island. The process of patterning is also known to those skilled in the relevant art as microlithography, photolithography, photomasking and masking. The patterning operation serves to create parts of the semiconductor device on the wafer surface in the dimensions required by the circuit design and to locate the parts in their proper location on the wafer surface. [0032] Doping involves implanting dopants in the surface of the wafer through openings in the layers to create the n-type and p-type pockets needed to form the N-P junctions for operation of discrete elements such as transistors and diodes. Doping is generally achieved with thermal diffusion (wafer is heated and exposed to the desired dopant) and ion implantation (dopant atoms are ionized, accelerated to high velocities and implanted into the wafer surface). [0033] Described herein is a method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion. [0034] The present invention also provides for an apparatus for constructing the routing of an IC design. The apparatus includes at least one processor and memory connected to the processor. The memory may be any machine-readable storage medium containing the instructions for the processor to perform the steps of the present invention. [0035] These and other aspects, features, and advantages of the present invention will be apparent to those persons having ordinary skilled in the art to which the present invention relates from the foregoing description and the accompanying drawings. [0036]FIG. 1 is a simplified illustration of an integrated circuit chip on semiconducting material; [0037]FIG. 2 is a flowchart illustrating the Parallel Simultaneous Global and Detailed Routing System; [0038]FIG. 3 is a flowchart illustrating the Parallel Steiner Tree Routing system; [0039]FIG. 4A shows an elementary pair of pins; [0040]FIG. 4B shows a quasi-elementary pair of pins; [0041]FIG. 4C shows a quasi-elementary pair of pins; [0042]FIG. 4D shows a pair of pins which is neither elementary nor quasi-elementary; [0043]FIG. 4E shows an elementary pair of pins; [0044]FIG. 4F shows a quasi-elementary pair of pins; [0045]FIG. 5 shows a 10-pin net; [0046]FIG. 6 shows the 10-pin net with horizontal and vertical lines drawn through the pins; [0047]FIG. 7A shows the pins of the 10-pin net after the relative y-coordinates and x-coordinates are set; [0048]FIG. 7B shows the pins of the 10-pin net after the x-coordinates are halved; [0049]FIG. 7C shows the pins of the 10-pin net after the y-coordinates are halved; [0050]FIG. 7D shows the pins of the 10-pin net after the x-coordinates are again halved; [0051]FIG. 7E shows the pins of the 10-pin net after the y-coordinates are again halved; [0052]FIG. 7F shows the pins of the 10-pin net after the x-coordinates are again halved; [0053]FIG. 7G shows the pins of the 10-pin net after the y-coordinates are again halved; [0054]FIG. 7H shows the pins of the 10-pin net after the x-coordinates are again halved; [0055]FIG. 8A shows the two pins remaining after net compression, which comprise an elementary pair; [0056]FIG. 8B shows the first expansion step; [0057]FIG. 8C shows the next expansion step, wherein the net has been expanded in the y-direction; [0058]FIG. 8D shows the next expansion step, wherein the net has been expanded again in the x-direction; [0059]FIG. 8E shows the next expansion step, wherein the net has been expanded in the y-direction; [0060]FIG. 8F shows the next expansion step, wherein the net has been expanded in the x-direction; [0061]FIG. 8G shows the next expansion step, wherein the net has been expanded in the y-direction; [0062]FIG. 8H shows the results of the final expansion step; [0063]FIG. 9 shows the graph from FIG. 8H on a rectangular grid; [0064]FIG. 10 shows the resulting planar graph; [0065]FIG. 11A shows the planar graph, which divides the plane into 10 regions; [0066]FIG. 11B shows the planar graph after the longest edge is removed; [0067]FIG. 11C shows the planar graph after the next longest edge is removed; [0068]FIG. 11D shows the resulting spanning tree; [0069]FIG. 12 shows the spanning tree directed away from a root pin; [0070]FIG. 13 shows the spanning tree directed away from the root pin, wherein the pins are numbered; [0071]FIG. 14 shows a net wherein each pin has been assigned relative coordinates; [0072]FIG. 15 shows a hierarchy tree; [0073]FIG. 16 shows the placement of the root vertex on a grid. [0074]FIG. 17 shows four pins with intersecting edges. [0075]FIG. 18 is a flowchart that describes the Course Global Routing Process; [0076]FIG. 19 is a routing graph; [0077]FIG. 20 is a flowchart which depicts the steps in the Construction of a Spanning Hypertree process; [0078]FIG. 21A depicts a two-pin basis element; [0079]FIG. 21B depicts a three-pin basis element; [0080]FIG. 21C depicts a four-pin basis element; [0081]FIG. 22 is a flowchart that describes the steps of the Hierarchical Global Routing Descend process; [0082]FIG. 23A is a routing graph for the previous level; [0083]FIG. 23B is a routing graph for the current level; [0084]FIG. 24 is a flowchart that depicts the steps of the Local Optimization of the Global Routing process; [0085]FIG. 25 is a flowchart that depicts the parallel routing locking mechanism; [0086]FIG. 26 depicts an apparatus constituting the present invention having a single processor; and [0087]FIG. 27 depicts an apparatus constituting the present invention having multiple processors. [0088] Described in this Section I (“Method and Apparatus for Parallel Simultaneous Global and Detailed Routing”) is a system for routing an integrated circuit in parallel. The system takes into account congestion and routes nets so as to avoid congested areas. The system also minimizes process defects by spreading wires as evenly as is possible. This routing system utilizes several steps as are shown in FIG. 2. FIG. 2 is a flow chart [0089] As an initializing step [0090] The first operational step [0091] The second operational step [0092] The third operational step is to reroute nets passing through congested areas [0093] As a fourth operational step, we redo the routing in optimizing meshes [0094] If k is equal to zero 7, we proceeded to distribute evenly vertical lines between the first and third layers of the IC design [0095] Next, we perform detailed routing [0096] Also described herein is a Method and Apparatus for a Parallel Routing Locking Mechanism. This is discussed more fully in Section IX below. Since an object of the present invention is to allow the parallel routing of nets, this mechanism can be utilized throughout the system as a memory-efficient means of parallel processing the routing. [0097] A class of paths termed Steiner trees has been developed as one method that is used in the physical design of integrated circuits to efficiently route multi-terminal interconnective nets. The utilization of Steiner tree routing algorithms is well known to those skilled in the art of IC design. It is described, for example, in (1) the U.S. Application for Letters Patent, entitled “Parallel Processor Implementation of Net Routing”, filed by Ranko Scepanovic, Edwin Jones and Alexander E. Andreev, on Feb. 11, 1997, (2) U.S. Pat. No. 5,615,128, issued on Mar. 25, 1997, to Ranko Scepanovic and Cheng-Liang Ding, entitled “Towards optimal steiner tree routing in the presence of rectilinear obstacles, and (3) U.S. Pat. No. 5,587,923, issued on Dec. 24, 1996, to Deborah C. Wang, entitled “Method for estimating routability and congestion in a cell placement for integrated circuit chip. Applicants incorporate said patent application and said two issued patents herein by this reference as though each were set forth herein in full. [0098] A Steiner tree for n demand points is a tree (a connected graph with no closed paths) made up of lines that interconnect all n demand points of the tree. A Steiner tree, unlike for example a spanning tree, may also contain additional vertices that are not among the n demand points, in order to achieve a shorter pathway among these n demand points. A rectilinear Steiner tree (RST) of n demand points may be characterized as a tree composed only of orthogonal line segments (typically termed edges) that interconnect all n demand points (which are located at vertices). A rectilinear Steiner tree (RST) is confined to an underlying grid type graph which has traditionally been defined as the intersections of orthogonal lines (usually horizontally and vertically oriented) that are drawn through the n demand points. A graph may be considered a pair of sets G=(V, E), where V is a set of vertices or points, and E is a set of edges between the vertices. Finding a minimum rectilinear Steiner tree (MRST) can be characterized as finding a Steiner tree whose edges are constrained to rectilinear shapes that in combination connect all of the desired points in the shortest path available. [0099] Because there are a large number of pins to connect and the complex nature of the connections required, a proper placement of the cells and the routing of the wires are critical for a successful implementation of a chip. Generally, as mentioned above, nets comprise 2 or 3 pins. However, a small number of nets for a particular IC may have many pins. Due to the nonlinear complexity of routing algorithms (in particular Steiner tree routing algorithms), it is very expensive computationally to apply them directly to high fanout nets. Applying the same algorithms on a number of much smaller subnets is considerably less expensive. The purpose of the present invention is to provide a method and apparatus by which high fanout nets can be partitioned into smaller subnets such that the subnets can be routed separately and in parallel. [0100] In accordance with the Parallel Steiner Tree Routing method described in this Section II, a high fanout net is partitioned into subnets so that the subnets can be routed separately in parallel. For a given net we create a set of subnets that satisfy the following conditions: (1) The union of the subnets is the whole net; (2) the number of pins in each subnet is bounded by a given number; and (3) the sum of half-perimeters of the subnets' bounding boxes is as small as possible. Partitioning of a netlist in accordance with the Parallel Steiner Tree Routing method described herein can be parallelized by splitting high fanouts nets among different processors. Steiner tree routing algorithms can then be applied, again in parallel, to the newly obtained netlist that contains no high fanout nets. See FIG. 2, element [0101]FIG. 3 consists of a flow chart [0102] As discussed above, the first operational step in the Parallel Steiner Tree Routing method is to identify all elementary pairs of pins in the net. The details of this step are discussed below. [0103] 1. Concepts of Elementary and Quasi-Elementary Pairs of Pins. [0104] The purpose of the Parallel Steiner Tree Routing method is to partition a net into subnets satisfying the above conditions. The key to the Parallel Steiner Tree Routing method is the concept of an “elementary” pair of pins. A pair of pins is said to be elementary if there are no other pins within or on its bounding box. [0105] The concept of a “quasi-elementary” pair of pins is similar to the concept of an elementary pair of pins. A quasi-elementary pair of pins has no pins inside the bounding box, but has one or more pins, other than the pins comprising the subject pair, on the bounding box. [0106]FIG. 4A shows an elementary pair of pins. In FIG. 4A, a pin [0107] In FIG. 4B, a pin [0108] In FIG. 4C, a pin [0109] In FIG. 4D, a pin [0110] In FIG. 4E, a pin [0111] Finally, in FIG. 4F, a pin [0112] 2. Lines Passing Through Pins in the Net. [0113]FIG. 5 shows a net comprising 10 pins. Although the Parallel Steiner Tree Routing method is generally applied to nets having greater numbers of pins, a 10-pin net is sufficient for illustration here. As shown in FIG. 5, the 10 pins are numbered [0114] As is shown in FIG. 6, we draw horizontal and vertical lines through each pin. The vertical lines are numbered
[0115] It should be noted that pins [0116] The ordinal number of the horizontal line passing through a pin is considered its relative y-coordinate and the ordinal number of the vertical line passing through a pin is its relative x-coordinate. To illustrate, FIG. 7A shows the pins of the 10-pin net discussed above after the relative y-coordinates and x-coordinates are set. The pins and their respective relative x- and y-coordinates are shown in Table 7A below.
[0117]FIG. 7B shows the pins of the 10-pin net after the x-coordinates are halved. The x-coordinate is set to the absolute value of half of the original x-coordinate. Therefore, if the first x-coordinate is 5, for example, the new x-coordinate is 2. If the first x-coordinate is 4, for example, the new x-coordinate is also 2. Table 7B lists the new positions of the pins as shown in FIG. 7B.
[0118]FIG. 7C shows the pins of the 10-pin net after the y-coordinates are halved. Again, each pin which previously had an odd y-coordinate is set to the absolute value of half of its original y-coordinate. The new positions are listed in Table 7C below.
[0119]FIG. 7D shows the pins of the 10-pin net after the x-coordinates are again halved. Previously, pin
[0120]FIG. 7E shows the pins of the 10-pin net after the y-coordinates are again halved. As a result of this step, pins
[0121]FIG. 7F shows the pins of the 10-pin net after the x-coordinates are again halved. As a result of this step, pins
[0122]FIG. 7G shows the pins of the 10-pin net after the y-coordinates are again halved. As a result of this step, pins
[0123]FIG. 7H shows the pins of the 10-pin net after the x-coordinates are again halved. As a result of this last step, pins [0124] After the stage where only two pins remain is achieved, the process then reverses back through the hierarchy. At each step, the pins are evaluated to determine the existence of additional elementary and quasi-elementary pairs. This process ends at the lowest level, producing the list of elementary pairs. With respect to a high fanout net, this process is considerably faster than checking all possible pairs for elementariness. [0125]FIG. 8A shows pins [0126]FIG. 8B shows the first expansion step. The net has been expanded in the x-direction. After expansion, we have pins [0127] The pins from prior elementary and quasi-elementary pairs are first checked to determine if they remain elementary and/or quasi-elementary. In the previous step, pins [0128] We also consider pins which had comprised a single pin in the previous level, but have divided. When a single pin divides, a new elementary pair is formed. Therefore, we check between pins [0129] Table 8B below sets forth in the first column the elementary and quasi-elementary pairs as reflected by FIG. 8B, and for each such pair identifies whether the pair is elementary (“E”) or quasi-elementary (“Q”), the pins forming the pair, and the former pin or pair from which the pair derives.
[0130]FIG. 8C shows the next expansion step, wherein the net has been expanded in the y-direction. Here, pin [0131] Checking between pins which had comprised a single pin in the previous level reveals elementary pair
[0132]FIG. 8D shows the next expansion step, wherein the net has been expanded again in the x-direction. Table 8D below sets forth in the first column the elementary and quasi-elementary pairs present after this step, and for each such pair identifies whether the pair is elementary (“E”) or quasi-elementary (“Q”), the pins forming the pair, and the former pin or pair from which the pair derives. After expansion, each of the pins have the coordinates shown in Table 7E above.
[0133] It should be noted that pair [0134]FIG. 8E shows the next expansion step, wherein the net has been expanded in the y-direction. Table 8E below sets forth in the first column the elementary and quasi-elementary pairs present after this step, and for each such pair identifies whether the pair is elementary (“E”) or quasi-elementary (“Q”), the pins forming the pair, and the former pin or pair from which the pair derives. After expansion, each of the pins have the coordinates shown in Table 7D above.
[0135] It should be noted that the status of pair [0136]FIG. 8F shows the next expansion step, wherein the net has been expanded in the x-direction. Table 8F below sets forth in the first column the elementary and quasi-elementary pairs present after this step, and for each such pair identifies whether the pair is elementary (“E”) or quasi-elementary (“Q”), the pins forming the pair, and the former pin or pair from which the pair derives. After expansion, each of the pins have the coordinates shown in Table 7C above.
[0137] It should be noted that, because pin [0138]FIG. 8G shows the next expansion step, wherein the net has been expanded in the y-direction. Table 8G below sets forth in the first column the elementary and quasi-elementary pairs present after this step, and for each such pair identifies whether the pair is elementary (“E”) or quasi-elementary (“Q”), the pins forming the pair, and the former pin or pair from which the pair derives. After expansion, each of the pins have the coordinates shown in Table 7B above.
[0139] It should be noted that pairs [0140] In the previous expansion steps, both elementary and quasi-elementary pairs were retained for consideration. However, in the next and final expansion step, only elementary pairs are retained for further consideration. As we have done in the expansion steps before, after expansion we check both elementary and quasi-elementary pairs. However, if an elementary pair becomes quasi-elementary or a quasi-elementary pair remains quasi-elementary, we consider the pair no further. Table 8H below shows the results after the final expansion in the x-direction and pair checking is completed. [0141] Therefore, in this final expansion step, we first check all elementary and quasi-elementary pairs for elementary pairs (but not quasi-elementary pairs). In our example, we do not have any pins which have just divided. However, if we did, they would also be checked, just as in the prior expansion steps.
[0142] It should be noted that pairs [0143] The next step in our process is to create a planar graph from the graph shown in FIG. 8H. From the graph in FIG. 8H, we make a planar graph by dropping the longer line where two lines intersect. [0144]FIG. 9 shows the graph from FIG. 8H on a rectangular grid. For purposes of our discussion herein, each rectangle is identified as R(i,j), with the value i being the column number and the value j being the row number. In FIG. 9, i equals 1 through 8, with 1 representing the column furthest left, 8 representing the column furthest right and the other columns being numbered sequentially. Likewise, in FIG. 9, j equals 1 through 8, with 1 representing the bottom row, 8 representing the top row, and the other rows being numbered sequentially. [0145] We start at R(1,1) and move right along the bottom row to R(8,1), checking each rectangle as we go. None of the rectangles in the bottom row have lines intersecting. We then check the next row up starting at R(1,2) and move right. At R(4,2) we come to the intersection between lines representing pairs [0146] We then continue checking rectangles for line intersections. At the next rectangle, R(5,2), lines [0147] We then check the next row, beginning with R(1,3). At R(5,3), lines [0148] The planar graph divides the plane into regions. FIG. 11A shows the planar graph, which divides the plane into 10 regions (identified as regions A through J). Each edge (line) of the planar graph is on the boundary of two regions, which we call neighboring regions. We remove the largest edge between neighboring regions, making these two regions into one. Here, for purposes of our example, the longest edge is
[0149] For each pin in our net, we create a neighborhood of the pin that has a given radius D. The typical value for parameter D is 2 or 3. To do this, we first identify all vertices that are connected to the chosen pin with one edge. We then do the same step for each of these vertices, and so on. By repeating this step D times, we get the collection of all vertices in our tree that are connected to the chosen pin with at most D edges. This is the pin's neighborhood. [0150] For example, referring to FIG. 11D, assume a parameter D equal to 2. For pin [0151] Next we find each subtree of this neighborhood that (1) passes through the center pin and (2) has no pins not belonging to the subtree that are located within the bounding box of the subtree. Note, for example, that there are three edges coming out of pin [0152] Group A: { [0153] Group B: { [0154] Group C: { [0155] Now, any pin [0156] Let A equal the number of elements in Group A, B equal the number of elements in Group B and C equal the number of elements in Group C. Then, the number of neighborhood subtrees from pin [0157] We then check each of these 29 neighborhood subtrees to determine if it has a pin which does not belong to the subtree within its bounding box. If so, the subtree is eliminated from consideration. [0158] We repeat this process for all pin neighborhoods. The resulting subtrees for all the pins in the spanning tree are “basis elements”. [0159] The next major operational step is to construct a connected covering for the net. We consider one pin a root, and orient all edges to point away from it. FIG. 12 shows our 10-pin spanning tree with pin [0160] For a given pin, its descendants are all pins that can be obtained by going from it along the edges in the direction specified by the edge orientation. For example, all pins other than the root itself are the root's descendants. With respect to FIG. 13, for example, pin [0161] We define the complexity of a basis element as the half-perimeter of its bounding box. We calculate the complexity for each basis element. [0162] Next, we calculate the complexity of other subtrees. Each subtree has a top pin, i.e., the pin in the subtree with the highest assigned number. For example, the top pin of the subtree consisting of edges [0163] We go through all pins in the numeration order and calculate the complexity of each subtree having this pin as its top pin. This is done by induction on the pin number and the number of edges coming out of the top pin and belonging in the subtree. Namely, for a given subtree s generated by n edges coming out of the pin numbered p, we consider all basis elements having p as their top pin and that are contained in s. For one such basis element b, we already have calculated the complexity of each piece of s−b, because each such piece either has its top pin with a number less then p, or its top pin is also p, but it has less than n edges inside. So, we add the complexities of all the pieces and the complexity of b (which is the half-perimeter of its bounding box). Of all basis elements, we choose the one that produces the smallest complexity and we remember both the complexity calculated and the identity of that basis element. [0164] To produce the covering, we start with the root. We choose and put on a list the basis element b remembered for the root and the subtree that is spanned by all edges coming out of the root. Then, for each pin in b, we add to the list the basis element remembered for that pin and spanned by the edges not in b, etc. The resulting list is the required covering. [0165] Since every subnet in the covering is a basis element, their size is controlled by the parameter D from the step of creating pin neighborhoods. Minimizing the complexity minimizes the sum of the half-perimeters of the subnets. [0166] The netlist is then adjusted to reflect the breakdown of the net into the subnets such that each subnet is treated as a net in the netlist. The subnets can now be processed in parallel. [0167] One of the major reasons for net partitioning is to parallelize routing algorithms (such as the Steiner Tree routing algorithms) for high fanout nets. Due to the nonlinear complexity of Steiner Tree routing algorithms, it is very expensive to apply them directly on a high fanout net. Applying the same algorithms on a number of much smaller subnets is considerably less expensive computationally. [0168] The partitioning method described in Section II above (“Method and Apparatus for Parallel Steiner Tree Routing”) partitions high fanout nets into smaller subnets so that each subnet can be routed separately and in parallel. However, the first and second operational steps of the Parallel Steiner Tree Routing method described in Section II above (i.e., the operational steps of determining elementary pairs of pins and creating a planer graph) may require more computer memory than is available in the particular routing apparatus used. The Memory-Saving Parallel Steiner Tree Routing method described in this Section III offers a much more memory efficient replacement for determining elementary pairs of pins. Preferably, the memory-saving method described in this Section III is utilized for very high fanout nets (e.g., 500 pins or more) and the method described in Section II above is utilized with respect to smaller high fanout nets (e.g. 5, 6, 7, 8, 9, or 10 to 499 pin nets). See FIG. 2, element [0169] Partitioning a netlist by using the memory-saving method can be easily parallelized by splitting nets with very high fanouts among processors. Steiner tree routing algorithms can then be applied, again in parallel, to the newly obtained larger netlist that contains no high fanout nets. [0170] As with the Parallel Steiner Tree Routing method described above in Section II, the Memory-Saving Parallel Steiner Tree Routing method starts with passing horizontal and vertical lines though each pin in the particular net to be processed. This results in a division of the plane into a coarse set of rectangles. The ordinal number of the horizontal line passing though a pin is its relative y-coordinate and the ordinal number of the vertical line passing through it is its relative x-coordinate. This is accomplished in the same manner as is discussed above in Section II with respect to drawings [0171] For each pin in the net a “combined coordinate” is then calculated. A combined coordinate is calculated by the following steps: [0172] a. Write the relative coordinates of the pin (x and y) as binary numbers. [0173] b. Write a binary combined coordinate for the pin (z) by alternatively taking digits from the binary x and the binary y. [0174] For example, suppose a pin has a relative x-coordinate of 5 and a relative y-coordinate of 3. The relative coordinates written as binary would be 101 for the x-coordinate and 011 for the y-coordinate. The combined coordinate z would be 100111. Note that the binary x-coordinate can be obtained from the combined coordinate by writing every other digit of z starting from the first one. The y-coordinate can be derived by writing every other digit of z starting from the second one. [0175]FIG. 14 provides an example. In FIG. 14, the pins of an eight-pin net (
[0176] After the combined coordinates are calculated, the pins of the net are sorted in ascending order. For each two pins appearing consecutively on the sorted list, a “level of equality” is calculated. The “level of equality” for a pair of pins is the ordinal number of the digit after which the two combined coordinates coincide, viewed from right to left. For example, if the first combined coordinate on the list is 8 (binary 1000) and the second combined coordinate on the list is 9 (binary 1001), the two combined coordinates coincide from the second digit on, viewed right to left. Therefore, the level of equality between the two pins is two. [0177] In Table 15A below, the pins of the eight-pin net from FIG. 14 have been sorted. Also listed is the combined coordinate of each pin in the exemplary net. In addition, the level of equality between consecutive pins on the sorted list is also shown.
[0178] The next step in the process is to create a “hierarchy tree.” To create the hierarchy tree we first add all the pins as vertices to the hierarchy tree. Their level is 0 and they have no descendants. This is shown in FIG. 15A. [0179] To create the next level of hierarchy, the process proceeds through the list and compares the level of equality of a current pin and the next pin against the level of equality of its neighbors to determine whether the current pin's level of equality with the following pin is smaller than the level of equality of its direct neighbors (both up and down). If this is not satisfied, the process moves on to the next pin. Otherwise, the process makes a new tree vertex. The new vertex's level is the level of equality of the pair consisting of the current pin and the one after it. The two pins are also the descendants of the new vertex. For the vertex's combined coordinate, the current pin's combined coordinate is used. The current pin and the one after it are removed from the list, the new vertex is inserted in these places, and the levels of equality are recalculated. [0180] For example, in the eight-pin net discussed above, the level of equality of pins
[0181] The resulting hierarchy tree is depicted by FIG. 15. Pin [0182] Once the hierarchy tree is completed, we expand from the root of the tree, similar to the expansion shown in FIGS. 8A to [0183] First, if an edge joins two pins such that both coordinates of the pins differ by less than 2, we do not remove the edge in spite of the other rules discussed directly below. [0184] Second, if more than 3 pins lie on a horizontal or a vertical edge, we remove it. Note that such an edge will necessarily be longer than 2 and the first rule will not apply here. [0185] Third, if for all possible combinations of descendants, the two edges intersect, and one is always larger that the other, we remove the larger one. This rule is exemplified by FIG. 17. In FIG. 17, four pins are shown, [0186] If an edge between a descendant of pin [0187] In order to identify candidates for removal in accordance with the third rule, we consider lines passing through rectangles at the current hierarchy level. For each elementary pair we draw a line connecting the two pins, obtaining a graph. For each rectangle we make a list of lines passing through it. Then for each rectangle having more than one line passing through it, we check for intersections. This method is considerably faster than checking each pair of lines for intersections. [0188] It may be beneficial to apply the above rules only under certain circumstances and not at all stages of the process. For example, if the Manhattan distance (rectilinear distance) between two pins in an edge is d, the edge intersects at most d+1 rectangles. We can start removing intersections at the previous level where the sum of the Manhattan distances for all the edges of the net is greater than 5 times the total number of edges for the net. For example, if we are in level 7 and this condition is met, we can return to level 8 and remove intersections. This way, the number of edges will not go over 30 times the number of pins, so the amount of memory required is more manageable. [0189] When this process is completed, we have a planer graph. We then treat this planer graph utilizing the third, fourth and fifth operational steps described in Section II. [0190] The purpose of the Course Global Routing method described in this Section IV is to permit global routing of the given netlist in parallel with the best quality possible. This method takes congestion into consideration and endeavors to route nets in such a way that they do not pass through congested areas, if possible. [0191] The result of this routing for each net will be a list of edges on a routing graph through which the net passes. This information will be later used by the hierarchical and detailed routers, which are described further below in other sections. [0192] At this point in the routing process, it can be assumed that there are no large nets in the netlist since the high fanout nets have been partitioned according to the methods described above in Sections II and III. [0193]FIG. 18 is a flowchart [0194] The first operational step [0195] As a second operational step [0196]FIG. 19 is an example of such a routing graph. Shown in FIG. 19 is the surface of an IC [0197] For each edge (i.e. the line connecting two adjacent points on the routing graph) we calculate a capacity. There are many ways in which to calculate the capacity of an edge, however, the capacity of an edge will generally be the capacity of the edge without blockages less any blockages. Where there is going to be more than one routing layer (which is generally the case) the capacity of each edge is calculated on that basis. Preferably, we calculate capacities of edges as follows: [0198] for each vertical edge, the capacity is the width of the corresponding halfchannel expressed in grids. [0199] for each horizontal edge going through the middle of the channel the capacity is the height of the corresponding tile expressed in grids. [0200] for each horizontal edge going through the middle of a column, the capacity is the height of the corresponding tile expressed in grids minus the number of active pins (a pin generally takes the space of about one grid) and minus the number of grids covered by the routing blocks. [0201] As the third operation step [0202] A vertex of the superforest is a collection of the vertices of the routing graph. An edge of the superforest is a pair of vertices. To make our superforest, we add a vertex for any set of tiles (generally two) representing the same pin. Note that these tiles do not need to be connected among themselves (as they all represent one pin) but only to other tiles. [0203] In the beginning the superforest has no edges, they will be created in the routing process. Each time an edge is created, we create a set of all least-penalty paths from one vertex of the edge to another. This set is called the envelope of the edge. [0204] We then create a net for which we will make a hypertree. For each vertex of the superforest we add a pin to our net. This pin will be located at the center of gravity of the tile of which the superforest vertex consists. Now we create the hypertree for this net using the process described below in Section V (“Method and Apparatus for Construction of a Spanning Hypertree”). [0205] As the next operational step [0206] As nets are routed, we replace the projected occupancies with the actual ones, i.e., if the net passes through this edge, we add 1 to its occupancy and subtract the projected occupancy relative to the particular net. For example, if the projected occupancy relative to a particular net was 0.25, we add 1 and subtract 0.25. The occupancies are also adjusted accordingly for other edges which are eliminated as a path for the net by virtue of the assignment. [0207] The penalty for passing through an edge will be a function of the quotient occupancy/capacity and of the length of the edge, for example we can use
[0208] This penalty function can vary although it is preferred that the penalty increase as a function of occupancy/capacity and that the penalty further increase as a function of length. For example, we could also calculate the penalty as follows:
[0209] Penalties are also adjusted to reflect the occupancy changes as nets are routed. [0210] As the fifth operational step in the Course Global Routing process, we now route in parallel. Steiner trees must be constructed for connecting sets of tiles on the routing graph. For two sets of tiles, we grow neighborhoods for each set of tiles until they intersect, marking the total penalty to get to each point in the neighborhood. Then, going backward, we choose the least-penalty path from one set to another. [0211] For three sets of tiles, we grow neighborhoods until they reach a point in another set. If there is a point in the intersection of all neighborhoods, we find the sum of the penalties to all three sets from that point. In other words, we find a point P for which that sum is minimal. We also make a minimal spanning tree (There are only three choices for the tree.). The edges of this tree are made as above in case there are two sets. If the sum of the penalties of the tree edges is less than the sum of penalties from P to the 3 sets, then the tree is the Steiner tree; otherwise it is the union of paths connecting P with the 3 sets. These paths are also obtained using neighborhoods. [0212] For four sets of tiles, we first consider the case where we have points rather then sets. We restrict ourselves to the situation where none of the points is inside the bounding box of the other three points. Then we have left, right, top and bottom points, that we shall call V [0213] For joining 4 sets we first consider the 4 centers of gravity of these sets. For them we find Steiner points and decide which points will be joined as above. Then we join the corresponding sets using the above method for joining two sets. [0214] For the routing of a net, the hyperedges of the hypertree belonging to the net are sorted in ascending order according to the half-perimeter of their bounding boxes. For each hyperedge we associate a routing rectangle which is a bounding box of the hyperedge expanded in all four directions by r times hp, where hp is the half-perimeter, and r is a parameter, typically ⅓. If the original bounding box intersects blocks or megacells, we expand this rectangle until it contains them. [0215] We start connecting the vertices of the superforest using the hypertree as a guide. This is done as follows. We start with the first hyperedge. For every vertex of the hyperedge inside the routing rectangle of this hyperedge we consider the corresponding superforest vertex (which is a set of tiles). We join these sets by a Steiner tree using the set connection method described above (note that the hyperedge has at most four vertices, so there will be at most four sets to be joined.) Then we consider the next hyperedge. For every vertex of the hyperedge inside the routing rectangle of this hyperedge we consider the corresponding superforest vertex. We find the intersection of the connected component of these vertices with the routing rectangle. We then find the intersection of the envelopes of all edges of the superforest belonging to the components and passing through the routing rectangle. They form the sets that need to be connected by a Steiner tree. For this we use the set connection methods described above. We repeat this process until we run out of hyperedges. Notice that after each step the connected components of the superforest correspond exactly to connected components of the part of the hypertree generated by the used hyperedges. Then, when we have addressed all of the hyperedges, the superforest will be connected since the hypertree is connected. From each of the envelopes we choose one of the least-penalty paths, and that creates our routing. [0216] Since we are updating the occupancies and the penalties of each edge of the routing graph that the net passes through, we need to make sure that while working in parallel we never need to adjust the same edge at the same time. The easiest way to do that is to make sure that the nets worked on simultaneously are not in the same area. In order to assure that we do as follows. [0217] For each net we calculate the two quotients: The length of net's bounding box divided by the length of the design, and the width of the net's bounding box divided by the width of the design. The larger of the two we term the net's characteristic. This roughly suggests how large a part of design needs to be in order to contain the net's bounding box. We order the nets in descending order according to this characteristic. The nets with the characteristic larger than ¼ we route sequentially. There will not be many such nets. Then we split the design into four parts, give different processors different parts and instruct them to route only the nets that are completely contained in the corresponding parts and have a characteristic that is larger than ⅛. Then we shift the parts to the right by a quarter of the design's length and follow the same operation. We then shift the parts from their original positions down by a quarter and repeat the routing procedure. Then we shift the parts from their original positions both down and to the right by a quarter and repeat the routing procedure. This way all nets with characteristics larger than ⅛ will be routed. [0218] Next we split the design into twice smaller parts, consider the nets of characteristic larger than {fraction (1/16)} and repeat the shifting process, moving the parts ⅛ instead of ¼. Note that now we can include more processors to speed up the routing process. We repeat this process a few times using smaller and smaller parts, and once we keep all the processors busy, we route all the remaining nets. [0219] We can then reroute nets passing through congested areas [0220] Making a Steiner tree for a given net, especially if congestion is taken into account, can be computationally very expensive for nets larger then 4 pins. Therefore, we split such a net into smaller subnets and use the subnets to guide the routing of the net. [0221] A collection of pins is a “hyperedge.” A connected covering of the net with hyperedges is called a spanning hypertree if it contains no cycles. By having no cycles we mean that the spanning hypertree forms a tree and that there are no closed loops within the tree. [0222] The purpose of the Construction of a Spanning Hypertree process described in this Section V is to create a spanning hypertree for a given net. FIG. 20 is a flowchart [0223] As a first initializing step [0224] a. Each hyperedge must have a size (number of pins) less than or equal to K and greater than 1. [0225] b. The bounding box of each hyperedge must contain no pins from the net that are not in the hyperedge. [0226] c. For hyperedges containing more than two pins, no pin in the hyperedge can be contained in the bounding box of the other pins of the hyperedge. [0227] d. The sum of the minimal lengths of Steiner trees of the hyperedge must be as small as possible. [0228] Condition “a” insures that the hyperedges will be sufficiently small. Conditions “b” and “c” insure that the pins not in the hyperedge will not interfere with the creation of the Steiner tree routing for each hyperedge. Condition “d” implies that the obtained routing will have minimal wire length possible. [0229] At this point, we can assume that the net has no more than 15 vertices, which will be guaranteed because the netlist will have already been processed by the Parallel Steiner Tree Routing method (described in Section II above) and the Memory-Saving Parallel Steiner Tree Routing method (described in Section III above). [0230] As the first operational step [0231] As the next operational step [0232] For four-pin basic elements we construct a quick Steiner tree to find the length. FIG. 21C shows a four-pin basic element, comprising pins [0233] As the third operational step [0234] Where a subnet has two pins, if it is a basis element, the complexity is already calculated; otherwise we set its complexity to infinity. [0235] Suppose that we have already calculated the complexity of all subsets having less than n pins, and that A is a subset having n pins. If A does not contain any basis elements, we set its complexity to infinity. If A is a basis element, we have the complexity calculated already. In the remaining case, we take a basis element B contained in A and a point x in B. The potential complexity of A is the sum of complexities of B and of A−BU{x}. Since A−B U {x} has less than n pins, we have already calculated its complexity. We vary all basis elements B in A, as well as for each B we vary all possible x. Then we take the minimal potential complexity of all these variations as the complexity of A, and we save on which B and which x it occurs. [0236] As the next operational step [0237] The purpose of the Hierarchical Global Routing Descend process described in this Section VI is to create, in a parallel fashion, a hierarchy of finer and finer global routings of the given netlist with the best quality possible. This process takes congestion into consideration and tries to route nets in such a way that they do not pass through congested areas if possible. [0238] As discussed above, the overall IC design is initially divided with horizontal and vertical lines. Vertical lines pass through the middle of columns and the middle of channels and they do not change. Horizontal lines are 2 [0239] The nets are initially routed using the Course Global Routing process described in Section IV above. The Hierarchical Global Routing Descend process described in this Section VI comprises a method to obtain a routing on the next level of the hierarchy using the routing on the previous level. [0240]FIG. 22 sets forth a flowchart that describes the steps in the Hierarchical Global Routing Descend process. For purposes of the Hierarchical Global Routing Descend process, we use the notions of the routing graph and the tilenet from the Course Global Routing process described in Section IV. We can assume that the routing has been done on a certain level, and we want to use it for the routing on the next level. [0241] As the first initializing step [0242] As the first operational step [0243] Given a net, we consider its routing on the previous level. To each vertical line will correspond a vertical line on the new level. We combine horizontal edges of the net into connected fragments. For each of these fragments we have a local task, i.e., we need to route the piece of the net inside the rectangle corresponding to the fragment on the current level. This can be described as follows. We number the half-channels of the design from left to right, and the horizontal lines from the bottom to the top. Each vertex of the routing graph lies in one half-channel, and on one horizontal lines, so it can be completely described with a pair of numbers (i, j), where i is the half-channel's number and j is the horizontal line's number. [0244] Corresponding to a vertex (i, j) from the previous level are two vertices on the current level, namely (i, 2j) and (i, 2j+1). An edge can be represented as a pair of vertices. The graph of a local task is a set of vertices (i, 0) and (i, 1) and a set of edges ((i−1, 0), (i, 0)), ((i−1, 1), (i, 1) and (i, 0), (i, 1)). Where i=0, we ignore edges containing i−1. A fragment will contain all the vertices (i, j) of the line where i [0245] We create a local net that will correspond to the fragment. A vertex (i, k), i [0246] a. There is a pin from our original net corresponding to this vertex. [0247] b. k=0 and the edge ((i, j), (i, j−1)) was in the net's routing on the previous level. [0248] c. k=1 and the edge ((i, j), (i, j+1)) was in the net's routing on the previous level. The local task consists of routing this local net inside the local task graph. [0249] As a second operational step
[0250] Similarly, the routing is given by α=(α
[0251] Penalty pen (i, α [0252] The penalty PEN(α) of the whole sequence α is calculated by the following formula.
[0253] We assume that pen(i, α
[0254]
[0255] The role of pen is to ensure that the routing has the smallest penalty, while the only role of functions Φ and Ψ is to rule out the impossible routings by setting their penalty to infinity. Our routing is going to be given by the sequence α that yields the minimal value of PEN(α). [0256] In order to find such a sequence, we define the function PEN(i, α)=
[0257] The above function gives the least possible penalty up to i [0258] We calculate all possible values of the function. Then we choose the value for the sequence that makes PEN (i [0259] The purpose of the Local Optimization of the Global Routing method described in this Section VII is to optimize the results of the global routing by rerouting parts of some nets on rectangular pieces of the routing graph. These re-routings, due to particulars of the area, can be done in a faster and better way than the general global routing, thereby providing better quality without increasing the run time dramatically. [0260] As discussed above, the design is initially divided with horizontal and vertical lines. Vertical lines pass through the middle of columns and the middle of channels and they do not change. Horizontal lines are 2 [0261] The nets are initially routed using the Course Global Routing method described above. Passing to the next level is done using the Hierarchical Global Routing Descend method. The optimizations discussed in this Section VII can be applied on each level, and can be accomplished utilizing parallel processing. [0262] The basic operational steps of the Local Optimization of the Global Routing method described herein are set forth in the flowchart [0263] As initializing step [0264] As a first operational step [0265] The segments of the strip are numbered from 1 to LN. The i [0266] The penalty for a vector is described with a function
[0267] We need to find the vector of minimal penalty. [0268] Let us consider a function
[0269] This function can be calculated by a recursive formula
[0270] Each time we calculate the left side, we write which element ν it is achieved on. Using which we calculate all values
[0271] It follows that,
[0272] We find u [0273] We start with k=LN−I and decrease k until it reaches 1. For each k we read u Φ [0274] The obtained vector (u [0275] As a second operational step [0276] In mathematical terms, the mesh is a set of pairs (i,j), where 0≦i≦n−1, where n is the number of half-channels, and 0≦j≦t−1, where t is the number of horizontal lines. This mesh is a part of the routing graph, and its starting point (0,0) corresponds to a point (I,J) on the routing graph. [0277] We consider all nets passing through the mesh. Notice that the nets are now routed, so we consider all the edges that connect the pins. For each such net we consider the connected components of its intersection with the mesh. These components are the subject of our optimization. We shall basically re-route all of them. We will make a new net, called the local net for each of the components and then route it. [0278] A vertex (i,k) in the component will be considered a pin in the local net if at least one of these conditions apply: [0279] a. It represents a real pin from the tilenet. [0280] b. k=0 and the edge ((I+i,J), (I+i,J−1)) is part of the routing of the tilenet. [0281] c. k=0 and the edge ((I+i, J+t−1), (l+i, J+t)) is part of the routing of the tilenet. [0282] By W [0283] Given a net w, we define mn (w,i) and mx (w,i) as follows. mn (w,i) is a minimum of f [0284] Now we can apply the general task algorithm to solve this problem and obtain the optimal routing of the local nets. Note that all horizontal lines can be done independently, hence this algorithm can be parallelized. [0285] Similarly we can do the optimizations in the vertical strips, basically swapping roles of horizontal and vertical edges above. On the routing graph, these would be two halfchannels wide. [0286] If the number of possible choices for f [0287] The purpose of the method and apparatus for the minimization of process defects described in this Section VIII is to optimize the results of the routing by spreading the wires as evenly as possible. The need for this arises in the production and fabrication of the IC designs. When a lot of wires are very close to each other, the machines that lay the wires on sometimes produce “spots” of metal, which cause the designs to be defective. [0288] As discussed above, the design is initially divided with horizontal and vertical lines. Vertical lines pass through the middle of columns and the middle of channels and they do not change. Horizontal lines are 2 [0289] The nets are initially routed using the Course Global Routing method described above in Section IV. Passing to the next level is done using the Hierarchical Global Routing Descend described above. The optimizations discussed in this Section VIII can be applied on each level and can be accomplished with parallel processing. [0290] For purposes of the Minimization of Process Defects method described herein, we use the notions of the routing graph, capacity, occupancy, penalty and the tilenet from the Course Global Routing method, the hierarchy from the Hierarchical Global Routing Descend method, and the general task from the Local Optimization of the Global Routing method. [0291] The optimization of the hierarchy is performed by adding a new expression to the penalty of each edge. The additional penalty adds to the overall penalty as a function of the actual or projected neighboring wires, thus increasing tendencies to distribute the routing evenly. This can be done while performing other optimizations from the Local Optimization of the Global Routing method, or after them on similar parts of the design. [0292] Consider the horizontal edges of the type [0293] j=0, 1, . . . , t−1. [0294] Let c [0295] The weight of this penalty can be decided through testing, starting with 1. This modification of the penalty can be done for vertical edges as well. [0296] For purposes of describing the use of the Minimization of Process Defects While Routing method, assume that the design has three layers. We attempt to distribute the vertical wires between the first and third layer before they are assigned precise horizontal positions. [0297] For purposes of our discussion, we restrict our attention to a particular half-channel. Horizontal grid lines containing beginnings or ends of vertical wires are marked. The half-channel is divided into little strips. The lines marked above become strips. Non-empty spaces (i.e. containing at least one horizontal grid line) between neighboring marked lines become strips. A strip corresponds to two vertices of the graph, one for first and one for third level. Each vertex is joined with an edge to vertices above and below it. A pair of vertices corresponding to the same strip is joined with an edge as well. The capacity of such edges is equal to 1 if the corresponding horizontal line is free on the second level, otherwise it is 0. [0298] This penalty is similar to the penalty for optimization on the hierarchy, except that it is multiplied for each strip by its height in grids. The penalty is considered infinite if the configuration leads to occupancy being higher than capacity, notably in case of edges joining the first and third level. [0299] The task here is very similar to the general task of the Local Optimization of the Global Routing method with t=2. Instead of a net we have a wire. We have the initial and the final strip for the wire. The solution is a sequence of edges that joins the initial and the final strip, which is obtained using methods described in connection with the Local Optimization of the Global Routing. [0300] The Minimization of Process Defects while Routing optimization can be used after detailed routing, in a horizontal or vertical strip. For the solution we permit short pieces of wires on a layer that are perpendicular to the general direction of the layer. We do not change the relative order of wires, we just attempt to continuously deform the routing. [0301] The local situation is described on a cross-cut, i.e. a set of vertices ν [0302] j=0, 1, . . . , t−1. [0303] For each such cross-cut there is a set of wires W [0304] describes the current values of wire on the grids. The possible values of wires on grids are given by a pair of functions
[0305] that satisfy the following conditions [0306] 1) bt [0307] 2) if a [0308] 3) if the wire x is fixed, then bt [0309] 4) if x is a block then bt [0310] Corresponding to each wire x on a cross-cut is a piece [0311] (i, bt [0312] The ordering of wires and blocks is not violated, and the fixed wires have to contain their pin. [0313] A given configuration is called “regular” if for any wire x intersecting the (i−1) [0314] bt [0315] Otherwise, its penalty is set to infinity. In regular cases the penalty is equal to the sum of penalties for all cross-cuts. [0316] The problem of finding the minimal penalty is solved using the general solution for linear equations. [0317] The purpose of the Method and Apparatus for Parallel Routing Locking Mechanism described in this Section IX is to enable data consistency while routing a large number of nets in parallel. As described above, for each horizontal strip of a design, we need to reroute all wires passing through it, and we want to do that in parallel. Since this information is stored on a per-net basis, we cannot allow different processors to simultaneously change the data belonging to one net, as this might corrupt the data. [0318] Accordingly, we assign to each processor a portion of the design on which to work and we spread the portions apart in order to avoid conflicts between parallel processors. However, there is no way to completely avoid such conflicts, as some nets have pins far away from each other, forcing the routing to pass through many portions of the design. [0319] Standard procedure would require a processor locking each net it works on, then unlocking the net as it is finished. This requires a multiple exclusion (“mutex”) lock structure for each net. Such a structure takes a significant amount of memory, especially on large designs. Taking so much memory just for locking is not feasible. [0320] A better approach is to have a single lock dealing with collisions for a group of nets. This is described in FIG. 25, which is a flowchart [0321] As an initializing step [0322] As a second operational step [0323] When a processor needs to work on i [0324] If it was changed, that means that another processor grabbed the same net while we waited for the lock, so we release the lock and wait again [0325] The character array takes 1 byte per member, so it requires 64 times less memory than the array of locks. Our smaller lock array is n times smaller than the full array, so varying n we can achieve various levels of memory-saving. The parameter n is chosen such that the required memory saving is obtained, while at the same time maintaining good run-time. Since a processor's waiting for a lock is expensive, we cannot take n to be too large. [0326] Each of the steps discussed above can be encoded for use in a general computer. Now referring to FIG. 26, a computing apparatus [0327] The memory [0328] Referring now to FIG. 27, an additional apparatus [0329] As discussed above, the specific algorithms and steps described herein, as well as the basic steps which such algorithms represent (even if they are replaced by different algorithms), are designed for implementation in a general purpose computer. Furthermore, each of the algorithms and steps described herein, as well as the basic steps represented by such algorithms, can be encoded on computer storage media such as CD ROMS, floppy disks, computer harddrives, and other magnetic, optical, other machine readable media, whether alone or in combination with one or more of the algorithms and steps described herein. [0330] Although the methods discussed herein have been described in detail with regard to the exemplary embodiments and drawings thereof, it should be apparent to those skilled in the art that various adaptations and modifications of the methods may be accomplished without departing from the spirit and the scope of the invention. Thus, by way of example and not of limitation, the methods are discussed as illustrated by the figures. Accordingly, the invention is not limited to the precise embodiment shown in the drawings and described in detail hereinabove. Referenced by
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