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Publication numberUS20010020857 A1
Publication typeApplication
Application numberUS 09/771,364
Publication dateSep 13, 2001
Filing dateJan 26, 2001
Priority dateJan 27, 2000
Also published asDE60128608D1, DE60128608T2, EP1120714A1, EP1120714B1, US6362671
Publication number09771364, 771364, US 2001/0020857 A1, US 2001/020857 A1, US 20010020857 A1, US 20010020857A1, US 2001020857 A1, US 2001020857A1, US-A1-20010020857, US-A1-2001020857, US2001/0020857A1, US2001/020857A1, US20010020857 A1, US20010020857A1, US2001020857 A1, US2001020857A1
InventorsAlexandre Malherbe, Fabrice Marinet, Alain Pomet
Original AssigneeStmicroelectronics S.A.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Device for the regeneration of a clock signal
US 20010020857 A1
Abstract
A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.
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Claims(15)
That which is claimed is:
1. A device for the regeneration of the clock signal of an external serial bus in an integrated circuit, comprising a stage for the acquisition of the period of the clock signal of the bus comprising a ring oscillator, counting means and means for the reading of a current phase, said ring oscillator giving, at output, n phases of a clock signal, a phase being applied as a reference clock signal to said counting means to count the number of entire reference clock signal periods between a first pulse and a second pulse of the bus, said means for the reading of the current phase being activated by the second pulse, said current phase corresponding to the measurement of the phase delay between the reference clock signal and this second pulse, the regeneration device furthermore comprising a regeneration stage comprising a ring oscillator and counting means identical to those of the acquisition stage, to reproduce the number of pulses counted and the current acquisition phase, and control a pulse generator giving a regenerated clock signal at output.
2. A device according to
claim 1
, wherein the acquisition stage comprises means of re-initializing the ring oscillator and counting means to synchronize the acquisition cycle on each pulse of the serial bus.
3. A device according to
claim 2
, wherein said re-initializing means activate a first control signal on reception of the first pulse, which activates the re-initialization and wherein they activate the second control signal to store the current phase and the number of pulses and then activate the re-initialization.
4. A device according to
claim 2
or
3
, wherein the regeneration stage comprises re-initialization means to re-initialize the ring oscillator and the counting means upon reception of a pulse from the serial bus or of the regenerated clock signal.
5. A device according to
claim 4
, wherein the regeneration stage comprises re-initializing means to re-initialize the ring oscillator and the counting means upon reception of the first pulse of the serial bus, and of each regenerated clock signal pulse.
6. A device according to one of the
claims 4
to
5
, wherein the current phase and the number of pulses given by the acquisition stage are read by the regeneration stage at each re-initialization.
7. A device according to any of the above claims, wherein the regeneration stage comprises means of selection of the current phase, comprising a phase-controlled gate of the ring oscillator, to select one phase among the n phases, corresponding to the current phase.
8. A device according to any of the above claims, wherein the counting means of the acquisition and regeneration stages comprise two counters, a first counter to count a fixed number of reference clock strokes, a second counter to count a variable number.
9. A device according to
claim 8
, wherein the second counter of the regeneration stage is used as a countdown unit, the passage to zero of the counter activating a control signal applied as an enabling signal for the selection of the current phase in the oscillator (RO2).
10. A device according to any of the above claims, wherein the acquisition stage is re-initialized at the expiry of a time period after the reception of each pulse of the serial bus, if no other pulse of the serial bus has followed in this time period.
11. A device according to
claim 10
, wherein this time period is given by the counting means of the acquisition stage, after the counting of a predetermined maximum number.
12. A device according to
claim 10
, wherein this time period is given by a watchdog reset at each new pulse of the serial bus.
13. A device according to any of the above claims, wherein the serial bus is a USB type bus.
14. An integrated circuit comprising a device according to any of the above claims.
15. A smart-card type carrier support comprising an integrated circuit according to
claim 14
.
Description
    FIELD OF THE INVENTION
  • [0001]
    The present invention relates to the field of electronics, and, more particularly, to a device for the regeneration of a clock signal. The device may be used for exchanging data via a universal serial bus (USB).
  • BACKGROUND OF THE INVENTION
  • [0002]
    According to a USB (user serial bus), the USB clock signal is not transmitted on the bus. Only some synchronization bits are sent at the beginning of transmission so that the devices connected to this bus can get synchronized for sending or receiving data on this bus.
  • [0003]
    In systems using a data transmission protocol of this kind, the integrated circuits usually and quite conventionally comprise a circuit for the generation of a synchronous clock signal based on a phase-locked loop and a quartz crystal.
  • SUMMARY OF THE INVENTION
  • [0004]
    The invention is concerned with a system comprising smart-card type portable carriers. Portable carriers of this kind cannot incorporate a prior art synchronized clock signal generation circuit because it is not possible to integrate either the quartz or the phase-locked loop therein, as these elements take up a great deal of space. The invention therefore relates to a device for the regeneration of the clock signal of the bus from a few external synchronization pulses, e.g., from at least two of them.
  • [0005]
    In the example of a USB serial bus, the regeneration of a USB clock signal must have high precision. The precision must be to within about 1%. According to the invention, to measure the clock signal period of the bus, a ring oscillator is used. This ring oscillator gives n phases of a clock signal. The invention uses one phase among these n phases as a reference clock signal applied to a counter. This is done to count the number of entire reference clock signal periods between two pulses of the bus. The state of the n phases is read to obtain the current phase whose leading edge coincides with the second pulse of the bus.
  • [0006]
    This corresponds to the measurement of the delay between the reference clock signal and the second pulse of the bus. Through these two measurements, it is possible to regenerate the clock signal of the bus by the application of these two measurements to a regeneration stage comprising a ring oscillator and counting means identical to those used for the acquisition.
  • [0007]
    A device for the regeneration of the clock signal of the bus according to the invention thus comprises an acquisition stage and a regeneration stage, each comprising a ring oscillator and counting means. The acquisition stage is used to measure the number of entire reference clock periods between two successive pulses of the serial bus and the current phase of the reference clock signal on the second pulse. The regeneration stage uses the measurements of the acquisition stage to generate a pulse at output by a ring oscillator and identical counting means.
  • [0008]
    The invention therefore relates to a device for the regeneration of the clock signal of an external serial bus in an integrated circuit, comprising a stage for the acquisition of the period of the clock signal of the bus comprising a ring oscillator, counting means and means for the reading of a current phase. The ring oscillator provides at an output n phases of a clock signal.
  • [0009]
    A phase is applied as a reference clock signal to the counting means to count the number of entire reference clock signal periods between a first pulse and a second pulse of the bus. The means for the reading of the current phase is activated by the second pulse. The current phase corresponds to the measurement of the phase delay between the reference clock signal and this second pulse.
  • [0010]
    The regeneration device furthermore comprises a regeneration stage comprising a ring oscillator and counting means identical to those of the acquisition stage for reproducing the number of pulses counted and the current acquisition phase, and to control a pulse generator giving a regenerated clock signal at an output.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0011]
    Other features and advantages of the invention are described in detail in the following description given by way of a non-restrictive indication and with reference to the appended drawings, of which:
  • [0012]
    [0012]FIG. 1 shows a signal received by an integrated circuit via an external serial bus for which it is sought to regenerate the clock signal internally according to the present invention;
  • [0013]
    [0013]FIG. 2 shows a general block diagram of a device for the regeneration of a synchronized clock signal according to an embodiment of the present invention;
  • [0014]
    [0014]FIG. 3 is a detailed diagram of the oscillators with the storage and phase selection circuits according to the present invention;
  • [0015]
    [0015]FIG. 4 is a detailed description of the principle of acquisition of the current phase in the oscillator of the acquisition stage according to the present invention; and
  • [0016]
    [0016]FIG. 5 is a timing diagram of the different signals of the diagram of FIG. 2 in an example of sequencing according to the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0017]
    The present invention is more particularly described within the framework of an application to an integrated circuit carrying out transactions with other integrated circuits by a USB serial bus, but its use is not limited to this application. This bus in practice takes the form of two differential lines connected in each integrated circuit to a sender and a receiver.
  • [0018]
    According to the protocol associated with such a bus, when a transaction is initiated, there is a first transitional phase during which the voltage of one of the differential lines rises while the voltage in the other line remains at zero. Then the transaction starts. According to the USB protocol, synchronization bits are first sent by the system manager of the bus which has received a transaction request. Then, the circuit initiating the transaction sends its data.
  • [0019]
    [0019]FIG. 1 shows an exemplary start of a transaction on a USB type serial bus, with a transitional phase and the beginning of the transaction. The example shows six synchronization pulses IS1 to IS6 and then a sequence of logic data elements DATA transmitted by the integrated circuit which has initiated the transaction.
  • [0020]
    As soon as the receiver of an integrated circuit concerned by the transaction detects a difference in voltage between the differential lines d+ and d− of the bus, the integrated circuits start a transaction initializing procedure. The integrated circuit must get ready to receive the synchronization bits, typically six bits for a USB bus, for the internal regeneration of the USB clock signal by which it will be able to receive and/or send data elements.
  • [0021]
    According to the invention, the regeneration device uses two ring oscillators. Thus, the initializing phase following the phase of detection of a beginning of a transaction comprises especially the putting into operation of these oscillators. When this initialization phase is ended, the regeneration device according to the invention is ready. According to the invention, it can measure the clock signal of the bus from the first two synchronization bits received from the USB bus. The other pulses that are then received are used to update the measurements and resynchronize the device.
  • [0022]
    An integrated circuit comprising a regeneration circuit according to the invention is shown in FIG. 2. In the integrated circuit CI, after reshaping in an input circuit 1 of the signals received from the differential lines d+ and d− of the USB bus, a signal referenced CK6 is obtained. On this signal, therefore, the synchronization pulses IS1 to IS6 are received, and then a sequence of 0s and 1s corresponding to the data is transmitted at the frequency of the USB clock signal. This signal CK6 is applied to the input of the regeneration device 2 according to the invention. This device provides at an output a regenerated clock signal CKGEN that is applied to a data output stage 3 on the serial bus USB.
  • [0023]
    The regeneration device 2 according to the invention comprises an acquisition stage A and a regeneration stage R working in parallel. The regeneration stage uses at each new regeneration cycle the data given by the acquisition stage.
  • [0024]
    The acquisition stage A comprises a ring oscillator RO1, and means 10 of acquisition and storage of the current phase Φa of the reference clock signal given by the ring oscillator. The acquisition stage further comprises counting means 11, means for the storage of the number Na of the periods of the reference clock signal, and means 12 for the sequencing of the acquisition stage.
  • [0025]
    If we refer to the exemplary sequencing operation shown in the timing diagram of FIG. 5, this acquisition stage A is initialized at each signal CK6 pulse received from the serial bus. More precisely, in the example shown, after the detection of a start of transaction, the first synchronization pulse IS1 on CK6 causes the activation of an initialization signal Init of an acquisition cycle.
  • [0026]
    This signal Init is applied as an initialization signal Start1 of the ring oscillator R1 and the counting means 11. Thus, the ring oscillator is synchronized with the signal CK6 pulse. This provides for the counting, in the counting means 11, of the number of entire clock reference periods following this first signal CK6 pulse.
  • [0027]
    When the second synchronization pulse IS2 is received, the sequencing means activate a latch control signal which activates the acquisition and storage of the current phase Φa in the oscillator RO1 and of the number Na of pulses counted between the two pulses of CK6. This latch control signal then launches the initializing of the ring oscillator and the counting means for a new acquisition cycle. FIG. 2 shows that the latch control signal is applied as an initialization signal Start1 through a gate 13. Thus, the initialization signal Start1 is activated with a small delay on the latch signal. This delay is equal to the time taken for carrying out the acquisition and storage of the data elements Φa and Na.
  • [0028]
    When the synchronization pulses of CK6 have all been received, pulses of CK6 are received at variable time intervals greater than a clock signal period of the bus as a function of the sequence of the data transmitted. In this case, the data elements acquired between two of these pulses are not right. Thus, in the invention, it is planned to activate the acquisition and data storage means Φa and Na only if the two CK6 pulses that sandwich the acquisition cycle correspond to a clock period.
  • [0029]
    This can be done simply, for example by appropriately sizing the counting means at a maximum predetermined number so that, when this limit is reached, the counting means activate a signal indicating the crossing of this limit. This limit-crossing signal, referenced Time-out in FIG. 2, could also be sent by a watchdog type circuit reset at each initialization of the acquisition step.
  • [0030]
    The sequencing means 12 of the acquisition stage are obtained in practice by state machines to appropriately generate the Init and latch control signals as a function of the signal CK6 and the signal Time-out. In the example, the Init and latch signals are each applied as an initialization signal Start1 by an OR type logic gate 14.
  • [0031]
    In practice, the counting means 11 may include two counters 110 and 111. The first counter 110 counts a predetermined fixed number Nf. When this count is achieved, it activates the counting in the second counter 111. The data element Na corresponding to the measurement is then that of the second counter and is used to initialize a corresponding counter in the regeneration stage. This data element Na is stored in a register 11 a upon the activation of the latch command applied to the counter 111.
  • [0032]
    The regeneration stage includes a ring oscillator RO2, and means 20 for reading the phase Φa memorized in the acquisition stage and for the selection of the corresponding phase Φr in the oscillator RO2. The regeneration stage further includes means 21 for counting the number Na given by the acquisition stage and means 22 for initializing each new regeneration cycle. The ring oscillator RO2 is structurally identical to that of the acquisition phase. At output, it gives a reference clock signal CKR2 used to regenerate the clock signal of the bus.
  • [0033]
    The counting means 21 receive this reference clock signal CKR2 to count the number Na given by the acquisition stage R. When this count is reached, it activates an end-of-count signal END at output, which is applied as an enabling signal Val_Φ for the selection of the current phase Φr of the reference clock signal CK2. The appearance of the pulse on this phase then activates a pulse generator IGEN which gives the regenerated clock signal CKGEN at an output.
  • [0034]
    The sequencing means 22 of the regeneration stage have the function of resetting the oscillator RO2 and the counting means 21 at each new regeneration cycle. The first regeneration cycle is activated by the appearance of the first pulse IS1 of CK6.
  • [0035]
    The following cycles are, for example, activated by each of the pulses of the regenerated clock signal CKGEN. In a more complicated sequencing, it would be possible to take account of the pulses of this regenerated clock signal CKGEN by default or else the pulses of CK6 when these pulses are received. In any case, at each new regeneration cycle, a new reading of the data elements Φa and Na given by the acquisition stage is launched so that, at each regeneration cycle, the most recent data elements are used.
  • [0036]
    It has been seen here above that the counting means are identical in both stages, so that the clock signal of the bus can be regenerated with precision. Should the counting means 11 of the acquisition stage be formed by two counters 110 and 111, the counting means 21 of the regeneration stage are also formed by two counters. The first counter 210 is identical to that of the acquisition stage to count a fixed number Nf of reference clock pulses. The second counter 211 is identical to that of the acquisition stage to count the variable number Na. In the example, this second counter 211 is used as a countdown unit. It is activated by the first counter 210 when it has reached its count Nf.
  • [0037]
    It will clearly be understood that the regeneration device according to the invention is based on the identity of the circuits used, firstly, for the acquisition and, secondly, for the regeneration, these circuits being used in the acquisition stage to measure the data elements Φa and Na, these same circuits being used in the restitution stage for the restitution at output of the signal corresponding to these measurements.
  • [0038]
    [0038]FIG. 3 gives a detailed view of the ring oscillators of the acquisition and regeneration stages with the means 10 of acquisition and storage and the current phase Φa reading and selecting means 20. In the example the ring oscillator RO1 has ten D-type, series-connected latches B0 to B9. The output Q9 of the last latch give the reference clock signal CKR1 and is looped to the input of the first latch B0.
  • [0039]
    In the example, the nine first latches B0 to B8 are such that their Q output is applied to the input of the next latch. The tenth latch B9 is such that its output nq is applied as an output signal and at input of the latch B0. However, these ten latches are structurally identical so that they impose exactly the same delay between the input d and their output q (B0 to B8) or nq (B9). This is obtained in practice in a well-known manner by reversing the transfer control signals in the “nq” latch with respect to the “q” latches.
  • [0040]
    The signal Start1 for initializing an acquisition cycle is applied to force the starting conditions of the ring oscillator RO1. In the example, it is applied to an input Preset for presetting the first three latches B0 to B2 and to an input Clear for clearing the other latches.
  • [0041]
    The signal latch for its part is applied to the latches B0 to B9 of the oscillator to stop them for the period of time taken for the storage, in the other latches B0_1 to B9_1, of the state of their inputs D0 to D9. These latches B0_1 to B9_1 of the acquisition and storage means 10 of the current phase Φa are of the D latch circuit type with edge activation. In the example, the passage from 0 to 1 of the latch signal activates the storage, in these flip-flops, of the input applied to them. The output of these latches B0_1 to B9_1 is applied to the inputs E0 to E9 of a circuit DEC capable of giving, at output, an information element on phase measurement. This is namely information determining a latch input, among the ten latch inputs of the ring oscillator, corresponding to the current phase Φa of the clock signal of the reference CKR1 at the time of reception of a pulse of CK6.
  • [0042]
    The principle of acquisition of the current phase is illustrated in FIG. 4. The ring oscillator gives n phases of a clock signal, one per latch input. In the example, n=10. We therefore have the phases Φ0 to Φ9. In the example, the phase Φ0 is taken as the reference phase to be used as a reference clock signal CKR1 applied to the counting means. Thus, in the example, when the ring oscillator and the counting means are initialized, at output, there is obtained the leading edge of a pulse on the phase Φ0. From which the counting means can count a number of entire periods of the reference clock signal.
  • [0043]
    The n phases of the oscillator are phase-shifted with respect to each other by the delay ut of the latch, which is the same in each latch. If the ring oscillator is sized so that this delay ut is equal to 1 nanosecond, ten phases signals with a period of 10 ns are obtained, phase-shifted from each other by 1 ns.
  • [0044]
    Referring to FIGS. 4 and 5, the first acquisition cycle is activated by the reception of the first pulse IS1 of CK6. The principle of acquisition according to the invention includes synchronizing the phase Φ0 used as the reference clock signal CKR1 on this pulse IS1. This is obtained by setting the initialization (Start1) of the oscillator RO1 and the counting means 11 upon reception of the pulse IS1. It has been seen that, at output, a leading pulse edge is obtained on Φ0. Starting from this leading edge, the counting means will start counting a number of entire periods of CKR1.
  • [0045]
    When the second pulse IS2 is received, the signal latch is activated and stops the oscillator and the counting means. The number Na of pulses counted is loaded into a storage register along with the state of the inputs of the latches B0 to B9, making it possible to deduce the phase delay between the last pulse of the reference pulse Φ0 and the pulse IS2 of CK6.
  • [0046]
    This delay corresponds to the measurement, in the time unit ut, of the time interval T between the last pulse of CKR10 and the pulse IS2 of CK6, namely in the example a measurement of this time unit to within 1 nanosecond. This delay corresponds to the identification of the current phase, namely the phase with which the pulse of CK6 corresponds to a leading edge. This is what is called the measurement of the current phase.
  • [0047]
    What has to be done then, in the regeneration stage, is to select this phase to reproduce the time interval to be allowed to elapse after the counting of the number Na of pulses before regenerating the pulse CKGEN. For this purpose, the ring oscillator RO2 of the regeneration stage has to be strictly identical to the ring oscillator RO1 of the acquisition stage.
  • [0048]
    The oscillator RO2 in the example has ten D type latches B0_r to B9_r, in series. The output Q9 of the last latch gives the reference clock signal CKR2 and is applied to the input of the first latch B0_r (FIG. 3). The signal Start2 is applied to these latches to force precisely the same initialization conditions (Preset, Clear) as in the ring oscillator RO1.
  • [0049]
    The read means 20 of the phase to be selected in the ring oscillator RO2 comprises a logic circuit 20_a to transmit the phase selection information Sel_Φ=[Sel_Φ0, Sel_Φ1, . . . , Sel_Φ9] on a circuit 20_b of controlled gates. This transmission is done upon activation of the signal Start2. The phase selection information Sel_Φ is such that only one bit is at 1 for the selection of only one latch input of the ring oscillator RO2 as the phase output Φr. All the other bits are at zero.
  • [0050]
    The controlled gate circuit 20_b comprises one gate per latch of the oscillator RO2, i.e., in the example, there are ten controlled gates P0, . . . , P9. Each of these gates is connected between the input of the associated latch and the phase output Φr. This phase output Φr is applied to the pulse generation circuit IGEN when the end-of-count signal END of the means 21 is activated.
  • [0051]
    With a device according to the invention, it is possible, in practice, to regenerate the clock of the bus and to do so with high precision. This device is more particularly applicable in the integrated circuits of smart-card type portable carriers, but also can be used more generally.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7453958Jun 23, 2005Nov 18, 2008Infineon Technologies AgMethod and device for extracting a clock frequency underlying a data stream
US8595543 *Sep 24, 2010Nov 26, 2013Elan Microelectronics CorporationMethod and circuit for trimming an internal oscillator of a USB device according to a counting number between a first and second clock count value
US20060023824 *Jun 23, 2005Feb 2, 2006Infineon Technologies AgMethod and device for extracting a clock frequency underlying a data stream
US20110093736 *Apr 21, 2011Elan Microelectronics CorporationMethod and circuit for trimming an internal oscillator of a usb device
EP1646150A1Dec 23, 2003Apr 12, 2006Infineon Technologies AGMethod and device for extracting a clock pulse frequency underlying a data flow
Classifications
U.S. Classification327/165
International ClassificationG06F13/42, G06K19/07
Cooperative ClassificationG06K19/07, G06F13/426
European ClassificationG06K19/07, G06F13/42D6
Legal Events
DateCodeEventDescription
Apr 30, 2001ASAssignment
Nov 19, 2002CCCertificate of correction
Sep 2, 2005FPAYFee payment
Year of fee payment: 4
Aug 28, 2009FPAYFee payment
Year of fee payment: 8
Aug 26, 2013FPAYFee payment
Year of fee payment: 12