US20010023051A1 - Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride - Google Patents

Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride Download PDF

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US20010023051A1
US20010023051A1 US09/773,462 US77346201A US2001023051A1 US 20010023051 A1 US20010023051 A1 US 20010023051A1 US 77346201 A US77346201 A US 77346201A US 2001023051 A1 US2001023051 A1 US 2001023051A1
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layer
photoresist
substrate
adhesion
processing method
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J. Rolfson
Annette Martin
Ardavan Niroomand
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist

Abstract

A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride includes, a) providing a substrate; b) providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface; c) covering the outer Si3N4 surface with a discrete photoresist adhesion layer; and d) depositing a layer of photoresist over the outer Si3N4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present. Further, a method in accordance with the invention includes, i) providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface; ii) transforming the outer Si3N4 surface into a material effective to promote adhesion of photoresist to the Si3N4 layer; and iii) depositing a layer of photoresist over the transformed outer Si3N4 surface, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface were not transformed.

Description

    TECHNICAL FIELD
  • This invention relates generally to semiconductor processing methods of promoting adhesion of photoresist to an outer substrate layer predominantly comprising silicon nitride. [0001]
    • BACKGROUND OF THE INVENTION
  • Microcircuit fabrication involves provision of precisely controlled quantities of impurities into small regions of a silicon substrate, and subsequently interconnecting these regions to create components and integrated circuits. The patterns that define such regions are typically created by a photolithographic process. Such processing sets the horizontal dimensions on the various parts of the devices and circuits. Photolithography is a multistep pattern transfer process similar to stenciling or photography. In photolithograpy, the required pattern is first formed in reticles or photomasks and transferred into the surface layer(s) of the wafer through photomasking steps. [0002]
  • Inherent in photolithograpy is application and adherence of photoresist materials to underlying substrates. The resist must be capable of adhering to these surfaces through all the resist processing and etch steps. Poor adhesion brings about severe undercutting, loss of resolution, or possibly the complete loss of the pattern. Wet etching techniques demand a high level of adhesion of the resist film to the underlying substrates. [0003]
  • Various techniques are used to increase the adhesion between resist and a substrate such as, a) dehydration baking prior to coating; b) use of hexamethyldisilazane (HMDS) and vapor priming systems to promote resist adhesion for polysilicon, metals and SiO[0004] 2 layers, and c) elevated temperature post-bake cycles. HMDS functions as an effective adhesion promoter for silicon and silicon oxide containing films, but provides effectively no surface-linking adhesion promotion with respect to silicon nitride films.
  • Accordingly, it would be desirable to develop alternate and improved techniques for providing better adhesion of photoresist to silicon nitride films.[0005]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0006]
  • FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention. [0007]
  • FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1. [0008]
  • FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 2. [0009]
  • FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 3. [0010]
  • FIG. 5 is a diagrammatic sectional view of an alternate embodiment semiconductor wafer fragment at one alternate processing step in accordance with the invention. [0011]
  • FIG. 6 is a view of the FIG. 5 wafer fragment at a processing step subsequent to that shown by FIG. 5. [0012]
  • FIG. 7 is a diagrammatic sectional view of yet another alternate embodiment semiconductor wafer fragment at yet another alternate processing step in accordance with the invention.[0013]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). [0014]
  • In accordance with one aspect of the invention, a semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride comprises the following steps: [0015]
  • providing a substrate; [0016]
  • providing an outer layer of Si[0017] 3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
  • covering the outer Si[0018] 3N4 surface with a discrete photoresist adhesion layer; and
  • a layer of photoresist over the outer Si[0019] 3N4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present.
  • In accordance with another aspect, a semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride comprises the following steps: [0020]
  • providing a substrate; [0021]
  • providing an outer layer of Si[0022] 3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
  • transforming the outer Si[0023] 3N4 surface into a material effective to promote adhesion of photoresist to the Si3N4 layer; and
  • depositing a layer of photoresist over the transformed outer Si[0024] 3N4 surface, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface were not transformed.
  • Referring to FIGS. [0025] 1-4, and initially to FIG. 1, a semiconductor wafer fragment in process is indicated generally with reference numeral 10. Such includes a substrate composed of a bulk monocrystalline silicon substrate 12 and an overlying insulating layer 14, such as SiO2. An example thickness for layer 14 is from 50 Angstroms to 300 Angstroms.
  • Referring to FIG. 2, an [0026] outer layer 16 of Si3N4 is provided outwardly of substrate 12/14. Nitride layer 16 includes an outer surface 18. Thickness of layer 16 will depend upon the application. For example where layer 16 is merely functioning as an etch stop in some later process step, its thickness may approximate 100 Angstroms or less. Where layer 16 is being used as a mask for a local oxidation of silicon (LOCOS), layer 16 thickness may be from 1500 Angstroms to 3000 Angstroms.
  • The preferred manner of depositing or otherwise providing [0027] nitride layer 16 is by chemical vapor deposition within a chemical vapor deposition reactor using a gaseous silicon containing precursor and a gaseous nitrogen containing precursor. An example preferred nitride precursor is dichlorosilane (DCS), with a preferred nitrogen containing precursor being ammonia (NH3). One example set of deposition parameters includes maintaining reactor temperature and pressure at 780° C. and 250 mTorr, respectively, with the precursors being provided at a volumetric ratio of DCS:NH3 at 1:3. Such is but one example set of conditions effective to deposit a Si3N4 layer on substrate 14/12.
  • Referring to FIG. 3, the gas flow of the nitrogen containing precursor to the chemical vapor deposition reactor is reduced, thus increasing the concentration of the silicon component of the precursor. This will have the effect of enrichening the Si[0028] 3N4 layer outermost surface 18 to outermost surface 18 a with silicon atoms, as depicted by the dots in the FIG. 3, to provide increased silicon concentration beyond the empirical stoichiometric relationship of silicon to nitride atoms in molecular silicon nitride. Thus, the outer silicon nitride surface has been transformed into a material (i.e. silicon enrichened Si3N4) which can effectively be used to promote subsequent adhesion of photoresist to Si3N4 layer 16 a. Silicon is a material to which photoresist will more readily adhere than Si3N4. An example reduction from the 1:3 DCS:NH3 ratio to achieve such enrichening is to a ratio of from 1:0 to 1:1.25.
  • Referring to FIG. 4, a layer of photoresist is deposited over silicon enrichened outer Si[0029] 3N4 surface 18 a, and is for example patterned as shown to produce photoresist blocks 20. Silicon enrichened outer surface 18 a can optionally be treated with suitable other adhesion primers appropriate to silicon, such as HMDS. Regardless, a desired result is photoresist material 20 adhering to Si3N4 layer 16 a with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface 18 were not transformed by silicon enrichening. All of the above described processing preferably and advantageously occurs in the same single chemical vapor deposition reactor. Alternately, more than one reactor chamber can be used.
  • An [0030] alternate embodiment 22 is described with reference to FIGS. 5 and 6. Such comprises a substrate composed of bulk monocrystalline silicon 24 and an overlying SiO2 layer 26. An outer predominantly nitride layer 28 is provided over SiO2 layer 26. Such also includes an outer surface 30, the immediately underlying portion thereof which has been transformed to an oxidized material 32, preferably SiO2. Bulk mass 34 of layer 28 constitutes Si3N4. The processing to produce materials 34 and 32 preferably is again conducted in a single, common chemical vapor deposition reactor.
  • [0031] Material 32 relative to outer surface 30 is preferably provided by feeding a gaseous oxygen containing precursor to the reactor under conditions effective to oxidize Si3N4 material 34 to SiO2 material 32. One example process for accomplishing such transformation of outer surface 30 is to cease feeding the dichlorosilane and ammonia precursors as described in the above example, and purging the reactor of such gaseous precursors. Immediately thereafter, N2O, O2, O3, or mixtures thereof are fed to the reactor under the same temperature and pressure conditions which effectively causes the outer surface of the nitride material to become oxidized to SiO2. The thickness of material 32 is preferably kept very low, such as from about 10 Angstroms to about 30 Angstroms. Purging of the Si3N4 precursors is highly desirable to prevent an undesired silicon dust from falling out onto the wafer as may occur without purging, which neither produces the SiO2 material of this example, nor readily adheres to the underlying substrate.
  • An example processing for O[0032] 3, would be at atmospheric or subatmospheric pressure at a temperature of 600° C. for from one to two hours. For O2, an example oxidizing condition would be feeding both O2 and H2 at atmospheric pressure and temperatures ranging from 800° C. to 1100° C. for from 30 minutes to two hours.
  • Alternately but less preferred, the above processing could take place in two separate chambers, with the wafer(s) being moved from one to the other after provision of the nitride layer for subsequent provision of the adhesion promoting layer. [0033]
  • Referring to FIG. 6, a layer of photoresist is deposited and patterned to produce [0034] photoresist blocks 36, as in the first described embodiment. The photoresist adheres to Si3N4 layer 28 with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface 30 were not oxidized.
  • Other alternate examples are described with reference to FIG. 7, illustrating a [0035] semiconductor wafer fragment 40. Such again comprises a substrate composed of a bulk monocrystalline silicon substrate 42 and overlying SiO2 layer 44. An overlying layer 46 of Si3N4 is provided, preferably as described above with respect to the other embodiments. Nitride layer 46 has an outer surface 48. Subsequently, conditions are provided within a chemical vapor deposition reactor to cover outer Si3N4 surface 48 with a discrete photoresist adhesion layer 50 having a thickness of preferably from about 10 Angstroms to about 30 Angstroms. Thus, an outer composite substrate layer 52 is provided which predominantly comprises Si3N4. Example and preferred materials for thin discrete photoresist adhesion layer 50 are silicon or SiO2.
  • Silicon can be deposited by any typical or known process for depositing polycrystalline silicon atop a semiconductor wafer. An example and preferred method for providing [0036] layer 50 to constitute SiO2 is to first purge the reactor after Si3N4 layer deposition, followed by feeding of DCS and N2O to the reactor under temperature conditions of 780° C. and 250 mTorr at a volumetric ratio of DCS:N2O of from 1:3 to 1:10. Subsequently provided photoresist will adhere to Si3N4 layer 52 with a greater degree of adhesion than would otherwise occur if the intermediate silicon, SiO2, or other adhesion promoting layer were not present.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0037]

Claims (27)

1. A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride, the method comprising the following steps:
providing a substrate;
providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
covering the outer Si3N4 surface with a discrete photoresist adhesion layer; and
depositing a layer of photoresist over the outer Si3N4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present.
2. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 1
 wherein the discrete photoresist adhesion layer is provided to a thickness of less than or equal to about 30 Angstroms.
3. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 1
 wherein the discrete photoresist adhesion layer is provided to a thickness of between about 10 Angstroms and 30 Angstroms.
4. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 1
 wherein the Si3N4 layer and photoresist adhesion layer are both provided by chemical vapor deposition in the same chemical vapor deposition reactor.
5. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 1
 wherein the photoresist adhesion layer is selected from the group consisting of silicon and SiO2.
6. A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride, the method comprising the following steps:
providing a substrate;
providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
transforming the outer Si3N4 surface into a material effective to promote adhesion of photoresist to the Si3N4 layer; and
depositing a layer of photoresist over the transformed outer Si3N4 surface, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface were not transformed.
7. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 6
 wherein the material predominately comprises silicon enriched Si3N4.
8. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 6
 wherein the material predominately comprises SiO2.
9. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 6
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the transforming step occurring within the same chemical vapor deposition reactor.
10. A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride, the method comprising the following steps:
providing a substrate;
placing the substrate within a chemical vapor deposition reactor;
feeding a gaseous silicon containing precursor and a gaseous nitrogen containing precursor to the reactor under conditions effective to deposit a Si3N4 layer on the substrate;
reducing the gas flow of the nitrogen containing precursor to the reactor to enrichen an outermost surface of the deposited Si3N4 layer with silicon atoms; and
depositing a layer of photoresist over the silicon enrichened outer Si3N4 surface, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface were not silicon enrichened.
11. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 10
 wherein the silicon containing precursor comprises dichlorosilane and the nitrogen containing precursor comprises ammonia.
12. A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride, the method comprising the following steps:
providing a substrate;
providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
providing the substrate having the Si3N4 layer within a chemical vapor deposition reactor;
feeding a gaseous oxygen containing precursor to the reactor under conditions effective to oxidize the Si3N4 layer outer surface to material comprising SiO2; and
depositing a layer of photoresist over the oxidized Si3N4 layer outer surface, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the outer Si3N4 surface were not oxidized.
13. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 12
 wherein the SiO2 material layer is provided to a thickness of less than or equal to about 30 Angstroms.
14. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 12
 wherein the SiO2 material layer is provided to a thickness of from about 10 Angstroms to about 30 Angstroms.
15. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 12
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the oxidizing step occurring within the same chemical vapor deposition reactor.
16. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 12
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the oxidizing step occurring within the same chemical vapor deposition reactor, the reactor being purged of gaseous precursors used for the Si3N4 deposition before the oxidation step.
17. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 12
 wherein the gaseous oxygen containing precursor is selected from the group consisting of O2, O3, N2O and mixtures thereof.
18. A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride, the method comprising the following steps:
providing a substrate;
providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
providing the substrate having the Si3N4 layer within a chemical vapor deposition reactor;
feeding a gaseous silicon containing precursor to the reactor under conditions effective to deposit a silicon layer over the Si3N4 layer outer surface; and
depositing a layer of photoresist over the silicon layer, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate silicon layer were not present.
19. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 18
 wherein the silicon layer is provided to a thickness of less than or equal to about 30 Angstroms.
20. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 18
 wherein the silicon layer is provided to a thickness of from about 10 Angstroms to about 30 Angstroms.
21. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 18
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the silicon deposition step occurring within the same chemical vapor deposition reactor.
22. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 18
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the silicon deposition step occurring within the same chemical vapor deposition reactor, the reactor being purged of gaseous precursors used for the Si3N4 deposition before the silicon deposition step.
23. A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride, the method comprising the following steps:
providing a substrate;
providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface;
providing the substrate having the Si3N4 layer within a chemical vapor deposition reactor;
feeding a gaseous silicon containing precursor and a gaseous oxygen containing precursor to the reactor under conditions effective to deposit an SiO2 layer over the Si3N4 layer outer surface; and
depositing a layer of photoresist over the outer Si3N4 surface having the intermediate SiO2 layer thereover, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate silicon layer were not present.
24. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 23
 wherein the SiO2 layer is provided to a thickness of less than or equal to about 30 Angstroms.
25. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 23
 wherein the SiO2 layer is provided to a thickness of from about 10 Angstroms to about 30 Angstroms.
26. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 23
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the SiO2 deposition step occurring within the same chemical vapor deposition reactor.
27. The semiconductor processing method of promoting adhesion of photoresist to silicon nitride of
claim 23
 wherein the Si3N4 layer is provided over the substrate within a chemical vapor deposition reactor, the SiO2 deposition step occurring within the same chemical vapor deposition reactor, the reactor being purged of gaseous precursors used for the Si3N4 deposition before the SiO2 deposition step.
US09/773,462 1995-12-04 2001-01-31 Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride Expired - Fee Related US6451504B2 (en)

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US08/567,090 US5926739A (en) 1995-12-04 1995-12-04 Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US09/295,642 US6297171B1 (en) 1995-12-04 1999-04-20 Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US09/773,462 US6451504B2 (en) 1995-12-04 2001-01-31 Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060228895A1 (en) * 2005-04-06 2006-10-12 Chae Yun-Sook Method of forming fine pitch photoresist patterns using double patterning technique
US7208805B2 (en) * 2000-01-18 2007-04-24 Micron Technology, Inc. Structures comprising a layer free of nitrogen between silicon nitride and photoresist
US20200118813A1 (en) * 2018-10-15 2020-04-16 Mattson Technology, Inc. Ozone for Selective Hydrophilic Surface Treatment

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926739A (en) 1995-12-04 1999-07-20 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US6300253B1 (en) 1998-04-07 2001-10-09 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6323139B1 (en) * 1995-12-04 2001-11-27 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials
KR100232853B1 (en) * 1997-10-15 1999-12-01 윤종용 Heating apparatus for inkjet printer head and method for fabricating thereof
US6274292B1 (en) 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US7804115B2 (en) 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6316372B1 (en) 1998-04-07 2001-11-13 Micron Technology, Inc. Methods of forming a layer of silicon nitride in a semiconductor fabrication process
US5985771A (en) 1998-04-07 1999-11-16 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US6635530B2 (en) * 1998-04-07 2003-10-21 Micron Technology, Inc. Methods of forming gated semiconductor assemblies
US6368919B2 (en) 1999-01-19 2002-04-09 Micron Technology, Inc. Method and composite for decreasing charge leakage
JP3400770B2 (en) * 1999-11-16 2003-04-28 松下電器産業株式会社 Etching method, semiconductor device and manufacturing method thereof
US7632929B2 (en) * 2000-04-20 2009-12-15 The Board Of Trustees Of The University Of Arkansas Methamphetamine-like hapten compounds, linkers, carriers and compositions and uses thereof
US6387719B1 (en) 2001-02-28 2002-05-14 Lexmark International, Inc. Method for improving adhesion
US20030150640A1 (en) * 2002-02-14 2003-08-14 Crippen Warren Stuart Silicon space transformer and method of manufacturing same
US7145182B2 (en) * 2003-09-12 2006-12-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Integrated emitter devices having beam divergence reducing encapsulation layer
US7642195B2 (en) * 2005-09-26 2010-01-05 Applied Materials, Inc. Hydrogen treatment to improve photoresist adhesion and rework consistency
US20080156346A1 (en) * 2006-12-28 2008-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for cleaning a substrate
JP5037243B2 (en) * 2007-07-06 2012-09-26 富士フイルム株式会社 Interfacial binder, resist composition containing the interfacial binder, laminate for forming a magnetic recording medium having a layer comprising the interfacial binder, a method for producing a magnetic recording medium using the interfacial binder, and Magnetic recording medium manufactured by the manufacturing method

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3549411A (en) 1967-06-27 1970-12-22 Texas Instruments Inc Method of preparing silicon nitride films
JPS497870B1 (en) 1969-06-06 1974-02-22
US3884698A (en) * 1972-08-23 1975-05-20 Hewlett Packard Co Method for achieving uniform exposure in a photosensitive material on a semiconductor wafer
US4075367A (en) * 1976-03-18 1978-02-21 Ncr Corporation Semiconductor processing of silicon nitride
US4330569A (en) * 1979-05-25 1982-05-18 Ncr Corporation Method for conditioning nitride surface
US4417325A (en) 1981-07-13 1983-11-22 Eliyahou Harari Highly scaleable dynamic ram cell with self-signal amplification
US4939559A (en) 1981-12-14 1990-07-03 International Business Machines Corporation Dual electron injector structures using a conductive oxide between injectors
US4446194A (en) 1982-06-21 1984-05-01 Motorola, Inc. Dual layer passivation
KR840006728A (en) * 1982-11-01 1984-12-01 오레그 이. 엘버 Integrated circuit manufacturing method
US4485553A (en) 1983-06-27 1984-12-04 Teletype Corporation Method for manufacturing an integrated circuit device
JPS6010644A (en) 1983-06-30 1985-01-19 Toshiba Corp Semiconductor device and manufacture thereof
US4439270A (en) 1983-08-08 1984-03-27 International Business Machines Corporation Process for the controlled etching of tapered vias in borosilicate glass dielectrics
US4499656A (en) * 1983-08-15 1985-02-19 Sperry Corporation Deep mesa process for fabricating monolithic integrated Schottky barrier diode for millimeter wave mixers
GB2145243B (en) * 1983-08-18 1987-08-26 Gen Electric Optical lithographic processes
US4698787A (en) 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
GB2170649A (en) * 1985-01-18 1986-08-06 Intel Corp Sputtered silicon as an anti-reflective coating for metal layer lithography
CA1252372A (en) * 1985-01-21 1989-04-11 Joseph P. Ellul Nitsinitride and oxidized nitsinitride dielectrics on silicon
JPS62137854A (en) 1985-12-11 1987-06-20 Nec Corp Manufacture of semiconductor device
US4874716A (en) 1986-04-01 1989-10-17 Texas Instrument Incorporated Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface
US4695872A (en) 1986-08-01 1987-09-22 Texas Instruments Incorporated High density micropackage for IC chips
US4732858A (en) * 1986-09-17 1988-03-22 Brewer Science, Inc. Adhesion promoting product and process for treating an integrated circuit substrate
JP2551595B2 (en) 1987-07-31 1996-11-06 工業技術院長 Semiconductor non-volatile memory device
JPH084109B2 (en) 1987-08-18 1996-01-17 富士通株式会社 Semiconductor device and manufacturing method thereof
JPH01185692A (en) * 1988-01-19 1989-07-25 Sanyo Electric Co Ltd Plane display panel
US5304829A (en) 1989-01-17 1994-04-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device
JPH0375158A (en) 1989-08-16 1991-03-29 Matsushita Electric Ind Co Ltd Thermal head
US5045345A (en) * 1989-10-31 1991-09-03 The United States Of America As Represented By The Secretary Of The Navy Energy beam treatment for improved adhesion of coatings to surfaces
US5098865A (en) 1989-11-02 1992-03-24 Machado Jose R High step coverage silicon oxide thin films
US5178016A (en) 1989-11-15 1993-01-12 Sensym, Incorporated Silicon pressure sensor chip with a shear element on a sculptured diaphragm
TW214599B (en) 1990-10-15 1993-10-11 Seiko Epson Corp
JP2822656B2 (en) 1990-10-17 1998-11-11 株式会社デンソー Semiconductor device and manufacturing method thereof
KR940011483B1 (en) * 1990-11-28 1994-12-19 가부시끼가이샤 도시바 Semiconductor device with nitrided gate insulating film
US5219788A (en) * 1991-02-25 1993-06-15 Ibm Corporation Bilayer metallization cap for photolithography
JPH05102419A (en) * 1991-10-07 1993-04-23 Sony Corp Formation of capacity in dynamic ram
EP0627763B1 (en) 1993-05-31 2004-12-15 STMicroelectronics S.r.l. Process for improving the adhesion between dielectric layers at their interface in semiconductor devices manufacture
JP2682403B2 (en) 1993-10-29 1997-11-26 日本電気株式会社 Method for manufacturing semiconductor device
JP3364694B2 (en) * 1993-12-28 2003-01-08 株式会社アルバック Method of forming protective film
KR100366910B1 (en) 1994-04-05 2003-03-04 소니 가부시끼 가이샤 Manufacturing method of semiconductor device
JP2630257B2 (en) 1994-06-03 1997-07-16 日本電気株式会社 Method for manufacturing semiconductor device
US5508532A (en) 1994-06-16 1996-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with braded silicon nitride
US5834374A (en) 1994-09-30 1998-11-10 International Business Machines Corporation Method for controlling tensile and compressive stresses and mechanical problems in thin films on substrates
US5918147A (en) 1995-03-29 1999-06-29 Motorola, Inc. Process for forming a semiconductor device with an antireflective layer
US5926739A (en) 1995-12-04 1999-07-20 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US5756404A (en) 1995-12-07 1998-05-26 Micron Technologies, Inc. Two-step nitride deposition
US5925494A (en) 1996-02-16 1999-07-20 Massachusetts Institute Of Technology Vapor deposition of polymer films for photolithography
US5877069A (en) 1996-09-16 1999-03-02 Micron Technology, Inc. Method for electrochemical local oxidation of silicon
US5904523A (en) 1996-10-03 1999-05-18 Lucent Technologies Inc. Process for device fabrication in which a layer of oxynitride is formed at low temperatures
US5731235A (en) 1996-10-30 1998-03-24 Micron Technology, Inc. Methods of forming a silicon nitrite film, a capacitor dielectric layer and a capacitor
US5891793A (en) 1997-04-04 1999-04-06 Advanced Micro Devices, Inc. Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation
US6232643B1 (en) 1997-11-13 2001-05-15 Micron Technology, Inc. Memory using insulator traps
US6420777B2 (en) 1998-02-26 2002-07-16 International Business Machines Corporation Dual layer etch stop barrier
US5985771A (en) 1998-04-07 1999-11-16 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
TW404076B (en) 1999-04-16 2000-09-01 United Microelectronics Corp Photo diode and the manufacture method thereof
US6103619A (en) 1999-10-08 2000-08-15 United Microelectronics Corp. Method of forming a dual damascene structure on a semiconductor wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7208805B2 (en) * 2000-01-18 2007-04-24 Micron Technology, Inc. Structures comprising a layer free of nitrogen between silicon nitride and photoresist
US20060228895A1 (en) * 2005-04-06 2006-10-12 Chae Yun-Sook Method of forming fine pitch photoresist patterns using double patterning technique
US20200118813A1 (en) * 2018-10-15 2020-04-16 Mattson Technology, Inc. Ozone for Selective Hydrophilic Surface Treatment
US11495456B2 (en) * 2018-10-15 2022-11-08 Beijing E-Town Semiconductor Technology, Co., Ltd Ozone for selective hydrophilic surface treatment

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