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Publication numberUS20010023112 A1
Publication typeApplication
Application numberUS 09/837,136
Publication dateSep 20, 2001
Filing dateApr 18, 2001
Priority dateNov 20, 1998
Also published asUS6238998, US6437400
Publication number09837136, 837136, US 2001/0023112 A1, US 2001/023112 A1, US 20010023112 A1, US 20010023112A1, US 2001023112 A1, US 2001023112A1, US-A1-20010023112, US-A1-2001023112, US2001/0023112A1, US2001/023112A1, US20010023112 A1, US20010023112A1, US2001023112 A1, US2001023112A1
InventorsEffendi Leobandung
Original AssigneeEffendi Leobandung
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall
US 20010023112 A1
Abstract
A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.
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Claims(17)
What is claimed is:
1. A process for fabricating a trench, having a bottom and side walls defining a tapered shape, on a silicon substrate, the substrate having an exposed surface, wherein the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom, the process comprising:
forming an initial trench having initial trench side walls and the trench bottom extending from the exposed surface into an interior of the substrate;
implanting nitrogen ions on the initial trench side walls wherein more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and
oxidizing the trench side walls, thereby creating a trench having the tapered shape.
2. The process of
claim 1
wherein the initial trench side walls extend into the substrate in a direction substantially perpendicular to the exposed surface and are substantially perpendicular to each other.
3. The process according to
claim 2
wherein the step of implanting the nitrogen ions on the initial trench side walls comprises implanting the ions at an angle from about 10 degrees to about 60 degrees relative to the exposed surface.
4. The process according to
claim 3
wherein the nitrogen ions are implanted on the initial trench side walls at an angle of about 30 degrees relative to the exposed surface.
5. The process according to
claim 1
wherein the step of implanting the nitrogen ions comprises implanting from about 5 kev to about 10 keV nitrogen ions on the initial trench side walls to a dose of from about 11014/cm2 to about 11015/cm2.
6. The process according to
claim 5
wherein the step of implanting the nitrogen ions comprises implanting about 10 keV nitrogen ions on the initial trench side walls to a dose of about 51014/cm2.
7. The process according to
claim 1
wherein the step of forming the initial trench comprises photomasking and etching the substrate.
8. The process according to
claim 7
wherein the etching is dry etching.
9. The process according to
claim 1
wherein the substrate is a silicon-on-insulator substrate comprising a silicon oxide layer having a thickness of from about 0.1 μm to about 0.4 μm on a silicon wafer, a silicon layer having a thickness of from about 0.1 μm to about 0.2 μm on the silicon oxide layer, and a silicon nitride layer having a thickness of from about 0.1 μm to about 0.2 μm on the silicon layer.
10. The process according to
claim 9
wherein the silicon oxide layer has a thickness of about 0.4 μm, the silicon layer has a thickness of about 0.18 μm, and the silicon nitride layer has a thickness of about 0.12 μm.
11. The process according to
claim 9
wherein the substrate further comprises a thin silicon oxide layer having a thickness of from about 0.006 μm to about 0.01 μm between the silicon layer and the silicon nitride layer.
12. The process according to
claim 1
further comprising the step of cleaning the initial trench before the step of oxidizing the trench side walls.
13. A process for fabricating a trench having a bottom and side walls defining a tapered shape on a silicon-on-insulator substrate, the substrate having an exposed surface, wherein the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom, the process comprising:
forming an initial trench having initial trench side walls and the trench bottom extending from the exposed surface into an interior of the substrate by photomasking and dry etching the substrate;
implanting about 10 keV nitrogen ions to a dose of about 51014 cm/cm2 on the initial trench side walls at an angle from about 10 degrees to about 60 degrees wherein more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and
oxidizing the trench side walls with dry oxygen at about 1,000 C., thereby creating the tapered shape.
14. The process of
claim 13
wherein the substrate comprises a silicon oxide layer having a thickness of about 0.4 μm on a silicon wafer, a silicon layer having a thickness of about 0.18 μm on the silicon oxide layer, and a silicon nitride layer having a thickness of about 0.12 μm on the silicon layer.
15. A silicon substrate having an exposed surface and a trench having a bottom and side walls defining a tapered shape extending through the exposed surface into the substrate, wherein the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom, and wherein the trench is fabricated by:
forming an initial trench having initial trench side walls and the trench bottom extending from the exposed surface into the substrate;
implanting nitrogen ions on the initial trench side walls wherein more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and
oxidizing the trench side walls, thereby creating a trench having the tapered shape.
16. The substrate according to
claim 15
further comprising a silicon oxide layer on a silicon wafer, a silicon layer on the silicon oxide layer, and a silicon nitride layer on the silicon layer.
17. The substrate according to
claim 16
further comprising a thin silicon oxide layer having a thickness of from about 0.006 μm to about 0.01 μm between the silicon layer and the silicon nitride layer.
Description
TECHNICAL FIELD

[0001] The present invention relates to a process of fabricating a trench on a silicon substrate and, more particularly, to a process of forming a trench having tapered side walls on a silicon-on-insulator (SOI) substrate.

BACKGROUND OF THE INVENTION

[0002] An integrated circuit or an array of discrete integrated circuit devices includes numerous semiconductor devices. Current leakages and parasitic capacitances between devices can interfere with the intended operation of the circuit. Therefore, in many circuits, it is necessary to electrically isolate devices from one another. Several isolation techniques have been developed to meet that requirement.

[0003] A silicon-on-insulator (SOI) structure is a structure in which a buried insulating layer electrically isolates a silicon layer from a silicon substrate. The SOI structure does not always occupy the entire silicon substrate. Often, the SOI structure occupies only a portion of the silicon substrate.

[0004] Shallow Trench Isolation (STI) is a process used in isolating devices formed on SOI substrates. STI involves etching trenches, having side walls and bottoms, in the SOI substrate. Following etching, the trenches are filled with an oxide.

[0005] Unfortunately, there is a problem in implementing shallow trench isolation processing (STI) in SOI substrates. Following etching, and before filling the trenches with an oxide, the silicon layer portions of the trench side walls are oxidized. This step produces a bottleneck-shaped trench in which the trench side walls are wider adjacent the trench bottom than adjacent the top of the silicon layer portion of the trench side wall. After the step of oxidizing the silicon layer portion of the trench side walls, the next step in STI processing comprises filling the trenches with an oxide. The bottleneck shape of the trench makes filling the trench with an oxide difficult. This difficulty results in the formation of a seam in the center of the trench. This seam may open up during subsequent processing steps, leading to several problems. For instance, the seam might cause shorts between subsequently deposited poly gates if filled with polysilicon during the poly gate deposition step.

[0006] The deficiencies of the conventional processes of fabricating a trench on a silicon substrate using shallow trench isolation (STI) show that a need still exists for a process to eliminate the bottleneck-shaped trench produced after oxidizing the trench side walls. To overcome the shortcomings of the conventional processes, a new process is provided. An object of the present invention is to provide a process for fabricating a trench using STI in which the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom.

SUMMARY OF THE INVENTION

[0007] To achieve these and other objects, and in view of its purposes, the present invention provides a process for fabricating a trench having a tapered shape, side walls, and a bottom on a silicon substrate. The substrate has an exposed surface. The trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom. The process comprises the following steps:

[0008] forming an initial trench having initial trench side walls and a trench bottom extending from the exposed surface into an interior of the substrate;

[0009] implanting nitrogen ions on the initial trench side walls so that more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and

[0010] oxidizing the trench side walls, thereby creating a trench having the tapered shape.

[0011] In a preferred embodiment, the nitrogen ions are implanted on the initial trench side walls at an angle of from about 10 degrees to about 60 degrees relative to the exposed surface.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

BRIEF DESCRIPTION OF THE DRAWING

[0013] The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:

[0014]FIG. 1 shows in schematic representation a silicon substrate comprising a trench structure having side walls spaced further apart adjacent the trench bottom than adjacent the top of the silicon layer portion of the trench side wall;

[0015]FIG. 2A shows the structure of FIG. 1 after the trench has been filled with an oxide, producing a seam in the center of the trench;

[0016]FIG. 2B shows the structure of FIG. 2A after the seam has been filled with polysilicon, causing shorts between deposited poly gates;

[0017]FIG. 3 shows in schematic representation a silicon substrate;

[0018]FIG. 4 shows in schematic representation a silicon substrate having a trench with substantially perpendicular side walls;

[0019]FIG. 5 shows in schematic representation a top view of FIG. 4;

[0020]FIG. 6 illustrates the angle to the exposed surface in which nitrogen ions are implanted into the trench side walls;

[0021]FIG. 7 shows in schematic representation a silicon substrate having a tapered trench structure; and

[0022]FIG. 8 shows in schematic representation a tapered trench of a silicon substrate that has been filled with oxide.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will next be described with reference to the drawing in which similar numbers indicate the same elements in all figures. Such figures are intended to be illustrative rather than limiting and are included to facilitate the explanation of the apparatus of the present invention. The apparatus is made by the Shallow Trench Isolation (STI) process. The STI process comprises the steps of etching trenches, having side walls and bottoms, in the SOI substrate, oxidizing the silicon layer portions of the trench sidewalls, and filling the trenches with an oxide.

[0024] Referring now to the drawing, FIG. 1 shows a side view of a silicon substrate 1 after the steps of etching a trench 18 and oxidizing those portions 19, 20 of the side walls 24, 26 of the trench 18 comprising a silicon layer 14. The substrate 1 comprises a silicon wafer 10, a buried silicon oxide layer 12 formed on the silicon wafer 10, the silicon layer 14, a silicon nitride layer 16, and the trench 18.

[0025] After oxidizing the side walls 24, 26 of the trench 18, the next step in STI processing comprises filling the trench 18 with an oxide 32. As a result of the bottleneck-shape of the trench 18, a shape in which the width of the trench 18 is greater near the bottom then at the top, it is very difficult to fill the trench 18 with an oxide 32. This difficulty results in the formation of a seam 22 in the center of the trench 18 as illustrated in FIG. 2A.

[0026] The seam 22 may open up during subsequent processing steps, leading to several problems. For instance, FIG. 2B shows the structure of FIG. 2A after the seam 22 has been filled with polysilicon 40. The polysilicon 40 fills the seam 22 during deposition of poly gates 42 and may cause shorts between the poly gates 42.

[0027] The present invention provides a process for fabricating a trench 18 using shallow trench isolation (STI) in which the side walls 24, 26 of the trench 18 are spaced further apart adjacent the exposed surface than adjacent the trench bottom. Forming a trench 18 having this structure eliminates the formation of a seam 22 in the center of the trench 18 when the trench 18 is filled with an oxide 32.

[0028]FIG. 3 shows a side view of an embodiment of a silicon substrate comprising a silicon-on-insulator (SOI) substrate 1. In this embodiment, the substrate 1, having an exposed surface 8, comprises a silicon wafer 10, a buried silicon oxide layer 12 formed on the silicon wafer 10, a silicon layer 14, and a silicon nitride layer 16. A thin oxide layer 15 of from about 0.006 μm to about 0.01 μm can optionally be deposited between the silicon layer 14 and the silicon nitride layer 16 to reduce damage to the silicon layer 14 caused by deposition of the silicon nitride layer 16.

[0029] In a preferred embodiment, the thickness of the silicon oxide layer 12 is from about 0.1 μm to about 0.4 μm, the thickness of the silicon layer 14 is from about 0.1 μm to about 0.2 μm, and the thickness of the silicon nitride layer 16 is from about 0.1 μm to about 0.15 μm. In a more preferred embodiment, the thickness of the silicon oxide layer 12 is about 0.4 μm, the thickness of the silicon layer 14 is about 0.18 μm, and the thickness of the silicon nitride layer 16 is about 0.12 μm.

[0030]FIG. 4 shows a side view of a substrate 1 having an initial trench 18 extending into the interior of the substrate 1. In FIG. 4, standard photomasking and etching of the silicon substrate 1, through the silicon nitride layer 16, thin oxide layer 15 (if present), and silicon layer 14, results in an initial trench 18 having a bottom 21 and four initial trench side walls 24, 26, 28, and 30. Side walls 24 and 26 are shown in FIG. 4. FIG. 5 is a top view of FIG. 4 showing all four side walls 24, 26, 28, and 30 of initial trench 18. Initial trench side walls 24, 26, 28, and 30 are substantially perpendicular to the exposed surface 8 of the substrate 1.

[0031] To form the side walls 24, 26, 28, and 30 of initial trench 18 substantially perpendicular to the exposed surface 8, dry etching techniques, which are well known in the art, are preferred. The initial trench 18 can be cleaned using methods commonly known in the art, which typically include a preliminary step of plasma oxidation stripping or immersion in an inorganic resist stripper, followed by the removal of residual organic contaminants and the desorption of remaining atomic and ionic contaminants. S. Wolf & R. N. Tauber discuss such cleaning processes on pages 516-517 of their text, titled Silicon Processing for the VLSI Era, Volume 1—Process Technology (1986).

[0032]FIG. 6 shows the step of nitrogen ion implantation into the side walls 24, 26, 28, and 30 of initial trench 18. The nitrogen ions 50 are implanted at an angle (α) to the exposed surface 8 of the substrate 1. Ion implantation is a process in which energetic, charged atoms or molecules are directly introduced into a substrate, such as a silicon wafer. At varying orientations, nitrogen ions 50 are implanted on each side wall 24, 26, 28, and 30 of initial trench 18.

[0033] In one embodiment, a first position of the substrate 1 is determined so that nitrogen ions 50 are beamed at a direction parallel to side walls 28 and 30 onto side wall 24. The substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a second position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 24 and 26 onto side wall 28. The substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a third position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 28 and 30 onto side wall 26. The substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a fourth position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 24 and 26 onto side wall 30.

[0034] The optimal angle (α) of nitrogen ion implantation depends on the thickness of the silicon nitride layer 16 and the size of the trench 18. In a preferred embodiment, the side walls 24, 26, 28, and 30 of trench 18 are implanted with from about 5 keV to about 15 keV nitrogen ions 50 to a dose of from about 11014/cm2 to about 11015/cm2, and the nitrogen ions 50 are implanted at an angle (α) of from about 10 to about 60 degrees relative to the exposed surface 8. In a more preferred embodiment, the side walls 24, 26, 28, and 30 of trench 18 are implanted with about 10 keV nitrogen ions 50 to a dose of about 51014/cm2 at an angle (α) of about 20 degrees. By implanting nitrogen ions 50 at an angle (α) relative to the exposed surface 8, more nitrogen ions 50 are implanted adjacent the exposed surface 8 than adjacent the bottom 21 of the trench 18.

[0035]FIG. 7 shows a side view of a resulting tapered trench 18 a after oxidation of the side walls 24, 26, 28, and 30 of initial trench 18, resulting in tapered side walls 24 a and 26 a. The oxidation rate of the side walls 24, 26, 28, and 30 is affected by nitrogen ion concentration which proportionally retards trench side wall oxidation. The high concentration of nitrogen ions in the silicon nitride layer 16, which forms the portion of the side walls 24 and 26 adjacent the exposed surface 8, inhibits oxidation. In contrast, the silicon layer 14, which forms the portion of the side walls 24 a and 26 a adjacent trench bottom 21, has a lower concentration of nitrogen ions. Oxidation of the portion of the side walls 24 a and 26 a of the trench 18 a adjacent the silicon layer 14 results in oxide formation in proportion to nitrogen ion concentration.

[0036] Because the nitrogen ions 50 are implanted at an angle (α) relative to the exposed surface 8, more nitrogen ions 50 are implanted into the portion of the side walls 24 a and 26 a of the trench 18 a adjacent the silicon layer 14 and the bottom 21 of the trench 18 a than in the silicon nitride layer 16 portion of the side walls 24 and 26 adjacent the exposed surface 8, thereby producing a tapered shape upon oxidation. A portion of silicon layer 14 adjacent the side walls 24 a and 26 a of the trench 18 a is also oxidized. In a preferred embodiment, the side walls 24, 26, 28, and 30 are oxidized using dry oxygen at a temperature of about 1,000 C.

[0037] Following oxidation of the trench sidewalls 24, 26, 28, and 30, the trench is then filled with an oxide 32. FIG. 8 shows a side view of the tapered trench 18 a shown in FIG. 7 after tapered trench 18 a has been filled with the oxide 32. Following oxide deposition to fill the trench 18 a, steps known in the art can be used to complete an STI structure. In addition, the present invention can be used in bulk STI processes.

[0038] In one embodiment, a silicon substrate comprising an SOI substrate was formed by the following steps. A 0.4 μm layer of silicon oxide 12 was formed on a silicon wafer 1 and a 0.18 μm silicon layer 14 was formed on the silicon oxide layer 12 using the separation by implantation of oxygen (SIMOX) process. A 0.008 μm layer of silicon oxide (thin silicon oxide layer 15) was next formed on the silicon layer 14 followed by deposition of a 0.12 μm layer of silicon nitride 16 on the thin silicon oxide layer 15. An initial trench 18 extending from the exposed surface 8 of the substrate 1 into an interior of the substrate was formed by photomasking and plasma etching. The plasma etching was selective to stop at the silicon oxide layer 15, producing a trench depth of 0.308 μm. The initial trench side walls 24, 26, 28, and 30 were implanted with 10 keV nitrogen ions 50 to a dose of 51014/cm2 at an angle (α) of 30 degrees with respect to the exterior, exposed surface 8 of the substrate 1. The trench side walls 24, 26, 28, and 30 were next oxidized with dry oxygen at 1,000 C., resulting in a tapered trench 18 a in which the trench side walls 24, 26, 28, and 30 were spaced further apart adjacent the exposed surface 8 of the substrate 1 than adjacent the trench bottom 21.

[0039] Although illustrated and described above with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention.

Referenced by
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US7892939 *Mar 6, 2008Feb 22, 2011Infineon Technologies AgThreshold voltage consistency and effective width in same-substrate device groups
US8349698 *Jan 28, 2010Jan 8, 2013Sanken Electric Co., Ltd.Integrated semiconductor device and method of manufacturing the same
US20100244183 *Jan 28, 2010Sep 30, 2010Sanken Electric Co., Ltd.Integrated semiconductor device and method of manufacturing the same
EP2573807A1 *Sep 23, 2011Mar 27, 2013SoitecSemiconductor structure and process for bird's beak reduction
Classifications
U.S. Classification438/423, 257/E21.551, 257/E21.55
International ClassificationH01L21/762, H01L21/76
Cooperative ClassificationH01L21/76237, H01L21/76235
European ClassificationH01L21/762C8, H01L21/762C6A
Legal Events
DateCodeEventDescription
Oct 12, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100820
Aug 20, 2010LAPSLapse for failure to pay maintenance fees
Mar 29, 2010REMIMaintenance fee reminder mailed
Nov 18, 2005FPAYFee payment
Year of fee payment: 4