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Publication numberUS20010023123 A1
Publication typeApplication
Application numberUS 09/740,948
Publication dateSep 20, 2001
Filing dateDec 21, 2000
Priority dateDec 24, 1999
Also published asUS6362073
Publication number09740948, 740948, US 2001/0023123 A1, US 2001/023123 A1, US 20010023123 A1, US 20010023123A1, US 2001023123 A1, US 2001023123A1, US-A1-20010023123, US-A1-2001023123, US2001/0023123A1, US2001/023123A1, US20010023123 A1, US20010023123A1, US2001023123 A1, US2001023123A1
InventorsJin-woong Kim
Original AssigneeKim Jin-Woong
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for forming semiconductor device having low parasite capacitance using air gap and self-aligned contact plug
US 20010023123 A1
Abstract
Disclosed is a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method. A method for forming a semiconductor according to the present invention comprises the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers. Accordingly, the present invention using the air gap as a gap filling materials reduces the parasite capacitance loaded on a bit line and omits an additional gap filling process.
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Claims(10)
What is claimed is:
1. A method for forming a semiconductor, comprising the steps of:
forming a plurality of word lines over a semiconductor substrate spaced a distance from one another for providing a plurality of plugs each between two adjacent word lines and defining contact and non-contact areas;
forming an epitaxial layer in the plug in the contact area and an air gap in the plug in the non-contact area; and
forming an interlayer insulation layer over the plurality of word lines and exposed portions of the semiconductor substrate exposing at least a part of the epitaxial layer in each plug in the contact area.
2. The method as recited in
claim 1
, wherein the interlayer insulation layer includes PECVD (Plasma Enhanced Chemical Vapor Deposition) with low power of RF bias.
3. The method as recited in
claim 1
, wherein the step of forming an interlayer insulation layer includes etching by C or F-bearing gas plasma.
4. The method as recited in
claim 3
, wherein the step of forming an interlayer insulation layer includes etching with a gas selected from the group consisting of C2F6, C3F8, C4F8, C5F8 and C4F6 or a mixture thereof.
5. The method as recited in
claim 1
, wherein the step of forming an interlayer insulation layer includes etching by C, H or F-bearing gas plasma.
6. The method as recited in
claim 5
, wherein the C, H or F-bearing gas includes one selected from the group consisting of CH3F, CH2F2, C2HF5 and C3H2F6 or a mixture thereof.
7. The method as recited in
claim 3
, wherein the C or F-bearing gas plasma contains an inert gas.
8. The method as recited in
claim 1
, wherein the step of forming an interlayer insulation layer includes isotropic dry-etching.
9. The method as recited in
claim 1
, further comprising forming a spacer on each sidewall of each word line.
10. The method as recited in
claim 9
, wherein the spacer includes an oxide or nitride layer.
Description
FIELD OF THE INVENTION

[0001] The present invention relates to a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method.

DESCRIPTION OF THE PRIOR ART

[0002] Generally, the refresh time, which is one of the most important features in semiconductor memory device, may be determined by a leakage current which is caused by a drain damage and this drain damage is often generated at the time of forming a charge storage node contact for electrically connecting the charge storage electrode to the drain of a transistor. The resolution of current lithography techniques may prevent a misconnection in 16M DRAM manufacturing processes or less, which may be caused by an undesired connection to other layers at sidewalls of a contact hole, but the space between the contact hole and adjacent conducting layers in an interlayer insulating layer becomes narrower with the development of the integrated circuits.

[0003] The contact is minimized in order to solve the abovementioned problem and this problem may be solved somewhat by modifying the exposure method in a step-and-repeat projection equipment (i.e., stepper), modifying mask to define the contact hole region, or using a self-aligned contact (hereinafter, referred to as SAC).

[0004] The most highlighted process is a nitride barrier SAC (hereinafter, referred to as NBSAC) process, in which a nitride layer is used as an etching barrier layer when an oxide layer is etched for forming the contact hole. The NBSAC process may be divided into two etching processes, i.e., oxide and nitride etching processes. In the oxide etching process, polymer-inducing gases, such as C3F8 and C4F8, are have been used in order to improve a selective etching rate to the nitride layer. The C3F8 and C4F8 gases induce a lot of polymer and then a high selective etching rate to the nitride layer may be obtain, but these gases may provoke a problem in that the oxide layer within the contact hole is not removed completely because the polymer may cause an etching stop of the oxide layer. Since the selective etching rate to the nitride layer and the etching stop of the oxide layer within the contact hole are contrary to each other, reappearance of the semiconductor devices may deteriorate and a process window of the contact hole may be narrow.

[0005] To make the process window broad, the processing conditions for etching the oxide layer is controlled by a polymer decreasing method. Accordingly, in the case where the oxide layer etching process is carried out by the polymer decreasing method, it requires that the nitride layer should be thick. However, the increase of the thickness of the nitride layer causes the contact area to be diminished and an isotropic etching process is applied to the nitride layer in order to make up for the diminution of the contact area.

[0006] Further, since the oxide layer under the nitride layer is used as an electrical insulating layer, the etching process requires that the oxide layer should be controlled by a high selective etching rate in order not to be damaged and a portion of a semiconductor substrate may be exposed at the time of etching an oxide layer in a periphery circuit area, the oxide etching process to minimize the loss of the exposed semiconductor substrate is required.

[0007] However, a conventional ion induced etcher to etch the nitride layer may not obtain such a high selective etching rate in the isotropic etching process. The recently highlighted radical etcher using the etchants, such as NF3 and CF4 and SF6, provides an isotropic etching process and a high selective etching rate to the oxide layer, but it does not provide a high selective etching rate to a silicon layer (i.e., silicon wafer) because the etching process uses the fluorine-bearing etchants. Also, the etching rate of the radical etching equipment is determined by the coherence of the oxide, nitride and silicon layers because these etchants may etch all of the oxide, nitride and silicon layers. That is, in the case where the oxide layer, nitride layer and silicon layer may be placed in the order of coherence, it is impossible to obtain a high selective etching rate to a silicon layer because the silicon layer is etched most rapidly.

[0008] As a result, the conventional NBSAC process is not sufficient for a high selective etching rate and it is more difficult to obtain a processing margin in etching the oxide, nitride and silicon layers with the decrease of the yield of the semiconductor devices.

SUMMARY OF THE INVENTION

[0009] It is, therefore, an object of the present invention to provide a method for forming self-aligned contacts using a selective epitaxial growing method.

[0010] It is another object of the present invention to provide a method for improving electrical characteristics of a semiconductor device by reducing parasite capacitance.

[0011] In the present invention, a contact plug is formed on a contact area using a selective epitaxial growing method and a self-aligned contact which is formed by a selective etching rate between an epitaxial layer and an oxide layer.

[0012] In accordance with an aspect of the present invention, there is provided a method for forming a semiconductor comprising the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Other objects and aspects of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

[0014]FIGS. 1A and 1B are cross-sectional views illustrating a method for forming a self-aligned contact with an air gap according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the present invention will be described in detail referring to the accompanying drawings.

[0016]FIGS. 1A and 1B illustrate a method for forming a self-aligned contact with an air gap according to the present invention.

[0017] First, referring to FIG. 1A, field oxide layers 13 are formed in a semiconductor substrate 11 in order to define active regions and field regions (non-active regions). A conduction layer 15 for a gate electrode is formed on the semiconductor substrate 11 and a mask insulation layer 17, such as a nitride or oxide layer, is formed on the conduction layer 15. The mask insulation layer 17 and the conduction layer 15 are patterned in a predetermined size and an amorphous carbon layer for spacers 19 are formed on sidewalls of the mask insulation layer 17 and the conduction layer 15, thereby exposing portions of the semiconductor substrate 11 between the patterned stacks. At this time, the spacers 19 are made of as an oxide or nitride layer.

[0018] Referring to FIG. 1B, epitaxial layers 23 for a contact plug are formed on the exposed portion of the semiconductor substrate 11 by the selective epitaxial growing method. In the selective epitaxial growing method, the epitaxial layers 23 are formed only on the semiconductor substrate 11, such as a silicon or silicon-germanium layer, because the mask insulation layer 17 and the spacers 19 function as barriers to epitaxial growing. In the preferred embodiment, an insulation layer or a nitride layer (not shown) as a barrier layer to the epitaxial growth is formed on non-contact areas and this barrier layer is removed after forming the epitaxial layers 23.

[0019] After removing the barrier layer to the epitaxial growth, an interlayer insulation layer 25, an oxide layer, is formed on the resulting structure though the PECVD (Plasma Enhanced Chemical Vapor Deposition) method. When the interlayer insulation layer 25 is formed by the PECVD method, the non-contact areas between the word lines (the conduction layer 15 for a gate electrode) are filled with an air gap 21 because the PECVD method has a demerit in topology of the interlayer insulation layer 25. It is quite different from what is required in the general semiconductor processing techniques. Especially, in the PECVD method according to the present invention, the low power of RF bias is kept for poor topology of the interlayer insulation layer 25. The use of the air gap 21 may remove a gap filling process required in a conventional semiconductor processing method. In DRAM memory devices, this air gap 21 may reduce parasite capacitance. Typically, in the case where an oxide layer or a nitride layer, which has higher dielectric constant than the air, is used a gap filling materials, these materials may increase the parasite capacitance and require much more refresh operations of memory devives. However, since the present invention uses the air gap 21 as a gap filling materials, the parasite capacitance loaded on a bit line may be reduced and an additional gap filling process is not required.

[0020] After forming the interlayer insulation layer 25 having poor topology, the interlayer insulation layer 25 is patterned using an etching mask (not shown) so that the top surface 27 of the epitaxial layers 23 is exposed between the patterns formed by the interlayer insulation layer 25. At this time, although the patterns of the interlayer insulation layer 25 are misaligned, an undesired interconnection of the conduction layer 15 and the following conduction layer for a charge storage electrode may be prevented.

[0021] On the other hand, the interlayer insulation layer 25 is etched by carbon and fluorine-bearing gases and particularly, C2F6, C3F8, C4F8, C5F8, C4F6 and their mixtures may be used for a high selective etching rate to the interlayer insulation layer 25 against the interlayer insulation layer 25. Also, C, H and F-bearing gases, such as CH3F, CH2F2, C2HF5, C3H2F6 and their mixtures, may be used to increase the selective etching rate to the interlayer insulation layer 25. In the preferred embodiment, an inert gas, such as Ar or He, may be contained to stabilize plasma while the interlayer insulation layer 25 is etched and the isotropic dry-etching process is applied to the interlayer insulation layer 25 to remove polymer which may cause the epitaxial layers 23 to be damaged.

[0022] As apparent from the above, the present invention may omit an additional gap filling process with an epitaxial layer growth of a charge storage electrode. Accordingly, this reduced parasite capacitance improves operation speed of the memory devices and the epitaxial layer provides sufficient processing margin which increases the yield of the semiconductor memory devices.

[0023] Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7071532Sep 30, 2003Jul 4, 2006International Business Machines CorporationAdjustable self-aligned air gap dielectric for low capacitance wiring
US7105431Aug 22, 2003Sep 12, 2006Micron Technology, Inc.Masking methods
US7115524May 17, 2004Oct 3, 2006Micron Technology, Inc.Methods of processing a semiconductor substrate
US7354631Nov 6, 2003Apr 8, 2008Micron Technology, Inc.Chemical vapor deposition apparatus and methods
US7358148May 5, 2006Apr 15, 2008International Business Machines CorporationAdjustable self-aligned air gap dielectric for low capacitance wiring
US7432212Jul 20, 2006Oct 7, 2008Micron Technology, Inc.Methods of processing a semiconductor substrate
US7459742 *Dec 27, 2006Dec 2, 2008Micron Technology, Inc.Method of manufacturing sidewall spacers on a memory device, and device comprising same
US7470606Jul 31, 2006Dec 30, 2008Micron Technology, Inc.Masking methods
US7601591Jan 28, 2008Oct 13, 2009Micron Technology, Inc.Method of manufacturing sidewall spacers on a memory device, and device comprising same
WO2005022617A1 *Aug 12, 2004Mar 10, 2005Micron Technology IncMasking methods
Classifications
U.S. Classification438/587, 257/E21.166, 257/E21.586, 257/E21.252, 257/E21.581
International ClassificationH01L21/768, H01L21/8242, H01L21/302, H01L27/088, H01L27/108, H01L21/311, H01L21/8234, H01L21/285, H01L21/28, H01L21/3065, H01L23/522
Cooperative ClassificationH01L21/28525, H01L21/76879, H01L21/31116, H01L21/7682
European ClassificationH01L21/311B2B, H01L21/768B6, H01L21/768C4B, H01L21/285B4B
Legal Events
DateCodeEventDescription
Aug 1, 2013FPAYFee payment
Year of fee payment: 12
Aug 26, 2009FPAYFee payment
Year of fee payment: 8
Sep 2, 2005FPAYFee payment
Year of fee payment: 4
Jul 1, 2003CCCertificate of correction
Apr 26, 2001ASAssignment
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, JIN-WOONG;REEL/FRAME:011766/0753
Effective date: 20010420
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. SAN 136-1
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, JIN-WOONG /AR;REEL/FRAME:011766/0753