Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010023994 A1
Publication typeApplication
Application numberUS 09/799,803
Publication dateSep 27, 2001
Filing dateMar 7, 2001
Priority dateMar 7, 2000
Also published asUS6777264, US20030020177
Publication number09799803, 799803, US 2001/0023994 A1, US 2001/023994 A1, US 20010023994 A1, US 20010023994A1, US 2001023994 A1, US 2001023994A1, US-A1-20010023994, US-A1-2001023994, US2001/0023994A1, US2001/023994A1, US20010023994 A1, US20010023994A1, US2001023994 A1, US2001023994A1
InventorsTakahiro Oka
Original AssigneeTakahiro Oka
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and the method for manufacturing the same
US 20010023994 A1
Abstract
A semiconductor device includes, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed, and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the first chip top surface is fixed on the die pad bottom surface, the second chip bottom surface is fixed on the die pad top surface.
Images(7)
Previous page
Next page
Claims(21)
What is claimed is:
1. A semiconductor device comprising:
a die pad having a die pad top surface and a die pad bottom surface;
a first semiconductor chip having a first chip top surface and a first chip bottom surface, and the first chip top surface having a first plurality of electrodes thereon,
a second semiconductor chip having a second chip top surface and a second chip bottom surface, the second chip top surface having a second plurality of electrodes thereon, and the second semiconductor chip being smaller than the first semiconductor chip;
wherein the first chip top surface is fixed under the die pad bottom surface, the second chip bottom surface is fixed over the die pad top surface.
2. The semiconductor device according to
claim 1
, wherein the second semiconductor chip is smaller than the die pad.
3. The semiconductor device according to
claim 1
, wherein the area of the die pad bottom surface is smaller than half of the area of the first chip top surface.
4. The semiconductor device according to
claim 1
, wherein the first semiconductor chip is a logic semiconductor chip, and the second semiconductor chip is a memory semiconductor chip.
5. The semiconductor device according to
claim 1
, further comprising inner leads, wherein the inner leads and the die pad are formed substantially at the same level.
6. The semiconductor device according to
claim 1
, wherein the first plurality of electrodes are disposed on the outside of a region that is defined by an edge of the second semiconductor chip.
7. The semiconductor device according to
claim 1
, wherein the first plurality of electrodes are disposed on the outside of the die pad.
8. The semiconductor device according to
claim 6
, further comprising a metal wire which electrically connects at least one of the first plurality of electrodes to at least one of the second plurality of electrodes.
9. The semiconductor device according to
claim 3
, further comprising
a first metal wire which connects at least one of the first plurality of electrodes to the inner leads;
a second metal wire which connects at least one of the second plurality of electrodes to the inner leads.
10. The semiconductor device according to
claim 8
, wherein the first metal wire and the second metal wire are formed in a side of the die pad top surface.
11. The semiconductor device according to
claim 1
, further comprising:
a molding resin that molds the first semiconductor chip, the second semiconductor chip, and the die pad,
wherein the thickness of the resin over the second semiconductor chip is substantially the same as the thickness of the resin under the first semiconductor chip.
12. A method for manufacturing the semiconductor device comprising
forming a first adhesive layer over a die pad bottom surface;
forming a second adhesive layer over a die pad top surface;
fixing a top surface of a first semiconductor chip on the first adhesive layer, the top surface of the first semiconductor chip having a first plurality of electrodes thereon, and
fixing a bottom surface of a second semiconductor chip, which is smaller than the first semiconductor chip, on the second adhesive layer, a top surface of the second semiconductor chip having a second plurality of electrodes thereon.
13. The method according to
claim 12
, wherein forming the second adhesive layer is performed after fixing the first semiconductor layer.
14. The method according to
claim 12
, wherein the first adhesive layer and the second adhesive layer have a thermosetting characteristic.
15. The method according to
claim 14
, wherein a second hardening temperature of the second adhesive layer is higher than a first hardening temperature of the first adhesive layer.
16. The method according to claim. 12, wherein the first adhesive layer and the second adhesive layer have a thermoplastic characteristic.
17. The method according to
claim 16
, wherein a second softening temperature of the second adhesive layer is lower than a first softening temperature of the first adhesive layer.
18. The method according to
claim 14
, wherein the first adhesive layer and the second adhesive layer are partly formed on the die pad top surface and the die pad bottom surface, a first portion on the die pad bottom surface, which corresponds to the first adhesive layer is different from a second portion on the die pad top surface which corresponds to the second adhesive layer.
19. The method according to
claim 16
, wherein the first adhesive layer and the second adhesive layer are partly formed on the die pad top surface and the die pad bottom surface, a first portion on the die pad bottom surface, which corresponds to the first adhesive layer is different from a second portion on the die pad top surface which corresponds to the second adhesive layer.
20. The method according to
claim 12
, further comprising;
connecting some of the first plurality of electrodes on the first semiconductor chip to some of the second plurality of electrodes on the second semiconductor chip,
wherein the electrodes on the first semiconductor chip are disposed on the outside of the region that is defined by an edge of the second semiconductor chip.
21. The method according to
claim 12
, further comprising;
first connecting at least one of the first plurality of electrodes on the first semiconductor chip to at least one of inner leads;
second connecting at least one of the second plurality of electrodes on the second semiconductor chip to at least one of inner leads,
wherein said first connecting and second connecting is performed subsequently in the same step.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    The present invention relates to a semiconductor device, and to the method for manufacturing the same.
  • [0002]
    [0002]FIG. 9 shows a schematic diagram of a conventional semiconductor device molded with resin. FIG. 10 shows a top-view of the semiconductor device. These drawings show a Quad Flat Package (QFP).
  • [0003]
    This semiconductor device has a first semiconductor chip 91, a second semiconductor chip 92, a die pad 93, a first adhesive layer 94, a second adhesive layer 95, electrodes 96 on the first semiconductor chip, electrodes 97 on the second semiconductor chip, inner leads 98, metal wires 99, 910, a package portion 912, outer leads 913, and a pad support portion 914. The semiconductor chips 91 and 92 are stacked on a die pad 93.
  • [0004]
    The die pad 93 is lower than the inner leads 98 as shown in FIG. 9 and FIG. 10. The hanging portion of the die pad 93 is bent, and the die pad and the inner leads are not in the same level. The bent portion is indicated by reference numeral 1011 in FIG. 10. This structure is called downset. The thickness t1 of the resin on the semiconductor chip 92 is the same as the thickness t2 of the resin under the die pad 93 in the conventional design. The resin is filled proportionally during transfer molding because the thickness of resin on the semiconductor chip 92 and the thickness of resin under the die pad 93 are the same. Therefore, a short-circuit of wires on the semiconductor chip 91 and the semiconductor chip 92 is prevented. The warp of the package is also prevented.
  • [0005]
    The semiconductor chip 91 is fixed over the die pad 93 by the first adhesive layer 94. The semiconductor chip 92 is fixed over the semiconductor chip 91 by the second adhesive layer 5.
  • [0006]
    The electrodes 96, 97 on each semiconductor chips are connected to inner leads 98 via metal wires 99, 910. For example, gold wires connect electrodes and inner leads. Some electrodes 97 on the semiconductor chip 92 are connected to the electrodes 96 on the semiconductor chip 91. After the wire bonding, a resin (for example, epoxy resin) is molded on semiconductor chips. After the forming of the package portion 12, the outer leads 13 are plated with solder. The outer leads 13 are then transformed into a predetermined form.
  • SUMMARY OF THE INVENTION
  • [0007]
    An object of the present invention is to provide a semiconductor device and the method for manufacturing the same that do not need a downset process. Therefore the yield is improved during the formation of a lead frame.
  • [0008]
    According to an embodiment of this invention, a semiconductor device comprises, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the top surface of the first semiconductor chip is fixed on the bottom surface of the die pad, the bottom surface of the second semiconductor chip is fixed on the top surface of the die pad.
  • [0009]
    A method for manufacturing the semiconductor device comprises forming a first adhesive layer on a bottom surface of a die pad, forming a second adhesive layer on a top surface of the die pad, fixing a top surface of a first semiconductor chip on the first adhesive layer, fixing a bottom surface of a second semiconductor chip which is smaller than the first semiconductor chip on the second adhesive layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    [0010]FIG. 1 shows a cross sectional view of a semiconductor device of a first preferred embodiment.
  • [0011]
    [0011]FIG. 2 shows a perspective diagram from the top view of the semiconductor device in the first preferred embodiment.
  • [0012]
    [0012]FIG. 3 shows a cross sectional view of a semiconductor device of a second preferred embodiment.
  • [0013]
    [0013]FIG. 4 shows a perspective diagram from the top view of the semiconductor device of the second preferred embodiment.
  • [0014]
    [0014]FIG. 5 shows a cross sectional view of the method for manufacturing the semiconductor device of the third p referred embodiment.
  • [0015]
    [0015]FIG. 6 shows a cross sectional view of the method for manufacturing a semiconductor device of the fourth preferred embodiment.
  • [0016]
    [0016]FIG. 7 shows a cross sectional view of the method for manufacturing a semiconductor device of the fifth preferred embodiment.
  • [0017]
    [0017]FIG. 8 shows a cross sectional view diagram of the method for manufacturing a semiconductor device of the sixth preferred embodiment.
  • [0018]
    [0018]FIG. 9 shows a cross sectional view of a conventional semiconductor device.
  • [0019]
    [0019]FIG. 10 shows a top view of the conventional semiconductor device.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0020]
    Preferred embodiments are described below using drawings.
  • [0021]
    [0021]FIG. 1 shows a cross sectional view of the semiconductor device of a first preferred embodiment. FIG. 2 shows a perspective diagram from the top view of the semiconductor device in the first embodiment.
  • [0022]
    This semiconductor device has a first semiconductor chip 1, a second semiconductor chip 2, a die pad 3, a first adhesive layer 4, a second adhesive layer 5, electrodes 6 on the first semiconductor chip, electrodes 7 on the second semiconductor chip, inner leads 8, metal wires 9, 10, a package portion 12, outer leads 13, and a pad support portion 14. The package is not limited to the drawings. For example, the inner leads 8 can be formed with an interconnection on Ball Grid Array (BGA) substrate.
  • [0023]
    The die pad 3 for mounting a semiconductor chip is not downset. The pad support portion 14 is not bent. Therefore, the die pad 3 and the inner leads 8 are formed on the same level. The second adhesive layer 5 is formed on the top surface of the die pad 3 (the die pad top surface) and the first adhesive layer 4 is formed on the bottom surface of the die pad 3 (die pad bottom surface). That is to say, the die pad 3 is disposed between the first and second adhesive layers.
  • [0024]
    The first semiconductor chip 1 is fixed on the first adhesive layer 4. The top surface of the first semiconductor chip 1 (first chip top surface) touches the first adhesive layer 4, and the first chip top surface is the main surface on which the circuits and electrodes are formed.
  • [0025]
    The second semiconductor chip 2 is fixed on the second adhesive layer 5. The bottom surface of the second semiconductor chip 2 (second chip bottom surface) touches the second adhesive layer 5, and the circuits are not formed on this bottom surface.
  • [0026]
    The electrodes 6 on the first semiconductor chip are connected to inner leads 8 via metal wires 9. The electrodes 7 on the second semiconductor chip are connected to inner leads 8 via metal wires 10. Some electrodes 6 on the first semiconductor chip 1 are connected to the electrodes 7 on the second semiconductor chip 2 via wires 11. The electrical signal of the semiconductor chips 1, 2 is outputted through the electrodes 6, 7, wires 9, 10, 11, inner leads 8, and outer leads 13.
  • [0027]
    The package portion 12 is formed by molding resin (for example, epoxy resin) on predetermined portion of the semiconductor device.
  • [0028]
    The total thickness of the first adhesive layer 4 plus the first semiconductor chip 1 is the same as the total thickness of the second adhesive layer 5 plus the second semiconductor chip 2. Therefore, The thickness t1 of the resin on the second semiconductor chip 2 is the same as the thickness t2 of the resin under the first semiconductor chip 1.
  • [0029]
    The die pad 3 is disposed between the first semiconductor chip 1 and the second semiconductor chip 2. Therefore, the hanging portion of the die pad is not have to be bent.
  • [0030]
    The first semiconductor chip 1 is wider than the second semiconductor chip 2 and the die pad 3 in this embodiment. The electrodes 6 on the first semiconductor chip 1 are disposed outside of the region that is defined by the edge of the second semiconductor chip 2. The electrodes 6 on the first semiconductor chip and the electrodes 7 on the second semiconductor chip do mot overlap from the top view as shown in FIG. 2.
  • [0031]
    The first chip top surface 1 is fixed on the first adhesive layer 4, and the second chip bottom surface 2 is fixed on the second adhesive layer 5. Therefore, all of the electrodes 6, 7 are not covered with the die pad 3. It is desirable that the difference of the size between the first semiconductor chip 1 and the second semiconductor chip 2 is at least 0.3 mm in each side. This is a minimum width to form an interconnecting wire between the electrodes 6 on the first semiconductor chip 1 and the electrodes 7 on the second semiconductor chip 2.
  • [0032]
    The electrodes 7 on the second semiconductor chip and the electrodes 6 on the first semiconductor chip 1 do not overlap. Therefore, all of the wire bonding to connect electrodes 6 and electrodes 7, electrodes 6 and inner lead 8, and electrodes 7 and inner lead 8 are performed in the same step. The wire bonding is performed from the same side (die pad top surface side) in the first preferred embodiment, and there is no wire connected by wire bonding from another side (die pad bottom surface side), and the wire, which has a loop summit at the die pad bottom surface, does not exist. Therefore, the thickness of the semiconductor device can be decreased.
  • [0033]
    The die pad top surface 3 is preferably wider than the bottom surface of the semiconductor chip 2. The die pad bottom surface 3 is preferably smaller than the top surface of the semiconductor chip 1.
  • [0034]
    In the first preferred embodiment, the adhesive layer 5 is prevented from running onto the top surface of the semiconductor chip 1 because the die pad 3 is wider than the semiconductor chip 2, when the semiconductor chip 2 is fixed.
  • [0035]
    An insulating adhesive is used as the adhesive layer 4 because the adhesive layer 4 bonds the first chip top surface, which is formed with circuit, to the die pad 3.
  • [0036]
    A conductive adhesive (for example solder paste) can be used as the adhesive layer 5 because the second chip bottom surface 2 is fixed on the die pad 3. Therefore, electric potential can be applied to the second semiconductor chip accordingly. For example, a semiconductor device, which has a logic semiconductor chip and a memory semiconductor device, is suitable for use a conductive adhesive as the adhesive layer 5. A certain potential should be applied to the substrate of a conventional memory semiconductor chip in order to stabilize an operation, on the other hand, there are many cases that the logic semiconductor chip does not need some potential at its substrate, therefore, the logic semiconductor chip can be used as the first semiconductor chip and the memory semiconductor chip can be used as the second semiconductor chip in the first preferred embodiment.
  • [0037]
    There are some effects described below according to this preferred embodiment.
  • [0038]
    This semiconductor device has a simple structure without downset. Therefore the yield of the lead-frame is improved during manufacturing, and the cost of manufacturing is declined.
  • [0039]
    The transformation of the lead frame is decreased during the carry and the molding. Because this semiconductor device does not have an downset structure. Therefore the yield of the assembly process is improved, and the cost of manufacturing is declined.
  • [0040]
    There is a die pad 3 between the first semiconductor chip 1 and the second semiconductor chip 2. Therefore, the noises between the semiconductor chips 1, 2 is decreased, and high speed signals can be applied to the semiconductor chips.
  • [0041]
    The area of the die pad 3 relates to the effect of noise reduction.
  • [0042]
    The second preferred embodiment is described below.
  • [0043]
    [0043]FIG. 3 shows a cross sectional view of the semiconductor device of the second preferred embodiment. FIG. 4 shows a perspective diagram from the top view of the semiconductor device in the second embodiment. The same reference numerals are applied for the elements those are described in the first embodiment.
  • [0044]
    The die pad 3 of the second preferred embodiment is not downset either.
  • [0045]
    The area of the die pad 3 is much smaller than the areas of the first semiconductor chip 1 and the second semiconductor chip 2. It is desirable that the area of the die pad 3 is smaller than half of the top surface area of the first semiconductor chip 1. The first chip top surface 1 is fixed on the die pad 3.
  • [0046]
    The die pad 3 is smaller than the semiconductor chips 1 and 2 in this embodiment. The contact area between the first semiconductor chip 1 and the die pad 3 shrinks because the area of the die pad 3 is small. Therefore the stress and the damage on the surface of the first semiconductor chip are decreased.
  • [0047]
    Consequently, this semiconductor device of the embodiment does not need a coating layer on the first chip top surface 1 because the passivation layer is enough to protect the top surface from damage. The coating process is reduced and the cost of manufacturing declines.
  • [0048]
    The amount of adhesive required to fix the semiconductor chips is reduced because the area of the die pad 3 is small. It also becomes easy to spread the adhesive uniformly on the total surface of the die pad 3. Therefore the adhesive strength is enough to fix each semiconductor chip.
  • [0049]
    The electrodes 7 on the second semiconductor chip and the electrodes 6 on the first semiconductor chip 1 do not overlap in the same way as the first embodiment. Therefore, all of the wire bonding are performed substantially in the same step.
  • [0050]
    In other words, all of the wire bonding are performed without a step of turning over the semiconductor device.
  • [0051]
    The conductive adhesive can be used as the adhesive layer 5 in the second embodiment in the same way as the first embodiment. Therefore, the logic semiconductor chip can be used as the first semiconductor chip and the memory semiconductor chip can be used as the second semiconductor chip in the first preferred embodiment.
  • [0052]
    FIGS. 5A-5D show cross sectional views of the method for manufacturing the semiconductor device according to the third preferred embodiment. The same reference numerals are applied for the elements those are described in the first preferred embodiment.
  • [0053]
    The die pad 3, which is not downset, is prepared as shown in FIG. 5A. The insulating adhesive layer (first adhesive layer) 4 is formed on a bottom surface of the die pad 3. The insulating or conductive adhesive layer 5 (second adhesive layer) is formed over a top surface of the die pad 3. Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape may be used as these adhesive layers. These adhesive layers preferably have some viscosity before hardening. This viscosity allows a semiconductor chip to be aligned on the die pad 3.
  • [0054]
    The first semiconductor chip 1 is put on the die pad bottom surface as shown in FIG. 5B. The first semiconductor chip 1, the first adhesive layer 4 and the die pad 3 are heated from the lower side of the first semiconductor chip 1. The adhesive layer 4 fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
  • [0055]
    The second semiconductor chip 2 is put over the die pad top surface 3 as shown in FIG. 5C. The second semiconductor chip 2, the second adhesive layer 5 and the die pad 3 are heated from the lower side of the first semiconductor chip 2. The adhesive layer 5 fixes the second semiconductor chip 2 on the die pad 3 after this heat treatment.
  • [0056]
    The final hardening of the adhesive layers is performed, and the semiconductor chips are perfectly fixed on the die pad 3. This fixing process is called a die bonding process. Electrodes 6, 7 on the semiconductor chips 1, 2 are then electrically connected to inner leads 8 or another electrode via metal wire 8, 9. Then, the molding process is performed.
  • [0057]
    There are some effects described below according to this preferred embodiment.
  • [0058]
    The manufacturing step is simplified because the downset process is lessened. Therefore the yield of the lead-frame is improved during manufacturing, and the cost of manufacturing is reduced.
  • [0059]
    The adhesive layers are formed before the semiconductor chips are put on the die pad 3. Therefore the spread of the adhesive layer can be easily controlled when the semiconductor chips are pressed on the die pad 3. The possibility that the adhesive layer 5 runs onto the top surface of the semiconductor chip 1 is decreased. Therefore the distance between the edge of the first semiconductor chip 1 and the edge of the second semiconductor chip 2 is minimized. This minimized distance means the shortest distance that the electrodes 6 on the first semiconductor chip 1 can be connected to the electrodes 7 on the second semiconductor chip 2 via metal wire.
  • [0060]
    The wire bonding ban be performed from the same side (die pad top surface side) and in the same step in the first preferred embodiment. The wire, which has a loop summit at the die pad bottom surface, does not exist. Therefore, turning over the semiconductor device does not have to be performed to perform wire bonding of another side.
  • [0061]
    [0061]FIG. 6 shows a cross sectional view of the method for manufacturing the semiconductor device of a fourth preferred embodiment. The same reference numerals are applied for the elements those are described in the first preferred embodiment.
  • [0062]
    The die pad 3, which is not downset, is prepared. The insulating adhesive layer 4 (first adhesive layer) is formed on a bottom surface of the die pad 3. The insulating or conductive adhesive layer 5 (second adhesive layer) is formed on a top surface of the die pad 3. Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape may be used as these adhesive layers. These adhesive layers have some viscosity before hardening. This viscosity allows aligning a semiconductor chip on the die pad 3.
  • [0063]
    The first adhesive layer 64 and the second adhesive layer 65 are partly formed on each surface in this embodiment. The portion on which the first adhesive layer 64 is formed in the die pad bottom surface does not correspond to the portion on which the second adhesive layer 65 is formed on the die pad top surface.
  • [0064]
    For example, thermosetting adhesive is used as the adhesive layers 64, 65. When the first semiconductor chip 1 is fixed, only the first portion, which the first adhesive layer 64 is formed on, are heated. The retained heat does not have an influence on the second adhesive layer 65. Therefore the second adhesive layer 65 is protected from the changing of the viscosity property.
  • [0065]
    The method of manufacturing of the fourth embodiment is described below. This method is approximately the same as the third embodiment.
  • [0066]
    The adhesive layers 64, 65 are formed on each surface of the die pad 3 as described above.
  • [0067]
    The first semiconductor chip 1 is put on the die pad bottom surface. The first adhesive layer 64 and the portions, those preferably corresponds to the first adhesive layer 64 in the first semiconductor chip 1 and the die pad 3, are heated. The adhesive layer 64 fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
  • [0068]
    The second semiconductor chip 2 is put over the die pad top surface 3. The second semiconductor chip 2, the second adhesive layer 65 and the die pad 3 are heated from the lower side of the first semiconductor chip 1. The second adhesive layer 65 fixes the second semiconductor chip 2 on the die pad 3 after this heat treatment.
  • [0069]
    The final hardening of the adhesive layers is performed, and the first and second semiconductor chips are perfectly fixed on the die pad 3.
  • [0070]
    The second adhesive layer 65 and the corresponding portion in the die pad 3 are not heated directory during the heat treatment to fix the first semiconductor chip 1. Therefore the second adhesive layer 65 is protected from the changing of the viscosity property.
  • [0071]
    [0071]FIG. 7 shows a cross sectional view of the method for manufacturing the semiconductor device of a fifth preferred embodiment. The same numerals are applied for the elements those are described in the first embodiment.
  • [0072]
    The die pad 3, which is not downset, is prepared. The insulating adhesive layer 74 (first adhesive layer) is formed on the bottom surface of the die pad 3. The insulating or conductive adhesive layer 65 (second adhesive layer) is formed on the top surface of the die pad 3. Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape can be used as these adhesive layers 64, 65. These adhesive 64, 65 layers preferably have some viscosity before hardening. This viscosity allows a semiconductor chip to be aligned on the die pad 3.
  • [0073]
    The softening (or hardening) temperature of the first adhesive layer 74 is different from that of the second adhesive layer 75 in this embodiment.
  • [0074]
    For example, the same thermoplastic adhesive can be used as the adhesive layers. The first semiconductor chip 1 is fixed before the second semiconductor chip 2 is fixed. Then the second adhesive layer is softened by heating from the lower side of the first semiconductor chip 1. The first adhesive layer 1 may be softened during this second heat treatment. The softening of the first adhesive layer 74 during the second heat treatment is not preferable to fix the first semiconductor chip tightly and precisely. If the softening temperature of the first adhesive layer is higher than that of the second adhesive layer, this problem does not occur.
  • [0075]
    For example, if the softening temperature of the first adhesive layer 74 is 100 C. and the softening temperature of the second adhesive layer is 50 C. the fixing would be performed more tightly.
  • [0076]
    Therefore using different adhesive layers respectively having different softening temperature for each surface makes the fixing of the semiconductor chips more precise and tight.
  • [0077]
    The method of manufacturing of the fifth embodiment using thermoplastic adhesive as an example is described below in order to more fully illustrate this embodiment. This is the opposite example of thermo characteristic to the above example. This method is substantially similar to the third embodiment.
  • [0078]
    The die pad 3, which is not downset, is prepared. The insulating adhesive layer 74 (first adhesive layer) is formed on bottom surface of the die pad 3. The softening temperature of the first adhesive layer is about 50 C. The insulating or conductive adhesive layer 75 (second adhesive layer) is formed on top surface of the die pad 3. The softening temperature of the second adhesive layer is about 100 C.
  • [0079]
    The first semiconductor chip 1 is put on the die pad bottom surface 3. The first semiconductor chip 1, the first adhesive layer 4 and the die pad 3 are heated at the temperature of 50 C. from the lower side of the first semiconductor chip 1. The adhesive layer 4 is hardened because this is a thermosetting adhesive, and it fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment. The second adhesive layer is not hardened during this heat treatment because softened temperature is higher than about 50 C.
  • [0080]
    The second semiconductor chip 2 is put over the die pad top surface 3. The second semiconductor chip 2, the second adhesive layer 5 and the die pad 3 are heated at the temperature of about 100 C. from the lower side of the first semiconductor chip 2. The adhesive layer 4 is hardened and it fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
  • [0081]
    The final hardening of the adhesive layers is performed, and the semiconductor chips are perfectly fixed on the die pad 3.
  • [0082]
    [0082]FIG. 8 shows a cross sectional view of the method for manufacturing the semiconductor device of the sixth preferred embodiment. The same reference numerals are applied for the elements those are described in the first embodiment.
  • [0083]
    The featuring point of this embodiment is that the second adhesive layer 5 is formed after the first semiconductor chip is fixed. One of thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape are preferably used as adhesive layers.
  • [0084]
    The die pad 3, which is not downset, is prepared. The insulating adhesive layer 84 (first adhesive layer) is formed on bottom surface of the die pad 3.
  • [0085]
    The first semiconductor chip 1 is put on the die pad bottom surface 3. The first semiconductor chip 1, the first adhesive layer 4 and the die pad 3 are heated from the lower side of the first semiconductor chip 1. The adhesive layer 4 fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
  • [0086]
    Then, The insulating or conductive adhesive layer 5 (second adhesive layer) is formed over the top surface of the die pad 3.
  • [0087]
    The second semiconductor chip 2 is put over the die pad top surface 3. The second semiconductor chip 2, the second adhesive layer 5 and the die pad 3 are heated from the lower side of the first semiconductor chip 2. The adhesive layer 5 fixes the second semiconductor chip 2 on the die pad 3 after this heat treatment.
  • [0088]
    The final hardening of the adhesive layers is performed, and the semiconductor chips are perfectly fixed on the die pad 3. This fixing process is called die bonding process. Electrodes of the semiconductor chips are electrically connected to inner leads or another electrode via metal wire 8, 9. Then molding process is performed.
  • [0089]
    In this embodiment, the second adhesive layer can be selected according to the needs, because the second adhesive layer is formed after the fixing of the first semiconductor chip. It can be selected in this method whether the second chip bottom surface must have potential or not even after the first semiconductor chip has fixed.
  • [0090]
    This invention is not limited by these embodiments.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7157790Jul 31, 2002Jan 2, 2007Microchip Technology Inc.Single die stitch bonding
US7199469 *Sep 28, 2001Apr 3, 2007Renesas Technology Corp.Semiconductor device having stacked semiconductor chips sealed with a resin seal member
US7326594Nov 28, 2006Feb 5, 2008Microchip Technology IncorporatedConnecting a plurality of bond pads and/or inner leads with a single bond wire
US7485490Nov 22, 2005Feb 3, 2009Amkor Technology, Inc.Method of forming a stacked semiconductor package
US7675180Feb 17, 2006Mar 9, 2010Amkor Technology, Inc.Stacked electronic component package having film-on-wire spacer
US7863723Dec 23, 2008Jan 4, 2011Amkor Technology, Inc.Adhesive on wire stacked semiconductor package
US8072083Jan 20, 2010Dec 6, 2011Amkor Technology, Inc.Stacked electronic component package having film-on-wire spacer
US8129849Oct 28, 2009Mar 6, 2012Amkor Technology, Inc.Method of making semiconductor package with adhering portion
US8143727Nov 16, 2010Mar 27, 2012Amkor Technology, Inc.Adhesive on wire stacked semiconductor package
US20020043717 *Sep 28, 2001Apr 18, 2002Toru IshidaSemiconductor device
US20020125556 *Dec 12, 2001Sep 12, 2002Oh Kwang SeokStacking structure of semiconductor chips and semiconductor package using it
US20080099893 *Dec 13, 2007May 1, 2008Microchip Technology IncorporatedConnecting a plurality of bond pads and/or inner leads with a single bond wire
EP2104142B1 *Apr 28, 2008Nov 2, 2016MediaTek Inc.Semiconductor chip package
Legal Events
DateCodeEventDescription
May 4, 2001ASAssignment
Owner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OKA, TAKAHIRO;REEL/FRAME:011772/0864
Effective date: 20010424