Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010026175 A1
Publication typeApplication
Application numberUS 09/819,616
Publication dateOct 4, 2001
Filing dateMar 29, 2001
Priority dateMar 29, 2000
Also published asUS6407592
Publication number09819616, 819616, US 2001/0026175 A1, US 2001/026175 A1, US 20010026175 A1, US 20010026175A1, US 2001026175 A1, US 2001026175A1, US-A1-20010026175, US-A1-2001026175, US2001/0026175A1, US2001/026175A1, US20010026175 A1, US20010026175A1, US2001026175 A1, US2001026175A1
InventorsMasayuki Ueno
Original AssigneeKawasaki Steel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Sample-and-hold circuit
US 20010026175 A1
Abstract
The purpose of the present invention is to prevent the charge stored in a hold capacitor from leaking via the switches connected to the electrode of the capacitor, in a sample-and-hold circuit, and to suppress the reduction in the voltage held in the capacitor, thereby improving the performance of the sample-and-hold circuit. The switches connected to the capacitor comprises two N-channel MOS transistors that are connected in series and are simultaneously turned on or off. During the period that the switches are in the OFF state, the potential at the interconnection node of the two transistors (one end of a first transistor) is set so as to be equal to that of the other end of the first transistor. Since the potential difference between the both ends of the first transistor thereby becomes zero, leakage currents via the first transistor is reduced, and charge leakage in the capacitor can be prevented.
Images(8)
Previous page
Next page
Claims(12)
What is claimed is:
1. A sample-and-hold circuit, comprising:
a capacitor for storing a voltage input from an outside as an electric charge, and holding a potential thereof;
switches connected to said capacitor, said switches being constituted of a plurality of switches that are connected in series with each other,
wherein a potential difference between both ends of a first switch connected to a side of said capacitor out of the plurality of switches, being set to zero or substantially zero, at least during a time period that said plurality of switches is in the OFF state.
2. A sample-and-hold circuit in accordance with
claim 1
, wherein said plurality of switches is connected in series with each other, said plurality of switches being simultaneously turned on or off.
3. A sample-and-hold circuit in accordance with
claim 1
, wherein said first switch is connected to a charge storage electrode of said capacitor.
4. A sample-and-hold circuit in accordance with claim 2, wherein said first switch is connected to a charge storage electrode of said capacitor.
5. A sample-and-hold circuit in accordance with
claim 1
, further comprising:
an equipotential setting circuit that sets the potential of one end of said first switch wherein another end thereof is connected to said capacitor so that the potential difference between the both ends of said first switch becomes zero or substantially zero.
6. A sample-and-hold circuit in accordance with
claim 2
, further comprising:
an equipotential setting circuit that sets the potential of one end of said first switch wherein another end thereof is connected to said capacitor so that the potential difference between the both ends of said first switch becomes zero or substantially zero.
7. A sample-and-hold circuit in accordance with
claim 1
, wherein each of said plurality of switches or said capacitor is formed of a MOS transistor.
8. A sample-and-hold circuit in accordance with
claim 2
, wherein each of said plurality of switches or said capacitor is formed of a MOS transistor.
9. A sample-and-hold circuit in accordance with
claim 5
, wherein said equipotential setting circuit comprising:
a differential amplifier having a first input terminal, a second input terminal, and an output terminal for outputting a voltage obtained by amplifying the potential difference between said first and second input terminals; and
a second switch for connecting an interconnection node of said plurality of switches and said first input terminal,
wherein one end of said capacitor is connected to said second input terminal, the other end thereof is connected to said output terminal, and the interconnection node of said plurality of switches and said first input terminal are connected by said second switch, during the time period that said plurality of switches is in the OFF state.
10. A sample-and-hold circuit in accordance with
claim 6
, wherein said equipotential setting circuit comprising:
a differential amplifier having a first input terminal, a second input terminal, and an output terminal for outputting the voltage obtained by amplifying a potential difference between said first and second input terminals; and
a second switch for connecting an interconnection node of said plurality of switches and said first input terminal,
wherein one end of said capacitor is connected to said second input terminal, the other end thereof is connected to said output terminal, and the interconnection node of said plurality of switches and said first input terminal are connected by said second switch, during the time period that said plurality of switches is in the OFF state.
11. A sample-and-hold circuit in accordance with
claim 5
, wherein said equipotential setting circuit further comprising:
a buffer amplifier that amplifies a voltage at an interconnection node between one end of said capacitor and the input terminal of said amplifier, outputs the amplified voltage to the output terminal thereof, and has an amplification factor of “1”; and
a switch that connects the interconnection node of said plurality of switches and the output terminal of said buffer amplifier, during the time period that said plurality of switches is in the OFF state.
12. A sample-and-hold circuit in accordance with
claim 6
, wherein said equipotential setting circuit further comprising:
a buffer amplifier that amplifies a voltage at an interconnection node between one end of said capacitor and the input terminal of said amplifier, outputs the amplified voltage to the output terminal thereof, and has an amplification factor of “1”; and
a switch that connects the interconnection node of said plurality of switches and the output terminal of said buffer amplifier, during the time period that said plurality of switches is in the OFF state.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a sample-and-hold circuit that stores the electric charge corresponding to an input voltage in a capacitor, and holds the potential thereof, and particularly to a sample-and-hold circuit that reduces the charge leakage due to the switches connected to the electrode of the capacitor, and suppresses the reduction in the held voltage.

[0003] 2. Description of the Related Art

[0004]FIG. 4 is a circuit diagram for a capacitor array type D/A conversion circuit using a conventional sample-and-hold circuit.

[0005] This sample-and-hold circuit stores the charge corresponding to the voltage input from an input terminal VR in a capacitor C3, and holds the potential thereof. The held potential is amplified by an amplifier 10 connected to the capacitor C3, and the amplified voltage is output from an output terminal Vout to the outside.

[0006] The capacitor that stores the charge corresponding to the voltage input from the outside and holds the potential thereof is referred to as a “hold capacitor”.

[0007] The operation of this conventional capacitor array type D/A conversion circuit will be described below. First, for initialization (reset), all of the one ends of the capacitors C1 to C3 are connected to the ground GND by switches SW0 to SW2, and a N-channel MOS transistor TN1 is turned on. Then, the amount of the charges which have been stored in the capacitor C0 to C3 becomes zero.

[0008] Next, in response to the digital signals input as signals to be D/A converted, one ends of the capacitors CO to C2 are connected to a reference voltage terminal VR by the SW0 to SW2 switches, and then a N-channel MOS transistor TN1 is turned off. Here, for example, when one end of the capacitor C0 is connected to the ground GND by the switch SW0, the one ends of the capacitors C1 and C2 are connected to a reference voltage terminal VR by the switches SW1 and SW2, and the N-channel MOS transistor TN1 is turned off, a voltage output from the output terminal Vout is given by the following equation.

Vout=(Q3/C3)={(C1+C2)/C3}×VR  (1)

[0009] where, C1 to C3 denotes the capacitances of the capacitors C1 to C3, respectively, and Q3 denotes the amount of the charge stored between both ends of the capacitor C3.

[0010]FIG. 5 is a circuit diagram for a switching comparator using a sample-and-hold circuit in accordance with another conventional example.

[0011] In FIG. 5, a sample-and-hold circuit is comprised of a capacitor C4, an inverter I1, and a N-channel MOS transistor TN3. By adding N-channel MOS transistors TN2 and TN4 to such a sample-and-hold circuit, a switching comparator is formed.

[0012] The operation of the switching comparator shown in FIG. 5 will be described using a timing chart shown in FIG. 6.

[0013] First, in a time period T1, the N-channel MOS transistors TN2 and TN3 are turned on, and the N-channel MOS transistor TN4 is turned off. The capacitor C4 is thereby initialized while an input voltage V1 is applied.

[0014] Then, in a time period T2, the N-channel MOS transistors TN2 and TN3 are turned off, and the N-channel MOS transistors TN4 is turned on. As a result, the output of the inverter I1 varies in response to the potential difference between the input voltage V1 and an input voltage V2. If V1 is larger than V2, an “H” level, that is, a power supply voltage VDD is output from the inverter I1. On the other hand, if V1 is smaller than V2, an “L” level, that is, a GND level is output from the inverter I1. In this way, the switching comparator compares magnitudes between an input voltages V1 and V2, and outputs an “H” level or an “L” level.

[0015] Hereafter, after the time period T3, similar operations to the above-described time periods T1 and T2 are repeated.

[0016]FIG. 7 is a circuit diagram for a successive comparison type A/D conversion circuit using the above-described switching comparator.

[0017] In this A/D conversion circuit, each of N-channel MOS transistors TN11, TN12, TN13, etc. corresponds to the N-channel MOS transistor TN4 of the above-described switching comparator. The connection nodes in a ladder resistor comprising a plurality of resistors R are connected to the plurality of N-channel MOS transistors TN11, TN12, TN13 etc. Each of the plurality of N-channel MOS transistors selectively selects the voltage produced by the ladder resistor. Herein, a capacitor C4 stores the charge given by the following equation.

Q=C4×(Vin−Vb)  (2)

[0018] where, Vb denotes the input voltage of the inverter I1 when the capacitor C4 has been initialized.

[0019] The operation of the A/D conversion circuit shown in FIG. 7 will be described using a timing chart shown in FIG. 8.

[0020] First, in a time period TO, the N-channel MOS transistors TN2 and TN3 are turned on, and all of the N-channel MOS transistors TN11, TN12, TN13, etc. are turned off. The capacitor C4 is thereby initialized while an analog signal Vin to be A/D converted is applied to.

[0021] Then, in a time period T1, the N-channel MOS transistors TN2 and TN3 are turned off, and the N-channel MOS transistor TN11 is turned on. As a result, the output of the inverter I1 varies in response to the potential difference between the input voltage Vin and a reference voltage VR1. If VR1 is smaller than Vin, an “H” level is output from the inverter I1. On the other hand, if VR1 is larger than Vin, an “L” level is output. In this manner, the switching comparator compares magnitudes between the input voltage Vin and the reference voltage VR1, and outputs an “H” level or an “L” level.

[0022] Next, in a time period T2, the N-channel MOS transistors TN2 and TN3 are turned off, and the N-channel MOS transistor TN12 is turned on. As a result, the output of the inverter I1 varies in response to the potential difference between the input voltage Vin and a reference voltage VR2. If VR2 is smaller than Vin, an “H” level is output from the inverter I1. On the other hand, if VR1 is larger than Vin, an “L” level is output. The switching comparator thus compares magnitudes between an input voltage Vin and the reference voltage VR2, and outputs an “H” level or an “L” level.

[0023] The same operation is performed for each time period after a time period T3. N-channel MOS transistors from a N-channel MOS transistor TN14 onward are successively turned on, reference voltages from a voltage VR3 onward are successively input, and reference voltages are successively compared with the respective input voltages Vin.

[0024]FIG. 9 is a circuit diagram for a sample-and-hold circuit in accordance with a third conventional example.

[0025] In this sample-and-hold circuit, the voltage input from an input terminal Vin is amplified by an amplifier 11, and the amplified voltage is output from an output terminal Vout. Also, the charge corresponding to the voltage input from the input terminal Vin are stored in a capacitor C5, and the potential is held by turning off a N-channel MOS transistor TN5. Even after the N-channel MOS transistor TN5 has been turned off, the held potential continues to be output.

[0026] In this manner, in each of these first to third conventional examples, the charge corresponding to the voltage input from the outside are stored in the capacitor, and thereby the potential thereof is held. However, even if the switches connected to the capacitor is turned off, the charge stored in the capacitor leaks as leakage currents via the switches.

[0027] Specifically, for example, in the first conventional example shown in FIG. 4, even if the N-channel MOS transistor that constitutes a switch is in the OFF state with its gate voltage being 0 V, the charge stored in the capacitor C3 leaks as leakage currents via the N-channel MOS transistor TN1. Likewise, in the second conventional example shown in FIG. 5, the charge stored in the capacitor C4 leaks as leakage currents via the N-channel MOS transistor TN3 that is in the OFF state, and in the third conventional example shown in FIG. 9, the charge stored in the capacitor C5 leaks as leakage currents via the N-channel MOS transistor TN5 that is in the OFF state.

[0028]FIG. 10 is a diagram illustrating the leakage of the charge stored in the hold capacitor in the first conventional example.

[0029] In this diagram, the time period A is an initialization period that the charge is discharged and the next charge storage is prepared for. The time period B is a time period that the charge is stored and the potential is held, as well as the voltage output to the outside. Herein, the charge stored in the hold capacitor leaks as leakage currents via the switches connected thereto, and decreases with time. As shown in FIG. 10, for example, the amounts corresponding to charge amounts q1 or q2 become the loss portions due to the leakage currents flowing via the switches. Here, the difference in the amount of charge loss between q1 and q2 is attributable to the difference in the characteristics between transistors constituting the switches.

[0030] In this way, as the charge decreases, the held voltage also declines.

[0031] In the first conventional example, under ideal conditions that there is no leakage current, a voltage based on the above-described equation (1) is output. However, as shown in FIG. 10, when the charge Q3 stored in the capacitor C3 decreases, an intended voltage Vout cannot be achieved. The difference between the intended voltage and the voltage actually obtained corresponds to the above-described amounts of the charge losses q1 and q2.

[0032] Here, in order to speed up circuit operations, if the capacity of the hold capacitor is reduced and/or the on-resistances of the switches connected to the capacitor is decreased, such influences of leakage currents increase. Also, appropriate comparative operations in an A/D conversion and the like cannot be carried out when attempting to elongate a voltage output period.

[0033] To the contrary, in order to perform appropriate comparative operations, it is necessary to increase the capacity of the hold capacitor, and/or to increase the on-resistances of the switches. However, this, in turn, prevents an initialization operation from being appropriately achieved. That is, it takes longer time than necessary time to discharge the charge stored in the hold capacitor, and/or to store enough charge in the hold capacitor up to the voltage input from the outside.

[0034] Thus, in the conventional sample-and-hold circuits, the avoidance of the influences of leakage currents, and the achievement of a desired accuracy are gained at the expense of operation speed.

SUMMARY OF THE INVENTION

[0035] The present invention has been made with a view to solving the above-described problems associated with the conventional art. The purpose of the present invention is to prevent the electric charge stored in a hold capacitor from leaking as leakage currents via the switches connected to the hold capacitor, to suppress the reduction of the voltage held in the hold capacitor, and to thereby improve the performance of the sample-and-hold circuit.

[0036] In order to achieve the above-described purpose, the present invention provides a sample-and-hold circuit that has a capacitor for storing the voltage input from the outside as an electric charge, and holding the potential thereof, and has the switches connected to the capacitor. The switches are constituted of a plurality of switches that are connected in series with each other. In this sample-and-hold circuit, the potential difference between the both ends of the switch (referred to as a first switch or the input terminal side switch) connected to the side of the capacitor out of the plurality of switches, is set to zero or substantially zero, at least during the time period that the plurality of switches is in the OFF state.

[0037] Preferably, the plurality of switches are connected in series with each other, and is simultaneously turned on or off.

[0038] Also, preferably the first switch is connected to one electrode (referred to as a charge storage electrode) in which a charge is stored, out of both electrodes of the capacitor. Here, the other electrode (opposite electrode to the charge storage electrode) of the capacitor is provided with a predetermined potential.

[0039] Furthermore, it is preferable that the sample-and-hold circuit in accordance with the present invention further includes an equipotential setting circuit that sets the potential of one end of the first switch wherein the other end thereof is connected to the capacitor so that the potential difference between both ends of the switch becomes zero or substantially zero.

[0040] Also, preferably, each of the plurality of switches or the hold capacitor is formed of a MOS transistor.

[0041] Moreover, it is preferable that the equipotential setting circuit includes a differential amplifier having a first input terminal, a second input terminal, and an output terminal for outputting the voltage obtained by amplifying the potential difference between the first and second input terminals, and includes a switch (second switch) for connecting the interconnection node of the plurality of switches and the first input terminal. In this equipotential setting circuit, it is further preferable that one end of the capacitor is connected to the second input terminal, while the other end thereof is connected to the output terminal, and that the interconnection node of the plurality of switches and the first input terminal is connected by the second switch, during the time period that the plurality of switches is in the OFF state.

[0042] In addition, the equipotential setting circuit preferably has a buffer amplifier that amplifies the voltage at the interconnection node between one end of the capacitor and the input terminal of the amplifier, outputs the amplified voltage to the output terminal thereof, and has an amplification factor of “1”, and preferably has a switch that connects the interconnection node of these switches and the output terminal of the buffer amplifier, during the time period that these plurality of switches is in the OFF state.

[0043] The above and other objects, features, and advantages of the present invention will be clear from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044]FIG. 1 is a circuit diagram for a capacitor array type D/A conversion circuit using a sample-and-hold circuit in accordance with a first embodiment to which the present invention is applied;

[0045]FIG. 2 is a circuit diagram for a switching comparator using a sample-and-hold circuit in accordance with a second embodiment to which the present invention is applied;

[0046]FIG. 3 is a circuit diagram for a sample-and-hold circuit in accordance with a third embodiment to which the present invention is applied;

[0047]FIG. 4 is a circuit diagram for a capacitor array type D/A conversion circuit using a sample-and-hold circuit in accordance with a first conventional example;

[0048]FIG. 5 is a circuit diagram for a switching comparator using a sample-and-hold circuit in accordance with a second conventional example;

[0049]FIG. 6 is a time chart showing the operations of the switching comparator shown in FIG. 5;

[0050]FIG. 7 is a circuit diagram for a successive comparison A/D conversion circuit using a switching comparator in accordance with a second conventional example;

[0051]FIG. 8 is a time chart illustrating the operations of the A/D conversion circuit shown in FIG. 7;

[0052]FIG. 9 is a circuit diagram for a sample-and-hold circuit in accordance with a third conventional example; and

[0053]FIG. 10 is a diagram illustrating the leakage of the charge stored in the hold capacitor in the first conventional example.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] In the present invention, the switch connected to the hold capacitor comprises two switches that are connected in series with each other, and that are simultaneously turned on or off.

[0055] Hereinafter, the switches connected in series with each other are referred to as “series configuration switches”.

[0056] Even though the switches used in the sample-and-hold circuit are thus constituted of two switches in series with each other, these switches can be used in the same manner as typical switches if they are simultaneously turned on or off.

[0057] Also, in the present invention, the potential difference between both ends of the switch (hereinafter, referred to as an input terminal side switch) connected to the input terminal of the above-described amplifier, out of the switches that constitutes the series configuration switches, is set to zero, at least during the time period that the switches are in the OFF state. In order to set the potential difference to be zero, there is provided an equipotential setting circuit that sets the potential of interconnection node of these switches that constitutes the series configuration switches. The equipotential setting circuit generates the same voltage as the input terminal voltage of the amplifier or the voltage close thereto, and applies them to the interconnection node of these switches.

[0058] Then, one end of the input terminal side switch is a potential of the input terminal. The other end of the input terminal side switch exhibits an equal voltage to that of the input terminal or the voltage close thereto by the equipotential setting circuit. As a result, the potential difference between both ends of the switch becomes zero or a small voltage.

[0059] The leakage currents flowing via the switch depends on the potential difference between both ends of the switch. In the present invention, since the potential difference between both ends of the switch becomes zero or a small voltage, the leakage current flowing via the switch becomes zero or a small current. In the case of the switch other than the input terminal side switch that constitutes the series configuration switches, leakage currents flow as in the case of the conventional examples. However, since these leakage currents are supplied by the equipotential setting circuit, there is no leakage of the charge stored in the hold capacitor. Hence, if such series configuration switches are used as switches to be connected to the hold capacitor, the charge leakage from the capacitor via the switches will be reduced.

[0060] Thus, in the present invention, the charge stored in the capacitor can be prevented from leaking as leakage currents via the switches connected to the capacitor. It is, therefore, possible to suppress a reduction in the held voltage due to the leakage of the charge stored in the capacitor, and to thereby improve the performance of the sample-and-hold circuit.

[0061]FIG. 1 is a circuit diagram for a capacitor array type D/A conversion circuit using a sample-and-hold circuit in accordance with a first embodiment to which the present invention is applied.

[0062] In this embodiment, the N-channel MOS transistor TN1 in the conventional example shown in FIG. 4 is replaced with the series configuration switches that are constituted of N-channel MOS transistors TN1A and TN1B. In addition, this embodiment is provided with an equipotential setting circuit comprising a N-channel MOS transistor TN6 and an inverter I3.

[0063] An amplifier 10 is a differential amplifier, and outputs a voltage in proportion to the potential difference between the positive input terminal and negative input terminal to the output terminal. Since the amplifier 10 is constructed of a negative feedback circuit, the potential difference between the positive input terminal and negative input terminal thereof is significantly small. The relationship between the positive and negative input terminals, therefore, constitutes a state called “virtual short”.

[0064] In this embodiment, during the time period that the series configuration switches are in the OFF state, an “H” level is output from the inverter I3, and a N-channel MOS transistor TN6 comes into the ON state. Consequently, the potential at the interconnection node between the two switches that constitute the series configuration switches becomes equal to that of the positive input terminal of the amplifier 10. Thereby, the potential at the interconnection node becomes substantially equal to the negative input terminal of the amplifier 10 due to the above-described virtual short. Thus, substantially equal potentials are applied to the both ends of the N-channel MOS transistor TN1A.

[0065] In this way, in this embodiment, during the time period that the charge is held in the hold capacitor, the leakage currents flowing through the N-channel MOS transistor TN1A that constitutes the series configuration switches becomes substantially zero. On the other hand, in the other N-channel MOS transistor TN1B that constitutes the series configuration switches, since the currents flowing therethrough are supplied by a ground GND via the N-channel MOS transistor TN6 of the equipotential setting circuit, there is no leakage of the charge stored in the hold capacitor.

[0066] Thus, in this embodiment, the charge stored in the capacitor can be prevented from leaking as leakage currents via the switches connected to the capacitor. It is, therefore, possible to suppress a reduction in the held voltage due to the leakage of the charge stored in the capacitor, and to thereby improve the performance of the sample-and-hold circuit, for example, to increase the conversion accuracy in the capacitor array type D/A conversion circuit thereof.

[0067]FIG. 2 is a circuit diagram for a switching comparator using a sample-and-hold circuit in accordance with a second embodiment of the present invention.

[0068] The N-channel MOS transistor TN3 in the conventional example shown in FIG. 5 is a switch that stores charge in a capacitor C4 and holds the charge. The stored charge leaks as leakage currents via this switch.

[0069] In this embodiment, this N-channel MOS transistor TN3 in the conventional example is replaced with the series configuration switches that are constituted of N-channel MOS transistor TN3A and TN3B. In addition, this embodiment is provided with an equipotential setting circuit comprising a N-channel MOS transistor TN7 and an inverter I4.

[0070] An amplifier 12 is a differential amplifier. The amplifier amplifies the potential difference between the positive input terminal and negative input terminal thereof, and outputs the amplified voltage to the output terminal thereof. Since the amplifier 10 is constructed of a negative feedback circuit, and constitutes a buffer amplifier of which the amplification factor is “1”, the potential difference between the positive input terminal and negative input terminal thereof is significantly small. The relationship between the positive and negative input terminals, therefore, constitutes a state called “virtual short”, as described above.

[0071] In this embodiment, during the time period that the series configuration switches are in the OFF state, an “H” level is output from the inverter I4, and a N-channel MOS transistor TN7 comes in the ON state. Consequently, the potential at the interconnection node between the two switches constituting the series configuration switches becomes equal to that of the negative input terminal of the amplifier 12. Thereby, the potential at the interconnection node becomes substantially equal to that of the positive input terminal of the amplifier 12 due to the above-described virtual short. Thus, substantially equal potentials are applied to the both ends of the N-channel MOS transistor TN3A.

[0072] In this manner, in this embodiment, during the time period that the charge is held in the hold capacitor, the leakage currents flowing through the N-channel MOS transistor TN3A that constitutes the series configuration switches becomes substantially zero. On the other hand, in the other N-channel MOS transistor TN3B that constitutes the series configuration switches, since currents flowing therethrough are supplied by the amplifier 12 of the equipotential setting circuit, there is no leakage of the charge stored in the hold capacitor.

[0073] Thus, in this embodiment, the charge stored in the capacitor can be prevented from leaking as leakage currents via the switches connected to the capacitor. It is, therefore, possible to suppress a reduction in the held voltage due to the leakage of charge stored in the capacitor, and to thereby improve the performance of the sample-and-hold circuit.

[0074] Meanwhile, this second embodiment may be used instead of the sample-and-hold circuit that constitutes the successive comparison A/D conversion circuit in FIG. 7, this sample-and-hold circuit described as a conventional example.

[0075]FIG. 3 is a circuit diagram for a sample-and-hold circuit in accordance with a third embodiment of the present invention.

[0076] The N-channel MOS transistor TN5 in the conventional example shown in FIG. 9 is a switch that stores charge in a capacitor C5 and which holds the charge. The stored charge leaks as leakage currents via this switch.

[0077] In this embodiment, this N-channel MOS transistor TN5 in the conventional example is replaced with the series configuration switches constituted of N-channel MOS transistor TN5A and TN5B. In addition, this embodiment is provided with an equipotential setting circuit comprising a N-channel MOS transistor TN8 and an inverter I5.

[0078] An amplifier 13 is a differential amplifier. The amplifier 13 amplifies the potential difference between the positive input terminal and negative input terminal thereof, and outputs the amplified voltage to the output terminal thereof. Since the amplifier 13 is constructed of a negative feedback circuit, and constitutes a buffer amplifier of which the amplification factor is “1”, the potential difference between the positive input terminal and negative input terminal thereof is significantly small. The relationship between the positive and negative input terminals, therefore, constitutes a state called “virtual short”, as described above.

[0079] In this embodiment, during the time period that the series configuration switches are in the OFF state, an “H” level is output from the inverter I5, and a N-channel MOS transistor TN8 comes into the ON state. Consequently, the potential at the interconnection node between the two switches constituting the series configuration switches becomes equal to that of the negative input terminal of the amplifier 13, and also becomes substantially equal to the positive input terminal of the amplifier 13 due to the above-described virtual short.

[0080] Thus, in this embodiment, during the time period that the charge is held in the hold capacitor, the leakage currents flowing through the N-channel MOS transistor TN5A that constitutes the series configuration switches becomes substantially zero. On the other hand, in the other N-channel MOS transistor TN5B that constitutes the series configuration switches, since currents flowing therethrough are supplied by the amplifier 13 of the equipotential setting circuit, there is no leakage of the charge stored in the hold capacitor.

[0081] In this way, in this embodiment, the charge stored in the capacitor can be prevented from leaking as leakage currents via the switches connected to the capacitor. It is, therefore, possible to suppress a reduction in the held voltage due to the leakage of charge stored in the capacitor, and to thereby improve the performance of the sample-and-hold circuit.

[0082] As is evident from the foregoing, in accordance with the present invention, the reduction in the held voltage due to the leakage of the charge stored in the capacitor can be suppressed, and thereby an improvement in the performance of the sample-and-hold circuit can be achieved. Moreover, the elongation of the time period that charge can be held, allows operations at lower speed, and eliminates the need for frequent refresh operations, and leads to reduced power consumption.

[0083] While the present invention has been described with reference to what are at present considered to be the preferred embodiments, it is to be understood that various changes and modifications may be made thereto without departing from the invention in its broader aspects and therefore, it is intended that the appended claims cover all such changes and modifications as fall within the true spirit and scope of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7332941 *Mar 14, 2005Feb 19, 2008Kabushiki Kaisha ToshibaAnalog switch circuit and sample-and-hold circuit including the same
US7773332Nov 21, 2003Aug 10, 2010Agere Systems Inc.Long hold time sample and hold circuits
US8111094Jul 1, 2010Feb 7, 2012Lsi CorporationAnalog multiplexer circuits and methods
EP1538634A2 *Nov 2, 2004Jun 8, 2005Agere Systems, Inc.Long hold time sample and hold circuits
WO2004053887A1 *Dec 9, 2003Jun 24, 2004Infineon Technologies AgCircuit arrangement for leakage current restriction sample-and-hold circuit with said circuit arrangement and charge pumping circuit with said circuit arrangement
Classifications
U.S. Classification327/94
International ClassificationG11C27/02
Cooperative ClassificationG11C27/026, G11C27/024
European ClassificationG11C27/02C1, G11C27/02C
Legal Events
DateCodeEventDescription
Nov 20, 2013FPAYFee payment
Year of fee payment: 12
Nov 18, 2009FPAYFee payment
Year of fee payment: 8
Nov 28, 2005FPAYFee payment
Year of fee payment: 4
Dec 10, 2001ASAssignment
Owner name: KAWASAKI MICROELECTRONICS, INC., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAWASAKI STEEL CORPORATION;REEL/FRAME:012312/0864
Effective date: 20011129
Owner name: KAWASAKI MICROELECTRONICS, INC. 3 BANCHI NAKASE 1-
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAWASAKI STEEL CORPORATION /AR;REEL/FRAME:012312/0864
Mar 29, 2001ASAssignment
Owner name: KAWASAKI STEEL CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UENO, MASAYUKI;REEL/FRAME:011662/0404
Effective date: 20010327
Owner name: KAWASAKI STEEL CORPORATION CHUO-KU, KOBE-SHI 1-28,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UENO, MASAYUKI /AR;REEL/FRAME:011662/0404