Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010026985 A1
Publication typeApplication
Application numberUS 09/749,785
Publication dateOct 4, 2001
Filing dateDec 28, 2000
Priority dateMar 29, 2000
Also published asUS6372594
Publication number09749785, 749785, US 2001/0026985 A1, US 2001/026985 A1, US 20010026985 A1, US 20010026985A1, US 2001026985 A1, US 2001026985A1, US-A1-20010026985, US-A1-2001026985, US2001/0026985A1, US2001/026985A1, US20010026985 A1, US20010026985A1, US2001026985 A1, US2001026985A1
InventorsMoon Kim, Kyoung Yang, Young Kwon
Original AssigneeKim Moon Jung, Yang Kyoung Hoon, Kwon Young Se
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Fabrication method of submicron gate using anisotropic etching
US 20010026985 A1
Abstract
Disclosed is a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process. The method involves the steps of laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively, defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner, selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist, and depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate. In accordance with the present invention, a reliable submicron gate can be fabricated using a simple anisotropic wet etch process and an inexpensive contact aligner. Accordingly, the manufacturing costs can be reduced. In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter, thereby achieving a reduction in base resistance, by virtue of a self-alignment using a V-shaped submicron gate.
Images(5)
Previous page
Next page
Claims(11)
What is claimed is:
1. A method for fabricating a submicron gate comprising the steps of:
(a) laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively;
(b) defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner;
(c) selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist; and
(d) depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate.
2. The method according to
claim 1
, further comprising the step of:
(e) depositing a contact metal over a structure obtained after completion of the step (d), thereby self-aligning the gate.
3. The method according to
claim 1
, wherein the dummy emitter formed at the step (a) has a thickness more than the thickness of the layer defining the emitter region.
4. The method according to
claim 2
, wherein the dummy emitter formed at the step (a) has a thickness more than the thickness of the layer defining the emitter region.
5. The method according to
claim 1
, wherein the bottom width of the etched dummy emitter portion formed at the step (c) is adjusted to have a submicron unit in accordance with an adjustment for the width of the line defined by the photoresist, the thickness of the dummy emitter, and an etch inclination of the etched dummy emitter portion resulting from the anisotropic etching.
6. The method according to
claim 2
, wherein the bottom width of the etched dummy emitter portion formed at the step (c) is adjusted to have a submicron unit in accordance with an adjustment for the width of the line defined by the photoresist, the thickness of the dummy emitter, and an etch inclination of the etched dummy emitter portion resulting from the anisotropic etching.
7. The method according to
claim 1
, wherein the step (a) comprises the steps of:
preparing an InP substrate as the semiconductor substrate; and
laminating first through third InGaAs layers and first and second InP layers over the InP substrate in an alternating fashion to define the base region by the third InGaAs layer arranged just above the InP substrate, the emitter region by the second InP layer arranged just above the third InGaAs layer, the emitter cap region by the second InGaAs layer arranged just above the second InP layer, and the dummy emitter region by the first InP layer and the first InGaAs layer arranged over the second InGaAs layer.
8. The method according to
claim 2
, wherein the step (a) comprises the steps of:
preparing an InP substrate as the semiconductor substrate; and
laminating first through third InGaAs layers and first and second InP layers over the InP substrate in an alternating fashion to define the base region by the third InGaAs layer arranged just above the InP substrate, the emitter region by the second InP layer arranged just above the third InGaAs layer, the emitter cap region by the second InGaAs layer arranged just above the second InP layer, and the dummy emitter region by the first InP layer and the first InGaAs layer arranged over the second InGaAs layer.
9. The method according to
claim 1
, wherein the step (d) comprises the steps of:
depositing a contact metal over a structure obtained after completion of the step (c);
lifting off a portion of the contact metal arranged on the photoresist, along with the photoresist;
selectively etching the dummy emitter, thereby forming the gate; and
selectively anisotropic etching portions of the heterojunction bipolar transistor structure respectively corresponding to the emitter cap region and the emitter region while using the gate as a mask, thereby allowing the gate to have a self-aligned structure.
10. The method according to
claim 2
, wherein the step (d) comprises the steps of:
depositing a contact metal over a structure obtained after completion of the step (c);
lifting off a portion of the contact metal arranged on the photoresist, along with the photoresist;
selectively etching the dummy emitter, thereby forming the gate; and
selectively anisotropic etching portions of the heterojunction bipolar transistor structure respectively corresponding to the emitter cap region and the emitter region while using the gate as a mask, thereby allowing the gate to have a self-aligned structure.
11. The method according to
claim 9
, wherein the emitter region defining layer left after the selective anisotropic etching of the hetero bipolar transistor structure has a bottom width less than the width of the line defined by the photoresist while being more than the bottom width of the etched portion formed at the step (c), in accordance with an adjustment for the width of the line defined by the photoresist, the thickness of the emitter defining layer, and an etch inclination of the etched dummy emitter portion resulting from the anisotropic etching at the step (c).
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a submicron gate electrode of a semiconductor device, and more particularly to a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process.
  • [0003]
    2. Description of the Related Art
  • [0004]
    Remarkable development recently made in radio communication fields has resulted in an increased demand for ultrahigh broadband communication networks. An exemplary one of such networks is a network for local multipoint distribution services in which audio, video conference, and digital signals are simultaneously transmitted at a bandwidth of 1.3 GHz within a service area of 2 to 7 Km in radius, using a 28 GHz “Ka-band”. In order to construct such an ultrahigh broadband communication network, it is very important to develop ultrahigh-frequency devices operating the above mentioned frequency band while achieving a miniature and high performance of devices. To this end, active research efforts have been made. In particular, devices including submicron gates have been highlighted.
  • [0005]
    Conventional techniques associated with submicron gates are disclosed in U.S. Pat. No. 5,288,645 (entitled “Method of making a mushroom-shaped gate electrode of semiconductor device), and U.S. Pat. No. 5,053,348 (entitled “Fabrication of self-aligned, T-gate HEMT”). However, these techniques require an expensive exposure process, such as an electron beam writing process or a stepped exposure process, to form a submicron gate. Furthermore, these techniques involve execution of a number of semiconductor processes including repeated exposure, deposition and etching. In order to obtain a desired self-alignment of the submicron gate, diverse semiconductor processes for forming, for example, sidewalls, should be conducted.
  • [0006]
    Another conventional technique is known in association with submicron gates. For example, the following references discloses a method in which an electron beam writing process is repeatedly used to form a submicron gate, and sidewalls are formed using a dielectric material to obtain a self-alignment of the submicron gate.
  • [0007]
    [Reference]
  • [0008]
    1. A dielectric-defined process for the formation of T-gate field-effect transistors. G. M. Metze. IEEE MGWL. Vol. 1, No. 8, August 1991.
  • [0009]
    2. High-Frequency low power IC's in a scaled submicrometer HBT technology. IEEE MTT. Vol. 45, No. 12, December 1997.
  • [0010]
    However, this technique requires an expensive exposure process, such as an electron beam writing process or a stepped exposure process, or a complex process involving a formation of sidewalls, to form a self-aligned submicron gate. As a result, there is a drawback of an increase in the manufacturing costs.
  • SUMMARY OF THE INVENTION
  • [0011]
    Therefore, the present invention has been made in view of the above mentioned problems, and an object of the present invention is to provide a submicron gate fabrication method capable of fabricating a reliably self-aligned submicron gate using a simplified process.
  • [0012]
    In order to accomplish this object, the present invention provides a method for fabricating a submicron gate comprising the steps of: (a) laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively; (b) defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner; (c) selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist; and (d) depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate.
  • [0013]
    A contact metal is deposited over the resulting structure with the gate, thereby self-aligning the gate.
  • [0014]
    In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self alignment using a V-shaped submicron gate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description when taken in conjunction with the drawings, in which:
  • [0016]
    [0016]FIG. 1 is a cross-sectional view illustrating an essential laminated structure according to the embodiment of the present invention;
  • [0017]
    [0017]FIG. 2 is a cross-sectional view illustrating a structure obtained after patterning a photoresist (21) using a conventional contact aligner;
  • [0018]
    [0018]FIG. 3 is a cross-sectional view illustrating a structure obtained after selectively wet-etching a first InGaAs layer (12);
  • [0019]
    [0019]FIG. 4 is a cross-sectional view illustrating a structure obtained after selectively wet-etching a first InP layer (13);
  • [0020]
    [0020]FIG. 5 is a cross-sectional view illustrating a structure obtained after depositing a metal (51) over the entire upper surface of the structure shown in FIG. 4, for the formation of a gate;
  • [0021]
    [0021]FIG. 6 is a cross-sectional view illustrating a structure obtained to have a V-shaped gate after lifting off the photoresist (21);
  • [0022]
    [0022]FIG. 7 is a cross-sectional view illustrating a structure obtained after sequentially removing the first InGaAs layer (12) and first InP layer (13);
  • [0023]
    [0023]FIG. 8 is a cross-sectional view illustrating a structure obtained after anisotropically wet-etching a second InGaAs layer (14) and a second InP layer (15) using the V-shaped gate (61), formed in a process of FIG. 7, as a mask; and
  • [0024]
    [0024]FIG. 9 is a cross-sectional view illustrating a final device produced after a self-alignment of the gate.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0025]
    Now, a preferred embodiment of the present invention will be described in detail, with reference to the annexed drawings.
  • [0026]
    FIGS. 1 to 9 illustrate sequential steps of a submicron gate fabrication and self-alignment procedure according to an embodiment of the present invention, respectively.
  • [0027]
    [0027]FIG. 1 illustrates an essential laminated structure according to the embodiment of the present invention in which a dummy emitter is laminated on a general InP/InGaAs heterojunction bipolar transistor (HBT) structure. As shown in FIG. 1, this structure is formed by laminating InGaAs layers (12, 14, and 16), and InP layers (13 and 15) over a Fe-doped InP substrate (11) in an alternating fashion, using a laminated growth equipment such as MOCVD or MBE.
  • [0028]
    The second InP layer (15) defines an emitter region, the second InGaAs layer (14) an emitter cap region, and the third InGaAs layer (16) a base region, respectively. The first InGaAs layer (12) and the first InP layer (13) define dummy emitter regions, respectively. The first InP layer (13) has a thickness H1 more than the thickness H2 of the second InP layer (15) in order to obtain a self-aligned structure. That is, this thickness relation is adapted to satisfy a condition of “L2<L3<L1” in FIG. 8.
  • [0029]
    In order to define a region where a gate is to be formed, a line having a width L1 of about 1 μm is then patterned on the structure of FIG. 1 using a photoresist (21), as shown in FIG. 2. The line width L1 is limited by the resolution of a contact aligner.
  • [0030]
    Thereafter, the first InGaAs layer (12) is selectively etched under the condition in which the patterned photoresist (21) formed at the step of FIG. 2 is used as a mask, as shown in FIG. 3. H3PO4:H2O2:H2O is used as an etchant in order to achieve the selective etching of the first InGaAs layer (12) without any substantial influence on the first InP layer (13).
  • [0031]
    The first InP layer (13) is then etched, as shown in FIG. 4. At this etching step, HCl:H3PO4 is used as an etchant in order to achieve the selective etching of the first InP layer (13) without any substantial influence on the first and second InGaAs layer (12 and 14). Referring to FIG. 4, it can be found that the first InP layer (13) exhibits anisotropic etch characteristics due to an etch selectivity difference resulting from a variation in lattice direction in the first InP layer (13). That is, the first InP layer (13) is not isotropically etched, but anisotropically etched in accordance with the variation in lattice direction, so that it has an inclined etch cross section.
  • [0032]
    Where the etching of the first InP layer (13) is carried out under the condition in which the first InGaAs layer (12) is used as a mask, as shown in FIG. 4, it is begun from the region where the first InGaAs layer (12) is opened, and then anisotropically progressed along the depth of the first InP layer (13) so that the etch cross section of the first InP layer (13) has an inclination θ. The etching of the first InP layer (13) is stopped by the second InGaAs layer (14), so that the second InGaAs layer (14) and the second InP layer (15) are hardly etched.
  • [0033]
    The inclination θ is determined by the kind, concentration, and temperature of the etchant used.
  • [0034]
    The bottom width of the etch cross section, L2, is determined by the line width L1, the thickness of the first InP layer (13), H1, and the inclination θ. That is, the bottom width L2 corresponds to “L1−2H1/tan θ” (L2=L1−2H1/tan θ). Accordingly, L2 of a submicron unit can be appropriately defined by adjusting L1, H1, and θ.
  • [0035]
    Subsequently, a contact metal (51) is deposited over the entire upper surface of the structure obtained at the step of FIG. 4, using an electron-beam evaporator or a thermal evaporator, as shown in FIG. 5. At this time, the contact metal (51) has a V-shaped structure at a portion thereof deposited at the region where the first InP layer (13) is etched. The V-shaped structure of the contact metal (51) has an inclination corresponding to the inclination formed by the anisotropic etching of the first InP layer (13).
  • [0036]
    Thereafter, the portion of the contact metal (51) arranged on the photoresist (21) is lifted off along with the photoresist (21), as shown in FIG. 6.
  • [0037]
    Following the lift-off process, the first InGaAs layer (12) and first InP layer (13) are selectively etched, thereby forming a gate (61) made of the remaining contact metal (51), as shown in FIG. 7. Using the gate (61) as a mask, the second InGaAs layer (14) and second InP layer (15) arranged beneath the gate (61) are then sequentially etched in accordance with an anisotropic wet etch process. For the etching of the first and second InGaAs layer (12 and 14), H3PO4:H2O2:H2O is used as an etchant whereas HCl:H3PO4 is used as an etchant for the first and second InP layers (13 and 15). After the completion of the etching steps, an inclined structure made of the second InP layer (15) is obtained which has an inclination resulting from a variation in etch selectivity exhibited in the second InP layer (15). The bottom width of the inclined structure, L3, is also determined by the line width L1, the inclination θ, and the thickness of the second InP layer (15), H2. That is, the bottom width L3 corresponds to “L2+2H2/tan θ” (L3=L2+2H2/tan θ). Since H2 is less than H1, L3 is more than L2 even though it is less than L1. Of course, the inclination θ associated with L3 corresponds to the inclination θ associated with L2.
  • [0038]
    Thus, the gate (61) has a self-aligned structure in that its region includes the region defined by L3.
  • [0039]
    Finally, a contact metal (91) is deposited over the structure obtained after the process of FIG. 8, for a self-alignment of the gate, as shown in FIG. 9.
  • [0040]
    As apparent from the above description, in accordance with the present invention, the fabrication of a submicron gate is carried out using the existing exposure process such as an anisotropic wet etch process without use of any separate equipment. Accordingly, it is possible to simplify the fabrication of the submicron gate, thereby achieving a reduction in the manufacturing costs.
  • [0041]
    In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self-alignment using a V-shaped submicron gate.
  • [0042]
    Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7736956Mar 26, 2008Jun 15, 2010Intel CorporationLateral undercut of metal gate in SOI device
US7781771Feb 4, 2008Aug 24, 2010Intel CorporationBulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7820513Oct 28, 2008Oct 26, 2010Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7858481 *Jun 15, 2005Dec 28, 2010Intel CorporationMethod for fabricating transistor with thinned channel
US7879675May 2, 2008Feb 1, 2011Intel CorporationField effect transistor with metal source/drain regions
US7898041Sep 14, 2007Mar 1, 2011Intel CorporationBlock contact architectures for nanoscale channel transistors
US7902014Jan 3, 2007Mar 8, 2011Intel CorporationCMOS devices with a single work function gate electrode and method of fabrication
US7960794Dec 20, 2007Jun 14, 2011Intel CorporationNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7989280Dec 18, 2008Aug 2, 2011Intel CorporationDielectric interface for group III-V semiconductor device
US8067818Nov 24, 2010Nov 29, 2011Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US8071983May 8, 2009Dec 6, 2011Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US8084818Jan 12, 2006Dec 27, 2011Intel CorporationHigh mobility tri-gate devices and methods of fabrication
US8183646Feb 4, 2011May 22, 2012Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8268709Aug 6, 2010Sep 18, 2012Intel CorporationIndependently accessed double-gate and tri-gate transistors in same process flow
US8273626Sep 29, 2010Sep 25, 2012Intel CorporationnNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US8294180Mar 1, 2011Oct 23, 2012Intel CorporationCMOS devices with a single work function gate electrode and method of fabrication
US8362566Jun 23, 2008Jan 29, 2013Intel CorporationStress in trigate devices using complimentary gate fill materials
US8368135Apr 23, 2012Feb 5, 2013Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8399922Sep 14, 2012Mar 19, 2013Intel CorporationIndependently accessed double-gate and tri-gate transistors
US8405164Apr 26, 2010Mar 26, 2013Intel CorporationTri-gate transistor device with stress incorporation layer and method of fabrication
US8502351Sep 23, 2011Aug 6, 2013Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US8581258Oct 20, 2011Nov 12, 2013Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US8617945Feb 3, 2012Dec 31, 2013Intel CorporationStacking fault and twin blocking barrier for integrating III-V on Si
US8664694Jan 28, 2013Mar 4, 2014Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8741733Jan 25, 2013Jun 3, 2014Intel CorporationStress in trigate devices using complimentary gate fill materials
US8749026Jun 3, 2013Jun 10, 2014Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US8816394Dec 20, 2013Aug 26, 2014Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8912099 *Jul 30, 2013Dec 16, 2014Mitsubishi Electric CorporationMethod of manufacturing semiconductor device
US8933458Oct 8, 2013Jan 13, 2015Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US9048314Aug 21, 2014Jun 2, 2015Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9190518May 8, 2014Nov 17, 2015Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US9224754May 8, 2014Dec 29, 2015Intel CorporationStress in trigate devices using complimentary gate fill materials
US9337307 *Nov 18, 2010May 10, 2016Intel CorporationMethod for fabricating transistor with thinned channel
US9368583May 1, 2015Jun 14, 2016Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9385180Dec 18, 2014Jul 5, 2016Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US9450092Nov 11, 2015Sep 20, 2016Intel CorporationStress in trigate devices using complimentary gate fill materials
US9614083Jun 10, 2016Apr 4, 2017Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9741809Sep 16, 2015Aug 22, 2017Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US9748391Feb 24, 2017Aug 29, 2017Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9761724Jun 14, 2016Sep 12, 2017Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US9806193Aug 29, 2016Oct 31, 2017Intel CorporationStress in trigate devices using complimentary gate fill materials
US9806195Mar 14, 2016Oct 31, 2017Intel CorporationMethod for fabricating transistor with thinned channel
US20080169512 *Dec 20, 2007Jul 17, 2008Doyle Brian SNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20090061572 *Oct 28, 2008Mar 5, 2009Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US20110020987 *Sep 29, 2010Jan 27, 2011Hareland Scott ANonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US20110062520 *Nov 18, 2010Mar 17, 2011Brask Justin KMethod for fabricating transistor with thinned channel
Classifications
U.S. Classification438/312, 438/321, 257/E21.387
International ClassificationH01L29/73, H01L21/28, H01L29/737, H01L21/331, H01L29/417, H01L21/3213
Cooperative ClassificationH01L29/66318
European ClassificationH01L29/66M6T2V2
Legal Events
DateCodeEventDescription
Dec 28, 2000ASAssignment
Owner name: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JEON, SOO KUN;KIM, MOON JUNG;YANG, KYOUNG HOON;AND OTHERS;REEL/FRAME:011421/0476
Effective date: 20001220
Sep 23, 2005FPAYFee payment
Year of fee payment: 4
Sep 16, 2009FPAYFee payment
Year of fee payment: 8
Nov 22, 2013REMIMaintenance fee reminder mailed
Apr 16, 2014LAPSLapse for failure to pay maintenance fees
Jun 3, 2014FPExpired due to failure to pay maintenance fee
Effective date: 20140416