US 20010028578 A1
Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
1. A split-gate flash memory cell comprising:
a tunnel oxide formed by oxidation of a textured monocrystalline substrate;
a first floating gate electrode formed over said tunneling oxide;
a gate oxide, separate from the tunneling oxide, formed on a non-textured portion of said monocrystalline substrate; and
a second control electrode formed over said first floating gate electrode and said gate oxide.
2. The split-gate flash memory cell according to
3. The split-gate flash memory cell according to
4. The split-gate flash memory cell according to
5. The split-gate flash memory cell according to
6. The split-gate flash memory cell according to
7. The split-gate flash memory cell according to
8. A method for producing a split-gate flash memory cell comprising the steps of:
forming a tunnel oxide by oxidation of a textured monocrystalline substrate;
forming a first floating gate electrode over said tunneling oxide;
forming a gate oxide, separate from the tunneling oxide, on a non-textured portion of said monocrystalline substrate; and
forming a second control electrode over said first floating gate electrode and said gate oxide.
9. The method according to
self-aligning said first floating gate with said tunneling oxide.
10. The method according to
forming an oxide-nitride-oxide dielectric between said first floating gate electrode and said second control electrode.
11. The method according to
12. The method according to
13. The method according to
17. The method according to
18. A method for programming a split-gate flash memory cell comprising the steps of:
increasing a threshold voltage on a first floating gate electrode by channel initiated secondary electrons, said first floating gate electrode being formed over a tunnel oxide that has been oxidized on a textured monocrystalline substrate; and
applying a voltage to a second control electrode formed over said first floating gate electrode and a gate oxide, said gate oxide being separate from the tunneling oxide and being formed on a non-textured portion of said monocrystalline substrate.
 The present application relates to a co-pending application filed concurrently herewith, entitled: METHOD AND APPARATUS FOR PRODUCING A SINGLE POLYSILICON FLASH EEPROM (Attorney Docket No. 029300-437), the disclosure of which is hereby incorporated by reference in its entirety.
 1. Field of the Invention
 The present invention is generally directed to semiconductor memories, and more particularly, to the development of memory cells which can be easily integrated with high performance logic technologies.
 2. State of the Art
 Those skilled in the art appreciate the desirability of embedding memory technology such as dynamic random access memories (DRAMs), static random access memories (SRAMs), read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs into high performance logic technologies. However, at present, only technologies such as SRAM and ROM are straightforward to integrate into high performance logic technologies. Technologies, such as EEPROM and DRAM technologies are highly dedicated to their specific needs, and are very complex, rendering them unsuitable for straightforward, easy integration into high performance logic technologies.
 For example, EEPROM technology is typically implemented using one of four basic cell types: (1) the one transistor stacked-gate flash EEPROM cell; (2) the one and one half transistor split-gate flash EEPROM cell; (3) the double-gate two transistor EEPROM cell; and (4) cells which use edges for control or select gates. There have also been proposals regarding flash memory cells which form self-aligned trenches at the edge of a partially formed stack-gate structure. However, each of these technologies suffers drawbacks which inhibits their straightforward, easy integration into high performance logic technologies.
FIG. 1A shows a typical one transistor stacked-gate flash EEPROM cell. Stacked-gate flash EEPROM cells are available from Intel Corp. and Advanced Micro Devices Corp. (e.g., the Intel E28F016SA 16 Mbit flash memory and the AMD AM29F016 16 Mbit flash memory), having basic cell sizes of approximately 6 and 7 times the minimum feature size (f) squared (i.e., f2), respectively. However, these cells possess a very complex source-drain region which requires as many as four ion implants. These submicron cells are subject to punch through, premature breakdown at the drain, and various read disturb problems. In addition, the cells are susceptible to over erase, which can lead to a permanently turned-on device. These cells are also difficult to downward scale, because high voltages are required for the erase and program functions. Erasure is performed by taking an extended source diffused region to a high positive value to pull electrons from the floating gate by Fowler-Nordheim (FN) tunneling to make the floating gate more positive. The erase function is performed by lowering the floating gate threshold voltage VT, while programming is accomplished by applying high voltage to the drain and to the control gate formed with a second polysilicon layer (i.e., poly 2) to inject hot electrons from a channel near the drain onto the floating gate to raise the threshold voltage. That is, programming is achieved using hot electron injection by applying high voltage to the control gate. The high voltage (e.g., approximately 12 volts) requires inclusion of separate high voltage transistors.
 The exemplary FIG. 1 cell involves using two levels of polysilicon. Typical products use a NOR configuration, where each cell is configured with a bit line (BL) connection to the drain, a poly 2 control line (CL) or word line (WL), and a diffused source line (SL). The high voltages required for this device require building separate high voltage transistors which may have longer distances between the source of drain diffusion (i.e., longer Leff) and thicker gate oxides, thereby adding to the overall size of a memory device implemented with these cells.
 A one and one-half transistor split-gate flash EEPROM, as shown in FIG. 1B, avoids the over erase problem described with respect to the stacked-gate flash EEPROM cell, but is a larger cell size than the stacked gate. For a split-gate cell using modern shallow trench isolation (STI), an n+ source line self-aligned to the poly, self-aligned tungsten plug contacts, and conservative poly 1 to poly 2 aligment tolerances, a typical cell area can be on the order of approximately 10 f2. Lower n+ source regions may be created in the substrate by etching the oxide in an STI region down to the substrate. The poly 2 layer and a resist mask are used to protect other shallow trench isolation (STI) regions during etching.
 A double-gate two transistor EEPROM cell is shown in FIG. 1C, and includes a separate select transistor to permit erasure of individual cells. Such a cell is, for example, available from Atmel in its AT17C128 128 k serial EEPROM, which has a cell area of approximately 17 f2 for 1.0 micron rules. The cell is relatively large and is not used in flash EEPROMs.
FIG. 1D illustrates an exemplary cell which uses polysilicon edges for control of select gates. For example, exemplary versions of this cell use closely spaced polysilicon edges for voltage coupling. Although the cells are smaller than the cells discussed previously, they are very complex as reflected, for example, in the Sandisk 35 bit triple-polysilicon flash EEPROM, which is approximately 5 f2 in cell area using 0.6 micron rules. Because of their complexity, they are unsuited to integration in high performance logic technology.
FIG. 1E shows an exemplary flash memory cell described in a document entitled “A 0.24 μm 2 Well Process with 0.18 μm Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash Memories”, by Takashi Kobayashi et al, 1997 IEDM, page 275. Again, the process of producing such a cell is complex, and impractical for integration into high performance logic technology.
 Because numerous applications exist for integrating flash EEPROM technology with high performance complementary metal oxide semiconductor (CMOS) logic devices (e.g., microprocessors), the development of such a technology would be highly desirable. For example, the applications for such an integrated technology include software updates, storing identification codes, system reconfiguration in the field, look-up tables, manufacturing codes, nonvolatile data storage, smart cards which use flash embedded memory, prototyping, and various programmable logic devices and field programmable gate arrays.
 Known process technologies do not lend themselves to easy integration of commodity flash EEPROM cells with logic devices, such as high performance CMOS devices. That is, known processes, including processes as described in a document entitled “EEPROM/Flash Sub 3.0 V Drain-Source Bias Hot Carrier Rating”, by J. D. Bude et al., 1995 IEDM, page 989 and in a document entitled “Secondary Electron Flash-A High Performance Low Power Flash Technology for 0.25 μm and Below, by J. D. Bude et al., 1997, IEDM page 279, do not sufficiently simplify the flash EEPROM cell and fabrication process to permit straightforward integration into conventional high performance logic processes. In these documents, structural properties of submicron stacked gate EEPROM devices are disclosed which yield devices that can be programmed at low voltages. The properties are: (1) thin tunneling oxides (e.g., in a range of approximately 60 angstroms (Å)-100 Å); (2) heavily-doped shallow n+ junctions with boron halo implants, giving abrupt junctions; and (3) a negative substrate bias.
 In addition to process compatibility problems, scaling EEPROM technology into the 0.25 μm regime and below, as is used on typical high performance logic processes, has not been realized. Those skilled in the art have suggested that scaling EEPROM devices is subject to physical limits which may inhibit a reduction in cell size (see, for example, “Nonvolatile Semiconductor Memory Technology”, by William D. Brown and Joe E. Brewer, IEEE, Press 1998, page 130). Given the wide applicability of flash EEPROM technology, it would be desirable to avoid the process compatibility problems associated with integrating typical cell designs with conventional logic devices by developing a cell which can be easily integrated into high performance logic processes.
 Accordingly, exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split-gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
 Generally speaking, exemplary embodiments are directed to a split-gate flash memory cell comprising: a tunnel oxide formed by oxidation of a textured monocrystalline substrate; a first floating gate electrode formed over said tunneling oxide; a gate oxide, separate from the tunneling oxide, formed on a non-textured portion of said monocrystalline substrate; and a second control electrode formed over said first floating gate electrode and said gate oxide. An exemplary flash-EEPROM cell implemented in accordance with exemplary embodiments of the present invention is straightforward to integrate into high performance logic processes. In addition, the cell is free from the over erase problem of one transistor stacked-gate flash EEPROM cells, and can more easily be downward scaled. In addition, the cell can be programmed and erased at lower voltages, thereby eliminating process complexity associated with accommodating high on-chip voltages.
 The foregoing and other objects and features of the present invention will become more apparent from the following detailed description of preferred embodiments when read in connection with the accompanying drawings, wherein:
 FIGS. 1A-1E illustrate exemplary conventional EEPROM cells;
 FIGS. 2A-2I illustrate an exemplary process flow for implementing a flash EEPROM cell in accordance with the present invention;
 FIGS. 3A-3C illustrate exemplary erase, program and read functions of a flash EEPROM cell in accordance with the present invention; and
FIG. 4 illustrates an exemplary cell layout in accordance with the present invention.
 FIGS. 2A-2I, illustrate an exemplary process flow for producing a self-aligned, textured-substrate tunneling-oxide under a floating gate, and a standard oxide-nitride-oxide (ONO) dielectric over the floating gate for a high coupling ratio in accordance with exemplary embodiments of the present invention. In FIG. 2A, a first polysilicon layer 202 is deposited on a single crystal (i.e., monocrystalline) silicon substrate 200. In an exemplary embodiment, the first polysilicon layer (i.e., poly 1 layer) is approximately 120 Å in thickness, or any thickness on the order of 120 Å.
 In FIG. 2B, the first polysilicon layer is oxidized into the substrate to form an oxidation layer 204 of, for example, approximately 300 Å, or any thickness suitable for forming an acceptable textured surface as shown in FIG. 2C. FIG. 2C illustrates a stripping of the oxidation layer 204, resulting in the formation of a textured (i.e., rough) surface 206 on the single crystal silicon substrate 200. In FIG. 2D, a tunnel oxide layer 208 is grown on the textured surface 206. In exemplary embodiments, the tunnel oxide layer is grown with a depth of, for example, approximately 60 to 100 Å, and will ultimately have the floating gate formed over it.
FIG. 2E illustrates the depositing and formation of an oxide-nitride-oxide (ONO) dielectric layer 210 after first depositing a new first polysilicon layer 212 (poly 1 layer). The ONO layer 210 is deposited in known fashion, and can, for example, have a thickness of approximately 100-150 Å. The ONO layer 210 will constitute an interpoly dielectric formed between the poly 1 layer 212 and a later formed poly 2 layer.
 In FIG. 2F, a photoresist layer is deposited on the interpoly ONO 210 and is used to form a photoresist mask 214. The photoresist mask 214 is used to perform a photoresist etch into the substrate (e.g., to a depth on the order of approximately 10-100 Å into the substrate). The etch into the substrate is sufficient to remove unmasked portions of the textured surface 206. The textured surface is removed in portions of the substrate to permit a regular gate oxide to be grown thereon. As such, a self-aligning process is used to ensure that the textured surface 206 is retained only beneath the remaining portions of the poly 1 layer 212.
 In FIG. 2G, the photoresist mask 214 has been removed and a gate oxide has been grown on exposed surfaces of the substrate and poly 1. A sacrificial oxide may be formed and stripped prior to gate oxide formation as is known in the art. FIG. 2G illustrates a regrowth of a gate oxide 216 with a thickness of, for example, approximately 100 Å. In FIG. 2H, a second polysilicon layer 218 (i.e., poly 2 layer) has been deposited over the FIG. 2G structure.
FIG. 2I shows the formation of a control gate from the poly 2 layer 218 with a stepped configuration relative to the remaining portion of the poly 1 layer 212 that constitutes the floating gate of the cell structure. The control gate is formed by etching the poly 2 layer 212 using a technique similar to that described above with respect to the etching of the poly 1 layer to form the floating gate. The right hand edges of the floating gate and the control gate (as viewed in FIG. 2I) can be aligned using a self-aligned etching procedure (i.e., whereby the edges of the poly 2 and poly 1 layers are etched together). Afterwards, a reoxidation process can be used to grow an oxide layer 220 over the exposed surfaces of the control gate and floating gate. Those skilled in the art will appreciate that a relatively tall gate edge on a source side of the cell (i.e., shown to the left in FIG. 2I) facilitates the use of a self-aligned contact there, because the thickness of the edge spacer will increase.
 Referring to FIG. 3, a flash EEPROM cell configured using a process such as that described with respect to FIG. 2 can take into account the various conditions described by Bude regarding structural properties of submicron gate EEPROM devices; i.e., use of thin tunneling oxides, heavily doped shallow n+ junctions with boron halo implants, and negative substrate bias. The substrate bias can be facilitated by using a triple well process, such as a p-well in a deep n-well on a p-substrate. As such, conventional n-well on p-type material can be used for construction of the logic circuits. The bias on the p-well, where the flash cells are constructed, can be applied using on-chip voltage generation circuits, or the voltage can be supplied externally. As such, a device produced using the FIG. 2 process can include erase, program and read functions that are implemented in a manner as illustrated with respect to FIGS. 3A-3C respectively.
 Referring to FIGS. 3A-3C, relatively low programming voltages can be used in conjunction with the device produced using the FIG. 2 process. In FIGS. 3A-3C, the flash EEPROM cell is a 3.3 volt design, and all voltages used for the erase, program and read functions can be generated on-chip without high voltage transistors.
 More particularly, referring to FIG. 3A, an erase function is illustrated for a flash EEPROM cell produced using the process described with respect to FIG. 2. Boron halo implants 301 and 303 are formed in source and drain regions, respectively. FIG. 3A illustrates heavily-doped shallow n+ junctions 302 and 304 in a p-well of substrate 300 for the source and drain portions of the cell. These regions are formed in similar fashion to the well known LDD process but with a higher dose implant. Somewhat deeper, more conductive, heavily doped regions 306 and 308 are also formed as part of the source and drain regions.
 The source drain regions can be formed together with use of a triple well process. The substrate can be negatively biased, with the p-type well being formed in a deep n-well on a p-type substrate, thereby constituting the triple well process which facilitates substrate biasing. A voltage supply contact VS for the source, Vd for the drain, VCG for the control gate, and VB for the substrate biasing are also provided.
 The erase function is implemented by floating VS, placing VCG at ground, supplying a voltage pulse of, for example, 5 volts to the drain (i.e., Vd) and placing VB at ground. The threshold voltage VT at the floating gate drops below approximately 1 volt. Thus, for an erase condition, VT is relatively low. For example, for a target VT of 0.5 volts, the floating gate potential is about 1.0 volts (electrons depleted), which is too low to cause significant linkage by the Fowler-Nordheim process. To erase the floating gate in a relatively short time, the electric field should be sufficiently high that the Fowler-Nordheim conduction is operative.
 In exemplary embodiments, for 100 Å silicon dioxide dielectrics, 5 volt pulses on the drain produce currents on the order of 10−4 to 10−5 A/cm2. (This assumes that for the n+ poly-n+ substrate structure which accomplishes the tunneling, the flat band voltage which reduces the electric field across the oxide is negligible). Because the threshold shift is given roughly by Q/Co, where Q is the charge transfer to the floating gate and C0 is the floating gate-to-substrate capacity per unit area, substituting Jt for Q where J is the current density and t is time and seconds, for a three volt shift, only about 0.01 seconds are required. The actual erase time can be on the order of 5 to 10 times longer because the drain extension area under the floating gate is less than the total floating gate area, in exemplary embodiments. Those skilled in the art will appreciate that a value of a 3 volt shift is by way of example only.
 The n+ extensions shown in FIG. 3A can be formed prior to spacer formation using, for example, a phosphorus or arsenic implant of approximately 5×1014 atoms/cm2 and using a drive-in/activation step with RTA such that a junction depth is approximately 0.1 to 0.2 μm. This yields an exemplary doping concentration of mid 1019 atoms/cm3 range. Some diffusion underlap of the floating gate is used to accomplish the erase function.
 Those skilled in the art will appreciate that the values used for the various voltages of the FIG. 3A erase function, as well as those discussed with respect to FIGS. 3B and 3C, can be modified as desired. For example, the erase function can be performed at lower Vd values by, for example, using a thinner tunneling oxide.
FIG. 3B illustrates an exemplary program function wherein an increased threshold voltage on a floating gate electrode is caused by channel initiated secondary electrons. As mentioned above, a device configured and produced in accordance with exemplary embodiments of the present invention can be programmed using relatively low voltages. For a charge to be retained over a long period of time (e.g., many years) on the floating gate upon programming, given an exemplary VT of approximately 2 to 4 volts (measured at VB=0), the electric field should be low enough that the Fowler-Nordheim conduction mechanism is non-operative. Silicon dioxide leakage current densities are, for example, on the order of 10−15 A/cm2. This is achieved by forming dielectrics at an upper range of resistivities, by using dry O2 oxidation recipes known to those skilled in the art.
 Because the Fowler-Nordheim currents are much lower when leakage flows from negatively charged electrodes, the programmed VT is held by a negatively charged floating gate. The program state can be maintained a long period of time when the voltage-to-substrate electric field residing at the floating gate is small.
 The threshold voltage at the floating gate VT of an n-channel transistor with a channel doping concentration of about 2×1017 atoms/cm3, which is a value suitable for technologies in the 0.25 to 0.5 micron range is given by:
V T=ΦMS −Q F /C 0+2ΦF+[2εSε0 qN A(2ΦF +V BG)]½/C 0 +V FG +Σq/C 0
 where ΦMS is the metal-silicon work function, QF is the fixed charge, ΦF is the Fermi potential, Co is the capacitance, εS is the dielectric constant for silicon, ε0 is the permitivity of free space, VBG is the back gate, VFG is the voltage left on the field gate after programming, Σ is the boron threshold-adjust implant dose, and q is the charge on the electron.
 For the programmed state, the VT is Sufficiently high that the transistor will not turn on. Substituting VT=3V (measured at VBG=0), a low value for QF, VBG=0V, using 100 Å for the gate oxide thickness, other exemplary values appropriate for NA=2×1017 atoms/cm3, and Σq=0, the voltage on the VFG is about −0.5 V (electrons accumulated). This would yield a low electric field of 0.5×106 V/cm where almost no tunneling currents would flow. Programming can be done with a back gate bias, but the target threshold voltage is without that bias because the read condition is also without the bias. This lowers the charge on the floating gate, which must be held over a long time. The VT target can be lower, of course, making the charge on the floating gate even lower. Various other conditions can be specified for scaled technologies, as will be apparent to those skilled in the art.
 The relatively high doping concentration in the channel, near the surface can be the accumulation of several possible boron implants including the p-well, punch through and threshold adjust. Known halo implant processes can be used to produce the halo implants, and thereby improve punch through and other properties.
FIG. 3C shows exemplary voltages associated with a read function. Hot electron reliability problems are avoided by using a low VD during the read operation. Exemplary voltages are as follows: VS and VB are at 0 volts and VCG is approximately 3.3 volts, VD is approximately 1-2 volts. A low VT constitutes an on condition representing a “1” and a high VT constitutes an off condition constituting a “0” condition.
 Exemplary embodiments of a flash EEPROM cell configured as discussed with respect to FIGS. 3A-3C and produced using a process as described with respect to FIG. 2 can be readily integrated into conventional high performance logic processes. For example, at the 0.25 micron level, it is common in conventional high performance logic technologies to first form shallow trench isolation regions using a silicon nitride layer that serves as a chemical mechanical polish (CMP) stop after filing with SiO2. The wells can then be formed using high voltage ion implantation. The floating gates are then formed as disclosed in FIG. 2. The second polysilicon layer (i.e., poly 2) serves as gate electrodes for the logic transistors. The poly 2 layer can be formed as a polycide, or a salicide process can be used. Self aligned contacts can be formed using appropriate dielectric spacers as is known by those skilled in the art. The logic transistors can be formed as lightly doped drains (LDDS) with spacers. Extensions for the flash transistors can be doped at a higher level using appropriate masking an ion implantation steps. Thus, those skilled in the art will appreciate that a process for forming the FIG. 3 cell can be easily integrated with a high performance logic process.
FIG. 4 is an exemplary layout of a split gate, double poly structure suitable for the novel textured substrate EEPROM cell shown in FIGS. 2 and 3. The cell area is about 8 to 10 f2 depending on alignment tolerances. Shown is n+ source line 401, floating gate 402, word line poly 2 403, self align tungsten plug contacts 404, bit line 405, STI regions 406, and drain contact 407. Not shown are their dielectrics and details of the n+ doped regions, which will be apparent to those skilled in the art.
 Those skilled in the art will appreciate that the embodiments and processes described above are by way of example only. For example, additional steps can be added to the process discussed with respect to FIG. 2 and or additional features and/or voltages can be used in conjunction with the device illustrated in FIGS. 3A-3C.
 It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.