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Publication numberUS20010029087 A1
Publication typeApplication
Application numberUS 09/854,949
Publication dateOct 11, 2001
Filing dateMay 14, 2001
Priority dateJan 12, 1999
Also published asUS6235611, US6424017
Publication number09854949, 854949, US 2001/0029087 A1, US 2001/029087 A1, US 20010029087 A1, US 20010029087A1, US 2001029087 A1, US 2001029087A1, US-A1-20010029087, US-A1-2001029087, US2001/0029087A1, US2001/029087A1, US20010029087 A1, US20010029087A1, US2001029087 A1, US2001029087A1
InventorsAnthony Kurtz, Alexander Ned
Original AssigneeKurtz Anthony D., Ned Alexander A.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for making silicon-on-sapphire transducers
US 20010029087 A1
Abstract
An improved method for making silicon-on-sapphire transducers including the steps of: forming a first silicon layer on a first side of a first sapphire wafer; bonding a second sapphire wafer to the first side of the first sapphire wafer such that the first silicon layer is interposed between the first and second sapphire wafers; reducing the thickness of the first sapphire wafer to a predetermined thickness; depositing a second silicon layer on a second surface of the first sapphire wafer, wherein the second surface of the first sapphire wafer is oppositely disposed from the first surface of the first sapphire wafer; bonding a silicon wafer to the second surface of the first sapphire wafer such that the second silicon layer is interposed between the first sapphire wafer and the silicon wafer, wherein the silicon wafer includes p+ regions indicative of a transducer structure and non-p+ regions; and, removing the non-p+ regions of the silicon wafer thus forming the transducer structure of p+ regions on the second surface of the first sapphire wafer.
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Claims(20)
I claim:
1. An improved method for making silicon-on-sapphire transducers comprising the steps of:
forming a first silicon layer on a first side of a first sapphire wafer;
bonding a second sapphire wafer to said first side of said first sapphire wafer such that said first silicon layer is interposed between said first and second sapphire wafers;
reducing the thickness of said first sapphire wafer to a predetermined thickness;
depositing a second silicon layer on a second surface of said first sapphire wafer, wherein said second surface of said first sapphire wafer is oppositely disposed from said first surface of said first sapphire wafer;
bonding a silicon wafer to said second surface of said first sapphire wafer such that said second silicon layer is interposed between said first sapphire wafer and said silicon wafer, wherein said silicon wafer includes p+ regions indicative of a transducer structure and non-p+ regions; and,
removing said non-p+ regions of said silicon wafer thus forming said transducer structure of p+ regions on said second surface of said first sapphire wafer.
2. The method of
claim 1
, wherein said second sapphire wafer comprises a plurality of apertures.
3. The method of
claim 2
, wherein each of said plurality of apertures is approximately 0.150 inches in diameter.
4. The method of
claim 1
, wherein said second sapphire wafer is E.S. bonded to said first sapphire wafer.
5. The method of
claim 1
, wherein said second sapphire wafer is fusion bonded to said first sapphire wafer.
6. The method of
claim 1
, wherein said step of reducing the thickness of said first sapphire wafer comprises the step of lapping, or polishing said second surface of said first sapphire wafer until said first sapphire wafer is approximately of said predetermined thickness.
7. The method of
claim 6
, wherein said predetermined thickness is approximately 0.005 inches.
8. The method of
claim 1
, wherein said depositing of said second silicon layer comprises sputtering.
9. The method of
claim 1
, wherein said depositing of said second silicon layer comprises growing said second silicon layer.
10. The method of
claim 1
, further comprising the step of oxidizing said second silicon layer.
11. The method of
claim 10
, wherein said silicon wafer is fusion bonded to said oxidized second surface of said first sapphire wafer.
12. The method of
claim 11
further comprising the step of sealing a non-conductive wafer including a depression in a surface thereof to said second surface of said first sapphire wafer over said p+ regions.
13. The method of
claim 12
, wherein said step of sealing comprises the step of E.S. bonding.
14. The method of
claim 13
, further comprising the step of forming a plurality of apertures in said non-conductive wafer at given locations corresponding to electrical contact locations.
15. The method of
claim 14
, wherein said non-conductive wafer comprises glass.
16. The method of
claim 15
, further comprising the step of filling each of said plurality of apertures in said non-conductive wafer with a glass metal frit.
17. The method of
claim 1
, wherein said silicon wafer comprises a sensor network and a plurality of contact areas, and said method further comprises the step of selectively etching those portions of said silicon wafer not corresponding to said sensor network or any of said contact areas.
18. A silicon-on-sapphire semiconductor structure comprising:
a sapphire wafer of a predetermined thickness;
a silicon layer formed on a surface of said first sapphire wafer; and,
p+ regions configured in a predetermined pattern indicative of a semiconductor structure bonded to said surface of said first sapphire wafer such that said silicon layer is interposed between said p+ regions and said sapphire wafer.
19. The structure of
claim 18
, wherein said silicon layer is oxidized.
20. An improved method for making silicon-on-sapphire semiconductor structures comprising the steps of:
forming a first silicon layer on a first side of a first sapphire wafer;
bonding a second sapphire wafer to said first side of said first sapphire wafer such that said first silicon layer is interposed between said first and second sapphire wafers;
reducing the thickness of said first sapphire wafer to a predetermined thickness;
depositing a second silicon layer on a second surface of said first sapphire wafer, wherein said second surface of said sapphire wafer is oppositely disposed from said first surface of said first sapphire wafer;
bonding a silicon wafer to said second surface of said first sapphire wafer such that said second silicon layer is interposed between said first sapphire wafer and said silicon wafer, wherein said silicon wafer includes regions of a first conductivity type indicative of a transducer structure and regions of a second conductivity type; and,
removing said regions of said second conductivity type thus forming said semiconductor structure of said regions of said first conductivity type on said second surface of said first sapphire wafer.
Description
FIELD OF INVENTION

[0001] The present invention relates to silicon-on-sapphire transducers, and more particularly to an improved method for making the same.

BACKGROUND OF INVENTION

[0002] As is known, as a deflecting diaphragm, single-crystal sapphire has certain unique advantages. Not only is it a single crystal that displays no mechanical hysteresis when deflected, exhibiting only elastic deformation, but is ultra-resistant to almost any chemical attack or etching. While this may be an advantage in a finished transducer, it causes significant difficulties in fabrication.

[0003] Sapphire has a modulus of about 70106 PSI as compared to that of silicon which, in the transverse direction in the surface plane <100> (as defined on FIG. 4A), is about 20106 PSI. As a result, for the same electrical output from a piezoresistive Wheatstone bridge silicon grown or otherwise fastened to sapphire, the flexing diaphragm must be thinner by the ratio of YaL 2 O 3 Ysi ( 1 )

[0004] This means that to fabricate a pressure transducer of sapphire with the same surface stress as one of silicon, since the surface stress is proportional to 1 Y a 2 t 2 ( 2 )

[0005] where a is the radius of the deflecting portion and t is the thickness, a diaphragm of sapphire must have a much larger diameter than one of silicon, or be much thinner.

[0006] However, because of the inert nature of sapphire, it is almost impossible to thin the sapphire diaphragm by conventional means. Further, making a diaphragm of sufficient size to get enough stress lowers the number of sensors that can be made from an individual slice as well as lowering the resultant natural frequency of the finished sensors. Additionally, slices of commercially available sapphire are usually thick (about 0.020″). However, for a relatively small diameter sensor, a thickness on the order of 0.005 inches is required.

[0007] The present invention is designed to overcome these constraints and to produce a relatively smaller silicon on sapphire sensor with enhanced characteristics.

SUMMARY OF INVENTION

[0008] An improved method for making silicon-on-sapphire transducers including the steps of: sputtering or otherwise growing a silicon layer on a first surface of a commercially available first sapphire wafer.

[0009] Affixing a second sapphire wafer including a series of apertures to the first surface the first sapphire wafer, preferably by means of E.S. bonding, fusion bonding or any other suitable means as is understood by those possessing ordinary skill in the pertinent art.

[0010] Lapping and polishing a second surface of the first sapphire wafer until the first sapphire wafer is reduced to a desired thickness. The second sapphire wafer, which was previously secured to the first wafer, serves to strengthen the first wafer during this process.

[0011] Growing and/or sputtering a silicon layer on the now polished surface of the first sapphire wafer. This silicon layer is then oxidized using any well known, conventional technique.

[0012] A third wafer containing a series of sensor networks is formed using any suitable process. The third wafer includes p+ areas which include a sensor network and a group of contact areas extending from the sensor network. Outside of the contact areas, another p+ area separate from the contact areas but surrounding them, is also formed. The third wafer is then preferably fusion-bonded to the oxidized surface of the first sapphire wafer, and the non p+ areas are removed preferably by using a conductivity selective etch.

[0013] Appropriate areas in the p+ contact regions are preferably metalized using a high temperature metal system such as platinum silicide, titanium, or platinum.

[0014] A fourth wafer made of glass or any suitable, non-conductive material, is prepared such that there are a series of apertures corresponding to the various metalized contact areas on the first wafer. Additionally, there is preferably provided a slight depression in the fourth wafer corresponding to the area of the sensor network to allow the diaphragm to deflect without touching the glass.

[0015] Finally, the glass wafer is preferably sealed using an ES Bond to the p+ contact areas, and the apertures over the metalized areas may be filled with a glass metal frit to make electrical contacts to metalized areas of the p+ regions. If the seal of the glass wafer to the p+ contact area is not through a central aperture in the glass wafer over the deflecting portion of the first sapphire wafer, an absolute sensor will result. If there is a through-central aperture, a gage or differential sensor will result.

BRIEF DESCRIPTION OF THE FIGURES

[0016]FIG. 1 illustrates a cross section of a silicon and sapphire structure according to the present invention.

[0017]FIG. 2 illustrates a cross section of a structure according to FIG. 1 having an additional sapphire wafer bonded according to the present invention.

[0018]FIG. 3 illustrates a cross section of a structure according to FIG. 2 after thinning according to the present invention.

[0019]FIG. 4A illustrates an isometric view of a silicon wafer utilized according to the present invention.

[0020]FIG. 4B illustrates a cross section of the silicon wafer of FIG. 4A.

[0021]FIG. 5 illustrates a cross section of a silicon-on-sapphire structure according to the invention.

[0022]FIG. 6 illustrates a perspective view of a seal being applied to the structure of FIG. 5.

[0023]FIG. 7 illustrates an enlarged cross section of a structure formed according to method of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] Referring now to the many figures, wherein like references refer to like elements of the invention, FIG. 1 illustrates a commercially available slice of sapphire 10 having a thin silicon layer 20 grown on one surface 13, for example by sputtering.

[0025]FIG. 2 illustrates a second sapphire wafer 30 including a series of apertures 40 each having a diameter D which is preferably about 0.150 inches in diameter, affixed to surface 13 of the first wafer by means of E.S. bonding, fusion bonding or any other suitable means as is understood by those possessing ordinary skill in the pertinent art. An example of E.S. bonding can be seen in commonly assigned U.S. Pat. No. 3,951,707, entitled Method for Fabricating Glass-backed Transducers and Glass-backed Structures, the disclosure of which is incorporated by reference herein, while a suitable example of fusion bonding is illustrated in commonly assigned U.S. Pat. No. 5,286,671, entitled Fusion Bonding Technique for Use in Fabricating Semiconductor Devices, the disclosure of which is also incorporated by reference herein.

[0026] The apertures 40 can be formed prior to bonding sapphire wafer 30 to sapphire wafer 10 using any suitable means known to those skilled in the art.

[0027] Referring now to FIG. 3, therein is illustrated a next step according to the present invention, wherein the surface 17 (opposing surface 13) of the sapphire wafer 10 is then lapped and polished until the first sapphire wafer 10 is reduced to a desired thickness, preferably approximately 0.005 inches. The second wafer 30, which was previously secured to the first wafer 10, serves to strengthen the first wafer 10 during this process.

[0028] Next, a silicon layer 50 is grown, for example sputtered, on the now polished surface 17 of the first wafer 10. This silicon layer 50 is then preferably oxidized using any well known, conventional technique.

[0029] Referring now to FIGS. 4A and 4B, a silicon wafer 60 containing a series of sensor networks 70 is formed using any suitable process. The silicon wafer 60 includes p+ areas 80 which include sensor network 70 and a group of contact areas 90 extending from the sensor network 70. Outside of the contact areas 90, another p+ area 100 separate from the contact areas 90 but surrounding them, is also formed. The silicon wafer 60 is preferably fusion-bonded to the oxidized surface 17 of the first wafer 10, using the techniques described in the previously incorporated, commonly assigned U.S. Pat. No. 5,286,671, and the non p+ areas are removed using any suitable method, for example a conductivity selective etch, resulting in a structure such as that illustrated in FIG. 5. The remaining structure can be seen to include the p+ portions 80 of the silicon wafer 60 fusion bonded to the oxidized surface 50 of the first sapphire wafer 10, for example.

[0030] Next, appropriate areas 110 in the p+ contact regions 90 are preferably metalized using a high temperature metal system such as platinum silicide, titanium, or platinum.

[0031] Referring now to FIG. 6, a fourth wafer 120 made of any suitable, non-conductive material, such as glass for example, is prepared such that there are a series of apertures 130 corresponding to the various metalized contact areas 110. Additionally, there is preferably provided a slight depression 150 in the glass wafer 120 corresponding to the area of the sensor network 70 to allow the diaphragm to deflect without touching the glass wafer 120.

[0032] Referring now also to FIG. 7, the glass wafer 120 is preferably sealed using an ES Bond to the p+ contact areas 90, and the apertures 130 over the metalized areas 110 are filled with a glass metal frit 140 to make electrical contacts to metalized areas 110 of the p+ regions 80. If the seal of the glass wafer 120 to the p+ contact area 90 is not through a central aperture in the glass wafer 120 over the deflecting portion of the first wafer 10, an absolute sensor will result. If there is a through-central aperture, a gage or differential sensor will result.

[0033] There are a number of unanticipated advantages to the structure above. The method makes possible the construction of relatively small silicon-on-sapphire transducers with greater sensitivity and higher frequency response at a lower cost than conventional methods. The method makes possible the construction of either gauge or absolute transducers without the need for additional hermetic seals with headers, etc. as is understood by those possessing ordinary skill in the pertinent art. The method eliminates the need for ball-bond contacts to the silicon-on-sapphire surface resulting in greater reliability. The method makes possible much higher temperature operation by using a metal-glass frit as the contact means to the p+ region. The method does not require epitoxial growth of silicon-on-sapphire making it cheaper. And, the use of fusion bonding enables a much more degenerate sensing network to be formed.

[0034] Having described the preferred embodiment of this invention, it is evident that other embodiments incorporating these concepts may be used. Accordingly, although the invention has been described and pictured in a preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form has been made only by way of example and that numerous changes in the detail of construction, in combination, and arrangement of parts, may be made without departing from the spirit and scope of the invention as here and after claimed. It is intended that the patent shall cover by suitable expression in the appended claims, whatever features of patentable novelty exist in the invention disclosed.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
EP1444543A1 *Oct 18, 2002Aug 11, 2004Input/Output, Inc.Digital optical switch apparatus and process for manufacturing same
EP1890181A1 *Oct 18, 2002Feb 20, 2008Input/Output, Inc.Digital optical switch apparatus and process for manufacturing same
Classifications
U.S. Classification438/455
International ClassificationB81C1/00, G01L9/00
Cooperative ClassificationY10S148/012, Y10S438/967, G01L9/0042, B81C2201/019, B81C1/00357, G01L9/0055
European ClassificationB81C1/00D2, G01L9/00D2B4, G01L9/00D1
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