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Publication numberUS20010031534 A1
Publication typeApplication
Application numberUS 09/879,200
Publication dateOct 18, 2001
Filing dateJun 13, 2001
Priority dateJul 29, 1996
Also published asUS5877532, US6261910, US6362060
Publication number09879200, 879200, US 2001/0031534 A1, US 2001/031534 A1, US 20010031534 A1, US 20010031534A1, US 2001031534 A1, US 2001031534A1, US-A1-20010031534, US-A1-2001031534, US2001/0031534A1, US2001/031534A1, US20010031534 A1, US20010031534A1, US2001031534 A1, US2001031534A1
InventorsJae-Gyung Ahn, Jeong-Hwan Son
Original AssigneeJae-Gyung Ahn, Jeong-Hwan Son
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and method of manufacturing the same
US 20010031534 A1
Abstract
A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.
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Claims(20)
What is claimed is:
1. A method of manufacturing a semiconductor device, comprising the steps of:
forming a trench in a top surface of a semiconductor substrate, wherein said trench comprises at least one vertical wall;
implanting ions into said top surface of said semiconductor substrate and into a bottom surface of said trench;
forming an oxide film on said top surface of said semiconductor substrate, on said at least one vertical wall and on said bottom surface of said trench;
forming an oxide sidewall in said trench in contact with said oxide film on said at least one vertical wall and partially covering said bottom surface of said trench;
forming a gate in said trench in contact with said oxide sidewall and partially covering said bottom surface of said trench;
forming a first doped region in said top surface of said semiconductor substrate;
forming a second doped region in said bottom surface of said trench;
forming a recess by removing at least said oxide film on said at least one vertical wall and by removing at least said oxide sidewall; and
forming a third doped region in the bottom of said recess.
2. The method of
claim 1
, wherein the step of forming said gate comprises:
depositing an impurity-doped polycrystalline silicon material onto said oxide film on said top surface of said semiconductor substrate, onto said oxide sidewall, and onto said bottom surface of said trench; and
selectively removing portions of said impurity-doped polycrystalline silicon material such that said gate resides within said trench in contact with said oxide sidewall and partially covers said bottom surface of said trench.
3. The method of
claim 2
, wherein step of selectively removing said impurity-doped polycrystalline silicon material comprises a RIE (reactive ion etching) method.
4. The method of
claim 1
, wherein the step of forming a gate comprises forming the gate such that a top surface of said gate is at approximately the same height as the top surface of said semiconductor substrate.
5. The method of
claim 1
, wherein the step of forming said first doped region comprises forming said first doped region to approximately the depth of said bottom surface of said trench.
6. The method of
claim 1
, wherein the step of forming said third doped region comprises forming said third doped region between said first doped region and said gate.
7. The method of
claim 1
, wherein a channel region is formed between said first doped region and said second doped region, and said channel region is longer than a width of said gate.
8. A method of manufacturing a semiconductor device, comprising the steps of:
forming a trench in a top surface of a semiconductor substrate with at least one sidewall;
forming a gate oxide film over the semiconductor substrate so that the gate oxide film covers at least a portion of a bottom surface of the trench and covers the at least one sidewall of the trench;
forming a gate on the gate oxide film on the bottom of the trench such that a first side of the gate is exposed and a second side of the gate contacts the gate oxide film covering the at least one sidewall of the trench and such that a top surface of the gate is at approximately the same height as the top surface of the semiconductor substrate;
forming a first doped region having a first dopant concentration in the top surface of the substrate;
forming a second doped region having the first dopant concentration on the bottom surface of the trench adjacent the exposed side of the gate;
forming a recess between said gate and said at least one sidewall by removing at least said gate oxide film; and
forming a third doped region at the bottom of said recess having a second dopant concentration.
9. The method of
claim 8
, wherein the step of forming said gate comprises depositing an impurity-doped polycrystalline silicon material onto said top surface of said semiconductor substrate, and onto said bottom surface of said trench, and etching-back said impurity-doped polycrystalline silicon material.
10. The method of
claim 8
, wherein the step of forming a gate comprises forming the gate such that a top surface of said gate is at approximately the same height as the top surface of said semiconductor substrate.
11. The method of
claim 8
, wherein the step of forming said first doped region comprises forming said first doped region to approximately the depth of said bottom surface of said trench.
12. The method of
claim 8
, wherein the step of forming said third doped region comprises forming said third doped region between said first doped region and said gate.
13. The method of
claim 8
, wherein a channel region is formed between said first doped region and said second doped region, and said channel region is longer than a width of said gate.
14. A method of manufacturing a semiconductor device, comprising the steps of:
forming a trench in a top surface of a semiconductor substrate;
forming a gate oxide film on the surface of the semiconductor substrate so that the gate oxide film covers at least a portion of a bottom surface of the trench;
forming a spacer on the gate oxide film on the bottom of the trench such that a first side of the spacer is adjacent a side surface of the trench and such that a second side of the spacer is exposed;
forming a gate on the gate oxide film on the bottom of the trench such that a first side of the gate is adjacent the second side of said spacer and a second side of the gate is exposed;
forming a first doped region in the top surface of the substrate adjacent the first side of the spacer;
forming a second doped region on the bottom surface of the trench adjacent the second side of the gate;
removing the spacer to create a recess; and
forming a third doped region on the bottom surface of the recess between the gate and the first doped region.
15. The method of
claim 14
, wherein the step of forming said gate comprises:
depositing an impurity-doped polycrystalline silicon material onto said top surface of said semiconductor substrate, onto said vertical wall of said trench, and onto said bottom surface of said trench; and
etching-back said impurity-doped polycrystalline silicon material such that said gate is formed in the trench and adjacent the spacer.
16. The method of
claim 14
, wherein said etching-back comprises a RIE method.
17. The method of
claim 14
, wherein the step of forming a gate comprises forming the gate such that a top surface of said gate is at approximately the same height as the top surface of said semiconductor substrate.
18. The method of
claim 14
, wherein the step of forming said first doped region comprises forming said first doped region to approximately the depth of said bottom surface of said trench.
19. The method of
claim 14
, wherein the step of forming said third doped region comprises forming said third doped region between said first doped region and said gate.
20. The method of
claim 14
, wherein a channel region is formed between said first doped region and said second doped region, and said channel region is longer than a width of said gate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a Divisional of U.S. patent application Ser. No. 09/201,905, filed Nov. 30,1998, which is a Divisional of U.S. patent application Ser. No. 08/853,505, filed May 8, 1997 (now U.S. Pat. No. 5,877,532), both of which are hereby incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same in which one of the electrode region is formed in a recess or a trench of a substrate.

[0004] 2. Background of the Related Art

[0005] As the integration of semiconductor devices increases, the width of a gate becomes narrower, and thus, the length of a channel shortens. Therefore, the electric field in the vicinity of a drain is increased to accelerate carriers of the channel region in a depletion layer near the drain during the operation of a device, thereby causing a hot-carrier effect of injecting the carriers into a gate oxide film. The carriers injected into the gate oxide film create static charges in the interface between a semiconductor substrate and the gate oxide film, thereby varying a threshold voltage (VTH), or reducing a mutual inductance to deteriorate the device characteristics. Accordingly, in order to decrease the degradation of the device characteristics caused by the hot-carrier effect, a lightly doped drain (LDD) structure is used.

[0006]FIG. 1 is a cross-sectional view of a related art semiconductor device in which, on a predetermined part of a P-type semiconductor substrate 11, a device isolation region 13 for defining an active region of the device is formed by a local oxidation of silicon (LOCOS) method. A gate 17 is formed on a predetermined part of the active region of semiconductor substrate 11, with a gate insulating film 15 imposed therebetween. A capping oxide film 19 is formed on gate 17. A sidewall 23 is formed on the sides of both gate 17 and capping oxide film 19.

[0007] The semiconductor substrate 11 is doped on both sides of gate 17 with a low concentration of N-type impurity, thereby forming a low concentration region 21 for the LDD structure. Further, the semiconductor substrate is doped with a high concentration of N-type impurity so as to be partially overlapped with low concentration region 21, thereby forming source and drain regions 25 and 27, respectively. Source and drain regions 25 and 27 are formed using capping oxide film 19 and sidewall 23 as a mask. Low concentration region 21 is located between source and drain regions 25 and 27 and gate 17.

[0008] However, according to the aforementioned related art semiconductor device, low concentration region 21 for the LDD structure is formed in source region 25 as well as in drain region 27, so that the source resistance is increased thereby causing the current characteristics of the device to deteriorate. Further, if the bias of drain region 27 increases, a depletion region is increased, thereby causing a drain-induced barrier lowering (hereinafter, referred to as “DIBL”) phenomenon that reduces the potential barrier of the source. In addition, due to the limitations of a photolithographic methods, reduction of the gate width is difficult.

SUMMARY OF THE INVENTION

[0009] An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.

[0010] An object of the present invention is to obviate one or more of the problems of the related art.

[0011] Another object of the present invention is to reduce the source resistance.

[0012] Another object of the present invention is to suppress the occurrence of the DIBL phenomenon even if the channel length is short.

[0013] A further object of the present invention is to provide a narrow gate.

[0014] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device of the present invention comprises: a semiconductor substrate of a first conductivity type; a device isolation region formed on a predetermined part of the surface of the semiconductor substrate to define an active region of the device; a trench formed on a predetermined part of one side of the active region on the semiconductor substrate; a gate oxide film formed on predetermined parts of the side and the lower part of the trench; a gate formed such that the lower part and a first side thereof are in contact with the surface of the gate oxide film and the second side of the gate is exposed; a sidewall formed so as to be in contact with the second side of the gate; a low concentration region formed by doping an impurity of a second conductivity type opposite, to that of the semiconductor substrate, with a low concentration of dopant in the lower part of the sidewall; and source and drain regions formed by doping an impurity of the second conductivity type with a high concentration of dopant, using the gate and the sidewall as a mask.

[0015] In another aspect, the present invention provides a semiconductor device comprising: a semiconductor substrate of a first conductivity type; a device isolation region formed on a predetermined part of the surface of the semiconductor substrate to define an active region of the device; a trench formed on a predetermined part of one side of the active region on the semiconductor substrate; a gate oxide film formed on a predetermined part of the lower surface of the trench so as to be spaced apart from the side of the trench by a predetermined distance; a gate formed on the gate oxide film and having first and second sides; a low concentration region formed by doping an impurity of a second conductivity type, opposite to that of the semiconductor substrate, at a low concentration in the lower surface between the first side of the gate and the side of the trench; and source and drain regions formed by doping an impurity of the second conductivity type at a high concentration in a part of the semiconductor substrate in the direction of the first side of the gate not doped at a low concentration and a part of the semiconductor substrate in the direction of the second side of the gate.

[0016] In another aspect, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: forming a trench in a predetermined part of one side of a semiconductor substrate of a first conductivity type; forming a gate oxide film on the surface of the semiconductor substrate including the inner surface of the trench; depositing a polycrystalline silicon material on the upper part of the gate oxide film and etching back the polycrystalline silicon material to form a gate such that the first side thereof is in contact with the side of the trench and the second side of the gate is exposed; ion-implanting an impurity of a second conductivity type, opposite to that of the semiconductor substrate, using the gate as a mask to thereby form low concentration regions on both sides of the gate; forming a sidewall on the second side of the gate; and ion-implanting a high concentration of an impurity of the second conductivity type, using the gate and the sidewall as a mask, to thereby form source and drain regions in the semiconductor substrate in the direction of the first side of the gate and in the semiconductor substrate excluding the lower part of the sidewall in the direction of the second side of the gate.

[0017] In another aspect, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: forming a trench in a predetermined part of one side of a semiconductor substrate of a first conductivity type; forming a gate oxide film on the surface of the semiconductor substrate including the inner surface of the trench; forming a sidewall such that a first side thereof is in contact with a side or inner wall of the trench and the second side of the sidewall is exposed, with the gate oxide film imposed between the side of the trench and the first side of the sidewall; forming a gate such that the first side thereof is in contact with the second side of the sidewall and the second side of the gate is exposed; ion-implanting a high concentration of an impurity having a second conductivity type, opposite to that of the semiconductor substrate, using the sidewall and the gate as a mask, to thereby form source and drain regions, respectively, in the directions of the first side and the second side of the gate excluding the lower part of the sidewall; removing the sidewall; and ion-implanting an impurity of the second conductivity type using the gate as a mask, to thereby form a low concentration region in the direction of the first side of the gate where the sidewall is removed.

[0018] The present invention may be achieved in part or in whole by a semiconductor device, comprising a semiconductor substrate of a first conductivity type; a recess formed in a surface of the semiconductor substrate; a first region of a second conductivity formed in the recess; a second region of the second conductivity formed on the surface of the semiconductor substrate; a gate formed in the recess, between the first and second regions, and insulated from the semiconductor substrate, first region and second region; and a channel formed between the first and second regions and beneath the gate in the semiconductor substrate.

[0019] The present invention may also be achieved in whole or in part by a semiconductor device comprising: a semiconductor substrate of a first conductivity type; a trench formed in a surface of the semiconductor substrate, the trench having a side wall surface and a lower surface; an insulating film formed on the sidewall and a prescribed area of the lower surface; a gate formed on the insulating film; a first doped region of a second conductivity formed in the trench; a second doped region of the second conductivity formed on the surface of the semiconductor substrate and adjacent to the insulating film on the sidewall of the trench; and a third doped region formed on the lower surface of the trench and between the gate and the first region; and a channel formed between the second and third regions.

[0020] The present invention may be achieved in whole or in part by a semiconductor substrate of a first conductivity type; a trench formed in a surface of the semiconductor substrate; a first doped region of a second conductivity formed in the trench; a second doped region of the second conductivity formed on the surface of the semiconductor substrate; a third doped region of the second conductivity formed adjacent to the second doped region; an insulating film formed between the first and third doped regions; a gate formed on the insulating film; and a channel formed between the first and third regions in the semiconductor substrate and beneath the insulating film.

[0021] To achieve at least the above objects and advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing a semiconductor device, including the steps of forming a trench in a top surface of a semiconductor substrate, wherein the trench comprises at least one vertical wall, implanting ions into the top surface of the semiconductor substrate and into a bottom surface of said trench, forming an oxide film on the top surface of the semiconductor substrate, on the at least one vertical wall and on the bottom surface of the trench, forming an oxide sidewall in the trench in contact with the oxide film on the at least one vertical wall and partially covering the bottom surface of the trench, forming a gate in the trench in contact with the oxide sidewall and partially covering the bottom surface of the trench, forming a first doped region in the top surface of the semiconductor substrate, forming a second doped region in the bottom surface of the trench, forming a recess by removing at least the oxide film on the at least one vertical wall and by removing at least the oxide sidewall, and forming a third doped region in the bottom of the recess.

[0022] To further achieve at least the above objects and advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing a semiconductor device, including the steps of forming a trench in a top surface of a semiconductor substrate with at least one sidewall, forming a gate oxide film over the semiconductor substrate so that the gate oxide film covers at least a portion of a bottom surface of the trench and covers the at least one sidewall of the trench, forming a gate on the gate oxide film on the bottom of the trench such that a first side of the gate is exposed and a second side of the gate contacts the gate oxide film covering the at least one sidewall of the trench and such that a top surface of the gate is at approximately the same height as the top surface of the semiconductor substrate, forming a first doped region having the first dopant concentration in the top surface of the substrate, forming a second doped region having a first dopant concentration on the bottom surface of the trench adjacent the exposed side of the gate, forming a recess between the gate and the at least one sidewall by removing at least the gate oxide film, and forming a third doped region at the bottom of the recess having a second dopant concentration.

[0023] To further achieve at least the above objects and advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing a semiconductor device, including the steps of forming a trench in a top surface of a semiconductor substrate, forming a gate oxide film on the surface of the semiconductor substrate so that the gate oxide film covers at least a portion of a bottom surface of the trench, forming a spacer on the gate oxide film on the bottom of the trench such that a first side of the spacer is adjacent a side surface of the trench and such that a second side of the spacer is exposed, forming a gate on the gate oxide film on the bottom of the trench such that a first side of the gate is adjacent the second side of the spacer and a second side of the gate is exposed, forming a second doped region in the top surface of the substrate adjacent the first side of the spacer, forming a first doped region on the bottom surface of the trench adjacent the second side of the gate, removing the spacer to create a recess, and forming a third doped region on the bottom surface of the recess between the gate and the second doped region.

[0024] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

[0025] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

[0027] The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

[0028]FIG. 1 is a cross-sectional view of a related art semiconductor device;

[0029]FIG. 2 is a cross-sectional view of a semiconductor device, according to one embodiment of the present invention;

[0030]FIG. 3 is a cross-sectional view of a semiconductor device, according to another embodiment of the present invention;

[0031]FIGS. 4A to 4D are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2; and

[0032]FIGS. 5A to 5E are cross-sectional views for illustrating a method of manufacturing the semiconductor device shown in FIG. 3.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0033]FIG. 2 is a cross-sectional view of a semiconductor device, according to one embodiment of the present invention, in which a device isolation region 33 for defining an active region of the device is formed on a predetermined part of the surface of a P-type semiconductor substrate 31. By a dry etching process, such as reactive ion etching (hereinafter, referred to as “RIE”) or plasma etching, a trench or a recess 37 having a depth of about 500˜2000 Å is formed on a predetermined part of one side of the active region. This embodiment illustrates a trench, however, as can be appreciated, any type of recesses can be also used to achieve the present invention.

[0034] A gate 43 having a sidewall shape is formed on one side and a predetermined part of the lower surface or base of trench or recess 37, with a gate oxide film 41 imposed therebetween. Gate 43 is formed so that the first side thereof is in contact with gate oxide film 41, by depositing an impurity-doped polycrystalline silicon material on the surface of both substrate 31 and trench or recess 37 and then etching back impurity-doped polycrystalline silicon material by a RIE method. Accordingly, gate 43 can be formed so as to have a narrower width than that could be formed by a photolithographic method. The width is about 300˜2000 Å. Then, on the second exposed side of gate 43, a sidewall 47 consisting of an insulating material, such as a silicon oxide, is formed to a width of about 300˜1000 Å.

[0035] Using gate 43 as a mask, a low concentration region 45 doped with a low concentration by an N-type impurity, such as arsenic (As) or phosphorus (P) of a conductivity type opposite to that of semiconductor substrate 31, is formed in the lower surface of trench or recess 37 between the side of trench or recess 37 and the first side of gate 43. Low concentration region 45 serve to form the LDD structure and formed so as to be partially overlapped by gate 43.

[0036] Then, in predetermined portions of a part of the active region where trench 37 is not formed, and in a part where trench or recess 37 is formed, source region 49 and drain region 51, each doped with a high concentration of an N-type impurity, are formed, respectively. Source and drain regions 49 and 51 are formed using gate 43 and sidewall 47 as a mask. Drain region 51, formed in the lower surface of trench or recess 37 in the direction of the first side of gate 43, is not overlapped by gate 43, and is partially overlapped by low concentration region 45.

[0037] The region between source region 49 (formed in the part of the active region where trench or recess 37 is not formed, and which is located at predetermined part in the direction of the second side of gate 43) and low concentration region 45 forms a channel region. Since source region 49 is shallower than the lower surface of trench or recess 37, even if the width of gate 43 is narrow, the channel makes a right angle around a corner of gate 43 and the channel has a longer width than the width of gate 43. Thus, even if the bias of drain region 51 increases, the increase in a depletion region is prevented, thereby decreasing the occurrence of the DIBL phenomenon, in turn reducing the potential barrier of source region 49.

[0038]FIG. 3 is a cross-sectional view of a semiconductor device, according to another embodiment of the present invention, in which a device isolation region 33 for defining an active region of a device is formed on a predetermined part of the surface of a P-type semiconductor substrate 31. By a dry etching process such as RIE or plasma etching, a trench or recess 37 having a depth of about 500˜2000 Å is formed on a predetermined part of one side of the active region.

[0039] A gate 43 having first side and second sides is formed on a predetermined part of the lower surface of trench or recess 37, with a gate oxide film 41 imposed between the lower surface of the trench or recess and gate 43. Gate 43 is formed by depositing an impurity-doped polycrystalline silicon material on the lower surface of the trench or recess 37 including a sidewall (not shown) formed on the side of trench or recess 37, and then etching back the impurity-doped polycrystalline silicon material by a RIE method, and removing the sidewall. Accordingly, gate 43 can be formed so as to have a narrower width of about 300˜2000 Å than that could formed by a photolithographic method.

[0040] Using gate 43 as a mask, a low concentration region 45, doped with a low concentration of an N-type impurity, such As or P of a conductivity type opposite that of semiconductor substrate 31, is formed in the lower surface of trench or recess 37 between the side of trench or recess 37 and the first side of gate 43. Low concentration region 45 serves to form the LDD structure and is formed so as to be partially overlapped with gate 43.

[0041] Then, in the lower surface of trench 37 where low concentration region 45 is not formed, i.e., in the direction of the second side of gate 43, source region 49 is formed. While in the part where no trench or recess 37 is formed, i.e., in the direction of the first side of gate 43, drain region 51 is formed. Both source and drain regions 49 and 51 are doped with a high concentration of an N-type impurity. Drain region 51, in the direction of the first side of gate 43, is formed to the lower surface of trench or recess 37 and is partially overlapped with low concentration region 45. Thus, drain region 51 is electrically connected therewith. The region between source region 49, in the direction of the second side of gate 43, and low concentration region 45 forms a channel region.

[0042] According to the embodiment illustrated in FIG. 3, low concentration region 45 is not formed between the channel region and source region 49, but between the channel region and drain region 51. Thus, the source resistance of the device can be decreased.

[0043]FIGS. 4A to 4D are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2. Referring to FIG. 4A, a device isolation region 33 is formed to a thickness of about 3000˜5000 Å on a predetermined part of the surface of a P-type semiconductor substrate 31, thereby defining an active region of the device. Through a photolithographic method, including a dry etching process such as RIE or plasma etching, a trench or recess 37 having a depth of about 500˜2000 Å is formed in a predetermined part of one side of the active region of semiconductor substrate 31. As can be appreciated, semiconductor substrate 31 may be of the P-type or the N-type conductivity A P-type semiconductor substrate is chosen to explain the present invention. In the above case, trench or recess 37 is formed after forming device isolation region 33. However, as can be appreciated, device isolation region 33 may instead be formed after trench or recess 37 is formed.

[0044] Referring to FIG. 4B, in the surface of semiconductor substrate 31, including the inner surface of trench or recess 37, a P-type impurity of the same conductivity type as that of semiconductor substrate 31, e.g., boron (B) or BF2, is ion-implanted. This latter step is performed in order to control the threshold voltage and to suppress the punchthrough. The ion implantation step is performed at a predetermined tilt angle such that the ion is implanted in the side or wall of trench or recess 37, as well as in the perpendicular direction with respect to semiconductor substrate 31. Then, the surface of semiconductor substrate 31, including the inner surfaces of trench or recess 37, is thermally oxidized to form a gate oxide film 41 having a thickness of about 30˜100 Å.

[0045] Referring to FIG. 4C, through a CVD method, a polycrystalline silicon material is deposited on the upper part of device isolation region 33 and gate oxide film 41. Then, the polycrystalline silicon material is etched back by a RIE method to form a gate 43 having a sidewall shape and having a width of about 300˜2000 Å, so that the first side of the gate is in contact with the side of trench or recess 37 and the second side of the gate is exposed. At this time, gate oxide film 41, which is not in contact with gate 43, is also removed. Since gate 43 is formed by an etching-back method, it can be formed more narrowly than would be possible with a common photolithographic method.

[0046] Then, using gate 43 as a mask, an N-type impurity having a conductivity type opposite to that of semiconductor substrate 31, e.g., arsenic (As) or phosphorus (P), is ion-implanted at a concentration of about 1.0Χ1013˜1.0Χ1015/cm2, thereby forming low concentration regions 45 in semiconductor substrate 31 on both sides of gate 43. Low concentration region 45 serves to form the LDD structure. The impurity ion is implanted perpendicularly to semiconductor substrate 31, and formed so as to be partially overlapped with gate 43.

[0047] Referring to FIG. 4D, through a CVD method, an insulating material such as a silicon oxide is thickly deposited over the entire surface of the resultant structure and etched back by a RIE method, thereby forming a sidewall 47 having a width of about 300˜1000 Å that is in contact with the exposed second side of gate 43. Then, using gate 43 and sidewall 47 as a mask, an N-type impurity of the conductivity type opposite to that of semiconductor substrate 31, e.g., arsenic (As), is ion-implanted at a concentration of about 1.0Χ1014˜5.0Χ1015/cm2, thereby forming source and drain regions 49 and 51 in semiconductor substrate 31. Since the impurity ion for forming source and drain regions 49 and 51 are implanted perpendicularly to semiconductor substrate 31, low concentration region 45 making the LDD structure is completely overlapped by source region 49 in the direction of the first side of gate 43, and overlapped by drain region 51 in the direction of the second side of gate 43.

[0048] Accordingly, low concentration region 45 does not exist between channel region and source region 49 and exists only between channel region and drain region 51, thereby decreasing the source resistance. The channel region is defined by the formation of source and drain regions 49 and 51. The channel region is formed also on the side of trench or recess 37 along the junction depth of source region 49. Accordingly, source region 49 is formed so as to be higher than the lower surface of trench or recess 37, and the channel region makes a right angle trench or recess 37. Thus, the channel has a width longer than gate 43, and the increase in the depletion region is prevented even if the bias of drain region 51 increases. Therefore, the occurrence of the DIBL phenomenon, which tends to reduce the potential barrier of source region 49, can be decreased.

[0049]FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing the semiconductor device of FIG. 3. Referring to FIG. 5A, a device isolation region 33 is formed to a thickness of about 3000˜5000 Å on a predetermined part of the surface of a P-type semiconductor substrate 31, thereby defining an active region of the device. Through a photolithographic method, including a dry etching process such as RIE or plasma etching, a trench or recess 37 having a depth of about 500˜2000 Å is formed in a predetermined part of one side of the active region of semiconductor substrate 31. Semiconductor substrate 31 may be of the P-type or the N-type conductivity. In the above case, trench or recess 37 is formed after forming device isolation region 33. However, as can be appreciated, device isolation region 33 may be formed after trench or recess 37 is formed.

[0050] Referring to FIG. 5B, in the surface of semiconductor substrate 31, including the inner surface of trench or recess 37, a P-type impurity of the same conductivity type as that of semiconductor substrate 31, e.g., boron (B) or BF2, is ion-implanted in a perpendicular direction. This latter step is performed in order to control the threshold voltage and to suppress punchthrough. Then, the surface of semiconductor substrate 31, including the inner surface of trench or recess 37, is thermally oxidized to form a gate oxide film 41 having a thickness of about 30˜100 Å.

[0051] Referring to FIG. 5C, through a CVD method, an insulating material such as a silicon oxide is thickly deposited on the upper part of device isolation region 33 and gate oxide film 41, and the insulating material is etched back by a RIE method, thereby forming a sidewall 47 having a width of about 300˜1000 Å on the side of trench or recess 37. Sidewall 47 is formed such that the first side thereof is in contact with gate oxide film 41 and therefore not exposed, whereas the second side of sidewall 47 is exposed.

[0052] Referring to FIG. 5D, an impurity-doped polycrystalline silicon material is deposited on the entire surface of the resultant structure and etched back by a RIE method, thereby forming a gate 43 having a width of about 300˜2000 Å such that a first side thereof is in contact with the second side of sidewall 47 and the second side of the gate is exposed. Since gate 43 is formed by an etching-back method, it can be formed shorter or narrower than would be possible with a common photolithographic method.

[0053] Then, using gate 43 and sidewall 47 as a mask, an N-type impurity of a conductivity type opposite to that of semiconductor substrate 31, e.g., arsenic (As), is ion-implanted at a concentration of about 1.0Χ1014˜5.0Χ1015/cm2, thereby forming source and drain regions 49 and 51, respectively, in semiconductor substrate 31. Drain region 51, which is formed in a part of semiconductor substrate 31 where trench or recess 37 is not formed, i.e., in the direction of the first side of sidewall 47, should be formed to the depth of the lower surface of trench or recess 37.

[0054] Referring to FIG. 5E, sidewall 47 and gate oxide film 41 are removed by a wet etching process. Then, using gate 43 as a mask, an N-type impurity of the conductivity type opposite to that of semiconductor substrate 31, e.g., arsenic (As) or phosphorus (P), is ion-implanted at a concentration of about 1.0Χ1014˜5.0Χ1015/cm2, thereby forming a low concentration region 45 between the first side of gate 43 and drain region 51. Low concentration region 45 serves to form the LDD structure, and is not formed between gate 43 and source region 49. Rather, low concentration region 45 is formed only between gate 43 and drain region 51 so as to form a junction with drain region 51, thereby decreasing the source resistance of the semiconductor device.

[0055] In the above embodiments, a trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by the respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.

[0056] The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

[0057] The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7301193Jan 22, 2004Nov 27, 2007Spansion LlcStructure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
US7511337Aug 10, 2006Mar 31, 2009Hynix Semiconductor Inc.Recess gate type transistor
US7678653Feb 16, 2009Mar 16, 2010Hynix Semiconductor Inc.Method of fabricating a recess gate type transistor
US7687852Feb 16, 2009Mar 30, 2010Hynix Semiconductor Inc.Recess gate type transistor
WO2005074018A1 *Dec 17, 2004Aug 11, 2005Kuo-Tung ChangStructure and method for low vss resisitance and reduced dibl in a floating gate memory cell
Classifications
U.S. Classification438/268, 438/299, 257/E21.205, 257/E21.429, 257/E29.135, 257/E29.267, 257/E29.04, 257/E21.427, 257/E21.431
International ClassificationH01L29/78, H01L29/08, H01L29/423, H01L21/336, H01L21/28
Cooperative ClassificationH01L29/66659, H01L29/42376, H01L21/28114, H01L29/66636, H01L29/7834, H01L29/0847, H01L29/66621, H01L21/2815
European ClassificationH01L29/66M6T6F11D2, H01L29/66M6T6F11H, H01L29/66M6T6F11E, H01L21/28E2B20, H01L29/78F2, H01L29/423D2B7B, H01L21/28E2B30S
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