CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/186,445, entitled “Bootstrap direct full-band frequency synthesizer”, having attorney docket No. TI-30678PS, and filed on Mar. 2, 2000.
This invention relates in general to the field of radio communications and more specifically to a frequency synthesizer.
A large reduction of the transistor features in recently developed deep-submicron complementary metal-oxide semiconductor (CMOS) processes shifts the design paradigm towards more digitally intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of the number of devices used, but rather in terms of the occupied silicon area used. A typical digital cellular telephone on the market today contains over a million transistors. Analog and radio frequency (RF) circuits, on the other hand, do not scale down very well. A low-noise charge pump, or a low-distortion image-rejection modulator, both good examples of classical RF transceiver components, occupy roughly about the same amount of semiconductor surface area as is used for tens of thousands of digital gates. This is equivalent to a lot of digital signal processing (DSP) power. Consequently, there are numerous incentives to look for digital solutions for both analog and RF circuits. Unfortunately, very little research work on this topic has been disclosed so far.
There are a few frequency synthesis techniques found in RF communication products, they include direct-digital, indirect or phase-locked loop (PLL), and hybrids that are a combination of the direct and indirect approaches. Each of these methods of frequency synthesis has advantages and disadvantages; hence each application requires selection based upon the most acceptable combination of compromises to the designer.
Indirect synthesis, also called phase-locked loop (PLL), compares the output of a voltage-controlled oscillator (VCO) with a phase of a reference signal, fREF, as shown in the prior art PLL of FIG. 1. As the output of the PLL drifts, detected errors produce correction commands to the VCO, which responds accordingly. Error detection occurs in the phase frequency detector (PFD), which adds phase noise close to the carrier, though a PLL can outperform direct synthesis techniques at larger offsets. Fine frequency steps degrade phase noise, and fast switching is difficult to achieve with a PLL design even with the use of aggressive VCO pre-tuning techniques.
In general, an indirect synthesizer uses a PLL loop and a programmable fractional-N divider that multiplies the stable frequency, fREF. In the loop, a loop filter (LF) is present so as to suppress spurs produced in the PFD so that they do not cause unacceptable frequency modulation in the VCO. However, the LF causes the degradation in transients, which limits the switching time. Therefore, the requirements for both the frequency switching time and the suppression of spurs are in conflict. Classical PLL-based frequency synthesizers are only suitable for narrow-band frequency modulation schemes, in which the modulating data rate is well within the PLL loop bandwidth.
The second major synthesis technique currently used today is direct-digital frequency synthesis (DDFS) which uses logic and memory components to digitally construct the desired output signal, and a data conversion device to convert it from the digital to the analog domain, as shown in FIG. 2. The DDFS method of constructing a signal is almost all digital, and the precise amplitude, frequency, and phase are known and controlled at all times. For these reasons, the switching speed is considered extremely high, but the power consumption could be excessive at high clock frequencies. The DDFS method is not entirely digital in the true sense of the word since it requires a digital-to-analog converter (DAC) and a low-pass filter to attenuate the spurious frequencies caused by the digital switching. In addition, a very stable clock of at least three times the output frequency is required, and the total power consumption is not acceptable for designs used in mobile communications.
Because it is very costly to implement a DDFS at frequencies of interest for wireless communications (e.g., multi-GHz range), this technique is currently being used mainly for military applications. Due to its waveform reconstruction nature, the DDFS technique is best suited for implementing wideband transmit modulation, as well as fast channel-hopping schemes. In FIG. 3, there is shown the prior art front-end of the phase accumulator shown in FIG. 2. The front-end uses an arithmetic adder that combines the frequency control word (FCW) components of the selected channel and the frequency-modulating data.
In certain design applications, it is necessary to combine the two (direct and indirect) major synthesis techniques such that the best features from each method are emphasized. For example, the wideband modulation and fast channel-hopping capability of the DDFS method, is combined with a frequency multiplication property of a PLL loop that up-converts it to the RF band. This is shown in FIG. 4 as a hybrid synthesizer 400 including a DDFS 402 and a PLL 404. The DDFS 402 generates a stable frequency reference to the main PLL loop 404. Since the DDFS 402 operates at a low frequency, its major limitation of high power is not a concern.
BRIEF DESCRIPTION OF THE DRAWINGS
Deep-submicron CMOS processes present new integration opportunities to the designer, but make it difficult to implement traditional analog circuits. For example, frequency control input of a low-voltage deep-submicron CMOS oscillator is an extremely challenging task due to its highly nonlinear frequency versus voltage characteristics and low voltage headroom making it susceptible to the power supply and substrate noise. In such a low supply voltage case, the dynamic range of the signal and thus the signal-to-noise (S/N) ratio will degrade significantly. In this case, a circuit designer has to look for alternative solutions, such as utilizing a voltage doubler. Furthermore, the advanced CMOS processes typically use low resistance P-substrate that is an effective means in combating latch-up problems, but exacerbates substrate noise coupling into the analog circuits. This problem only gets worse with scaling down of the supply voltage. In order to address the various deep-submicron RF integration issues, some new and radical system and architectural changes have to be discovered.
The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention, may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:
FIG. 1 shows a block diagram of a prior art PLL.
FIG. 2 shows a block diagram of a prior art DDFS.
FIG. 3 shows a prior art front-end of the phase accumulator of the DDFS of FIG. 2.
FIG. 4 shows a block diagram of a prior art hybrid synthesizer.
FIG. 5 shows a block diagram of a synthesizer in accordance with the invention.
FIG. 6 shows a DDFS structure using a counter for FCW correction in accordance with the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 7 shows a DDFS structure as in FIG. 6 using a sigma-delta dither block in accordance with another aspect of the invention.
While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figure.
A frequency synthesizer in accordance with the invention is shown in FIG. 5. The synthesizer 500 maximizes digital hardware content in order to make it very amenable to deep sub-micron CMOS processes. The example shown in FIG. 5, is for a 2.4 GHz transceiver for use in a Bluetooth application. The 2.4 GHz VCO can be implemented as a digital-controlled oscillator (DCO) 508. Similarly, the loop filter (LF) 506 can be implemented in a digital manner.
The frequency synthesis is accomplished through the combination of a scaled-down DDFS 502 and a phase-lock-loop (PLL) 526 which includes the PFD 504, loop filter 506, DCO 508, first divider (divide by N1) 510 and second divider (divide by N2) 512. The first divider 510 is optional given that in some applications a divide-by-1 in that part of the loop can be used. In a typical example, the first divider 510 is set to divide by four and second divider 512 is set to divide by sixty-four, giving an fCLK signal 514 frequency of 600 MHz and a fupdate signal 528 frequency of 9.375 MHz.
The wideband modulation and fast channel-hopping capability of the DDFS method, that operates at a lower frequency in accordance with the invention, is combined with the frequency multiplication property of a PLL loop that upconverts the DDFS output (fDDFS) 518 to the RF band, in this case 2.4 GHz. In this way, the best features from each basic synthesis method are emphasized. The composite PLL loop is an all-digital PLL (ADPLL) architecture which generates the 2.4 GHz output signal (fRF) 516.
The underlying frequency stability of the system is derived from the reference crystal oscillator signal (fREF) 520, such as a 13 MHz signal as used in a GSM system.
The down-divided (by N1) DCO frequency signal (fCLK) 514 is used as a digital system clock mainly for the DDFS block 502, which can generate frequency roughly up to one-third of its clock frequency. As stated previously, the DDFS cannot generate the RF frequency directly for practical reasons.
The fCLK signal 514 is further divided by a second divider 512 by N2 to establish the update frequency signal (fupdate) 528. The output of the DDFS (fDDFS) 518 and the fupdate signal 528 are compared by the PFD 504. Its output is then filtered by the LF 506 before the signal is used as a tuning signal 522 (tuning word or tuning voltage) of the oscillator (DCO) 508. The phase/frequency detection process is performed between the DDFS output and the divide-by (N1ĚN2) clock. The output of the PFD 504 can be filtered by the loop filter (LF) 506 before being used as the tuning word of the DCO 508.
The system clock deviation from the ideal timing instances, as determined by the frequency reference fREF clock signal 520 establishes the long-term frequency stability, and will appropriately adjust the phase accumulator content. This principle of “bootstrapping” ensures that the system is synchronous and every internal clock is derived from the same source. The fREF input to the DDFS 502 is not used as an actual sampling clock but is used to update the frequency control word (FCW) of the DDFS 502.
As the oscillator frequency drifts, the FCW 524 provided to the DDFS input gets corrected such that the “reference” input (fDDFS 518) provided to the second stage PLL causes the oscillator to pull back.
Although the LF 506 and the first divider 510 are optional, they are likely to be used in most implementations. As shown in FIG. 5, the DDFS 502 which is clocked by the fCLK signal 514 is commanded by the FCW 524 to generate the lower-frequency output that, after N1ĚN2 frequency multiplication by the PLL loop, corresponds to the desired output frequency fRF 516 of the channel and instantaneous modulating data.
An example of such FCW correction in accordance with the invention is shown in FIG. 6, where the oscillator frequency drift is determined by counting the high frequency fCLK edges using counter 602 in a single or multiple fREF clock cycles. The thus obtained correction then gets added to the FCW 524 using adder 604. The adjusted FCW or FCW_ADJ 606 is then sent to the phase accumulator 608.
The channel selection and transmitter modulation can be further refined through a scaled-down DDFS with sigma-delta (ΣΔ) modulation of the phase position pulses that shape the frequency spectrum of the integer quantization. The circuit is similar to that shown in FIG. 6 with the ΣΔ modulation being accomplished using a sigma-delta dither block 702. The high-jitter content of the phase accumulator output (phase position pulses) are dithered with high-frequency noise shaping through the sigma-delta dither block 702 such that the quantization energy is easily filtered out by the PLL loop 526. Only the phase accumulator part of a conventional DDFS is used as shown in FIGS. 6 and 7, with the inclusion of the counter 602 and other adjustment circuit provided in accordance with the present invention. The output signal (fDDFS) 518 of the DDFS 502 is used as the “reference” frequency to the second stage PLL loop 526 as mentioned previously.
The present invention given its digitally intensive synthesizer implementation provides for improvements in power consumption, decrease in silicon area for the design, as also provides for lower parameter variability than with conventional analog circuits.
While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.