US20010034937A1 - Conductor interconnect with dendrites through film and method for producing same - Google Patents
Conductor interconnect with dendrites through film and method for producing same Download PDFInfo
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- US20010034937A1 US20010034937A1 US09/859,690 US85969001A US2001034937A1 US 20010034937 A1 US20010034937 A1 US 20010034937A1 US 85969001 A US85969001 A US 85969001A US 2001034937 A1 US2001034937 A1 US 2001034937A1
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- dendrites
- surface metal
- substrate
- electronic circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10666—Plated through-hole for surface mounting on PCB
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49194—Assembling elongated conductors, e.g., splicing, etc.
Definitions
- the present invention relates to electronic circuit packages with dendrites connecting two conductive surfaces through a film and method for producing same.
- the dendrites electrically connect the two conductive surfaces and avoid the need for drilling or punching holes for vias or through-holes.
- Electronic circuits contain many (sometimes millions) of components such as resistors, capacitors, inductors, diodes, electro-mechanical switches, and transistors.
- High density packaging of electronic components is particularly important to allow fast access to large amounts of data in computers.
- High density electronic circuit packages also are important in high frequency devices and communications devices.
- the components are connected to form circuits and circuits are connected to form functioning devices.
- the connections perform power and signal distribution.
- some layers of the package serve as power planes and other layers serve as signal planes, depending on the operational requirements of the device.
- the devices require mechanical support and structural protection.
- the circuits themselves require electrical energy to function.
- the functioning devices produce heat, or thermal energy which must be dissipated so that the devices do not stop functioning.
- the heat produced by the power-consuming components can be such that performance and reliability of the devices is adversely impacted.
- the adverse impact arises from electrical problems such as increased resistivity and mechanical problems such as thermal stress caused by increased heat.
- Electronic circuit packages such as chips, modules, circuit cards, circuit boards, and combinations of these, thus must meet a number of requirements for optimum performance.
- the package must be structurally sturdy enough to support and protect the components and the wiring.
- the package must be capable of dissipating heat and must have a coefficient of thermal expansion that is compatible with that of the components.
- the package should be inexpensive to produce and easy to manufacture.
- High density packages necessarily involve increased wiring density and thinner dielectric coatings between layers in a multi-layer electronic circuit package.
- the layers in a multi-layer package typically are electrically connected by vias and through-holes.
- the term “via” is used for a conductive pathway between adjacent layers in a multi-layer electronic circuit package.
- the term “through-hole” is used for a conductive pathway that extends to a non-adjacent layer.
- the through-holes are increasingly narrow in diameter and the through-holes in each layer must be aligned precisely.
- This invention provides an alternative means of interconnection-namely electrical interconnection using dendrites. Dendrite interconnection avoids the need to drill or punch holes for vias or through-holes.
- An object of this invention is to provide a means for connecting two conductors along the vertical or z-axis without using vias or through-holes, but still resulting in tight tolerances and high yield. Dendrite interconnections accomplish this purpose.
- a further object of this invention is to provide an electronic circuit package that provides electrical connection in the z-axis using dendrites, thereby eliminating the need for drilling or punching through-holes or vias in the manufacturing process of the electronic circuit package.
- a third object of this invention is to provide a method of fabrication of electronic circuit packages with dendrites forming electrical connections between a first conductive layer and a second conductive layer.
- a method for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy dielectric material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer.
- an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention.
- An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
- the dendrites provide electrical connection between two conductive layers of the electronic circuit package.
- the dendrites provide electrical connection in the z-axis using dendrites, thereby eliminating the need for photodefining, laser ablating, drilling or punching through-holes or vias in the manufacturing process of the electronic circuit package.
- FIG. 1 is a depiction of a single layer of a multi-layer electronic circuit package using dendrites, rather than through-holes or vias, to electrically connect two conductive surfaces, in accordance with the present invention.
- FIG. 2 is a depiction of two layers of a multi-layer electronic circuit package using dendrites to provide an electrical connection where a “through via” would exist in more traditional manufacturing.
- FIG. 3 is a flow chart of the method of the present invention.
- the present invention is of an electronic circuit package using dendrites to provide connection between two conductive surfaces, thereby avoiding the need to photodefine, laser ablate, drill or punch through-holes or vias.
- the invention can best be understood by reference to the drawings.
- FIG. 1 illustrates a sample layer 10 of an electronic circuit package in accordance with the present invention.
- the first substrate 12 can be a printed circuit board core or a subcomposite.
- the first substrate 12 is preferably made of FR-4 type epoxy.
- a first surface metal 14 is situated on top of the first substrate 12 and covers some portion of the- upper surface of first substrate 12 .
- the first surface metal 14 forms a first conductive surface.
- the first surface metal 14 is made of a copper material.
- Lower dendrites 16 are formed at selected locations on the first surface metal 14 .
- the lower dendrites 16 preferably are made of palladium metal. Palladium metal possesses desired mechanical and physical properties. Other suitable metals for the lower dendrites include, but are not limited to, nickel or copper.
- the lower dendrites may be formed by a variety of methods.
- One such method is to apply a photoresist material to the area of first surface metal 14 and then expose and develop the resist (not shown) by photolithographic techniques to provide an exposed area on which the dendrites are to be formed.
- Typical photoresist materials are methacrylate polymeric resist compositions and electrohoretic resists such as those obtainable from Shipley or Nippon Paint.
- an intermediate layer of nickel (not shown) is electroplated onto the first surface metal 14 followed by an intermediate layer of palladium, after applying resist material.
- the nickel layer is typically about 1 to about 2.5 microns and more typically about 2 microns thick.
- the nickel covers the first surface metal 14 to prevent it from contaminating the palladium plating composition.
- this intermediate layer of palladium is typically about 1 to about 2.5 microns and more typically about 2 microns thick.
- the lower dendrites 16 then are formed on the intermediate palladium layer by any known technique such as by ultrasonic plating of palladium typically at about 80 to 100 milliamps/cm 2 of surface area of first surface metal 14 . It is preferred that the lower dendrites 16 are about 0.1 to 1.5 mil. in height. If desired, each of the lower dendrites 16 can be coated with a metal that could interface with or diffuse to form a metallic bond. For instance, the lower dendrites 16 can be coated with pure gold or with tin.
- the photoresist is then removed by stripping in a suitable solvent such as propylene carbonate.
- a layer of epoxy dielectric 18 is applied across the upper surface of substrate 12 .
- the dielectric 18 thus covers the substrate 12 , the first surface metal 14 and the lower dendrites 16 .
- the adhesive dielectric layer 18 typically is in the range of 1 mil. to 5 mil. in thickness.
- the epoxy based dielectric 18 is Morton LB 404.
- Other suitable adhesives include, but are not limited to, BT-resin, polyimide, Teflon, and polysiloxanes.
- the dielectric may be applied by vacuum lamination, screen coating, curtain coating, or roller coating. In the preferred embodiment of the invention, the adhesive is applied by vacuum lamination of a dry film.
- the top of the layer 10 is a second substrate 20 .
- the second substrate 20 in the preferred embodiment of the invention, is made of epoxy glass.
- a second surface metal 22 is situated on the lower surface of second substrate 20 and covers some portion of second substrate 20 .
- the second surface metal 22 forms a second conductive surface.
- the second surface metal 22 is made of a copper material.
- the first substrate 12 and the second substrate 20 may be made of the same material, but are not required to be.
- the first surface metal 14 may be made of the same material as the second surface metal 22 , but is not required to be.
- Upper dendrites 24 are formed at selected locations on the second surface metal 22 .
- the upper dendrites 24 typically are made in the same manner and have the same composition as the lower dendrites 16 . However, this is not required.
- the upper dendrites preferably are formed to a height of 0.1 to 1.5 mil. If desired, the upper dendrites 24 also can be coated with a metal, as described above.
- the second substrate 20 having the second surface metal 22 and the upper dendrites 24 , then is attached compressively to the first substrate 12 that has the dielectric layer 18 .
- the separation 26 between the first surface metal 14 and the second surface metal 22 is about 0.2 to 2 mil.
- the upper dendrites 24 are in contact with the lower dendrites 16 , thereby forming an electrical connection between the first surface metal 14 and the second surface metal 22 .
- the upper dendrites 24 penetrate the adhesive layer 18 without any need for pre-drilled holes.
- the adhesive 18 may be heated to facilitate flow.
- the dielectric 18 will cure by heating after the mating is completed.
- the upper dendrites 24 should be positioned on the upper surface metal 22 to correspond with the position of the lower dendrites 16 on the lower surface metal 14 . Registration tolerance is large. Overlap of 1 mil. is desirable as long as 1 mil. clearance to an adjacent conductor is maintained.
- the dendrites 16 and 24 shown in FIG. 1 provide an electrical connection between the first surface metal 14 and the second surface metal 22 .
- the electrical connection is achieved without the need to drill or punch and plate through-holes or vias thereby simplifying the manufacturing process.
- Dendrites also can be used as electrical connectors when there are more than two layers involved.
- a circuitized core with dendrites formed in selected areas on it is deposited wherever a “through via” would exist in more traditional manufacturing.
- a “through via” is one that is intended to make contact with a conductor on the corresponding layer.
- the via in the core is used only to provide electrical connection for the dendrites for the through connection from surface metal on one substrate to surface metal on another substrate.
- FIG. 2 depicts the second embodiment of the invention.
- FIG. 2 shows a circuitized core 120 with a via 122 .
- Surface metal such as 114 , 124 , and 134 is attached to certain areas of the circuit board core 120 , the upper surface 132 and the lower surface 112 .
- Dendrites 116 , 126 , and 136 are formed on selected areas of the surface metal 114 , 124 and 134 .
- a dielectric adhesive 118 holds the dendrites 116 , 126 , and 136 in position relative to each other. Dendrites in contact with each other thus form an electrical connection between the upper surface 132 and lower surface 112 .
- FIG. 3 is a flow chart in accordance with the method of the present invention.
Abstract
A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
Description
- The present invention relates to electronic circuit packages with dendrites connecting two conductive surfaces through a film and method for producing same. The dendrites electrically connect the two conductive surfaces and avoid the need for drilling or punching holes for vias or through-holes.
- Electronic circuits contain many (sometimes millions) of components such as resistors, capacitors, inductors, diodes, electro-mechanical switches, and transistors. High density packaging of electronic components is particularly important to allow fast access to large amounts of data in computers. High density electronic circuit packages also are important in high frequency devices and communications devices. The components are connected to form circuits and circuits are connected to form functioning devices. The connections perform power and signal distribution. In a multi-layer electronic circuit package, some layers of the package serve as power planes and other layers serve as signal planes, depending on the operational requirements of the device. The devices require mechanical support and structural protection. The circuits themselves require electrical energy to function. The functioning devices, however, produce heat, or thermal energy which must be dissipated so that the devices do not stop functioning. Moreover, while high density packaging of a number of components can improve performance of the device, the heat produced by the power-consuming components can be such that performance and reliability of the devices is adversely impacted. The adverse impact arises from electrical problems such as increased resistivity and mechanical problems such as thermal stress caused by increased heat.
- Electronic circuit packages, such as chips, modules, circuit cards, circuit boards, and combinations of these, thus must meet a number of requirements for optimum performance. The package must be structurally sturdy enough to support and protect the components and the wiring. In addition, the package must be capable of dissipating heat and must have a coefficient of thermal expansion that is compatible with that of the components. Finally, to be commercially useful, the package should be inexpensive to produce and easy to manufacture.
- High density packages necessarily involve increased wiring density and thinner dielectric coatings between layers in a multi-layer electronic circuit package. The layers in a multi-layer package typically are electrically connected by vias and through-holes. The term “via” is used for a conductive pathway between adjacent layers in a multi-layer electronic circuit package. The term “through-hole” is used for a conductive pathway that extends to a non-adjacent layer. For high density packages the through-holes are increasingly narrow in diameter and the through-holes in each layer must be aligned precisely. This invention provides an alternative means of interconnection-namely electrical interconnection using dendrites. Dendrite interconnection avoids the need to drill or punch holes for vias or through-holes.
- An object of this invention is to provide a means for connecting two conductors along the vertical or z-axis without using vias or through-holes, but still resulting in tight tolerances and high yield. Dendrite interconnections accomplish this purpose.
- It is an object of this invention to provide an electronic circuit package with dendrites forming electrical connections between a first conductive layer and second conductive layer.
- A further object of this invention is to provide an electronic circuit package that provides electrical connection in the z-axis using dendrites, thereby eliminating the need for drilling or punching through-holes or vias in the manufacturing process of the electronic circuit package.
- A third object of this invention is to provide a method of fabrication of electronic circuit packages with dendrites forming electrical connections between a first conductive layer and a second conductive layer.
- Accordingly, a method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy dielectric material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
- It is an advantage of the present invention that the dendrites provide electrical connection between two conductive layers of the electronic circuit package.
- It is a further advantage that the dendrites provide electrical connection in the z-axis using dendrites, thereby eliminating the need for photodefining, laser ablating, drilling or punching through-holes or vias in the manufacturing process of the electronic circuit package.
- Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment of the invention taken in conjunction with the accompanying drawings and examples.
- FIG. 1 is a depiction of a single layer of a multi-layer electronic circuit package using dendrites, rather than through-holes or vias, to electrically connect two conductive surfaces, in accordance with the present invention.
- FIG. 2 is a depiction of two layers of a multi-layer electronic circuit package using dendrites to provide an electrical connection where a “through via” would exist in more traditional manufacturing.
- FIG. 3 is a flow chart of the method of the present invention.
- The present invention is of an electronic circuit package using dendrites to provide connection between two conductive surfaces, thereby avoiding the need to photodefine, laser ablate, drill or punch through-holes or vias. The invention can best be understood by reference to the drawings.
- FIG. 1 illustrates a
sample layer 10 of an electronic circuit package in accordance with the present invention. Referring to FIG. 1, at the bottom of thelayer 10 is afirst substrate 12. Thefirst substrate 12 can be a printed circuit board core or a subcomposite. Thefirst substrate 12 is preferably made of FR-4 type epoxy. Afirst surface metal 14 is situated on top of thefirst substrate 12 and covers some portion of the- upper surface offirst substrate 12. Thefirst surface metal 14 forms a first conductive surface. In the preferred embodiment of the invention, thefirst surface metal 14 is made of a copper material. -
Lower dendrites 16 are formed at selected locations on thefirst surface metal 14. Thelower dendrites 16 preferably are made of palladium metal. Palladium metal possesses desired mechanical and physical properties. Other suitable metals for the lower dendrites include, but are not limited to, nickel or copper. - The lower dendrites may be formed by a variety of methods. One such method is to apply a photoresist material to the area of
first surface metal 14 and then expose and develop the resist (not shown) by photolithographic techniques to provide an exposed area on which the dendrites are to be formed. - Typical photoresist materials are methacrylate polymeric resist compositions and electrohoretic resists such as those obtainable from Shipley or Nippon Paint.
- According to a preferred method, an intermediate layer of nickel (not shown) is electroplated onto the
first surface metal 14 followed by an intermediate layer of palladium, after applying resist material. - The nickel layer is typically about 1 to about 2.5 microns and more typically about 2 microns thick. The nickel covers the
first surface metal 14 to prevent it from contaminating the palladium plating composition. - In addition this intermediate layer of palladium is typically about 1 to about 2.5 microns and more typically about 2 microns thick.
- The
lower dendrites 16 then are formed on the intermediate palladium layer by any known technique such as by ultrasonic plating of palladium typically at about 80 to 100 milliamps/cm2 of surface area offirst surface metal 14. It is preferred that thelower dendrites 16 are about 0.1 to 1.5 mil. in height. If desired, each of thelower dendrites 16 can be coated with a metal that could interface with or diffuse to form a metallic bond. For instance, thelower dendrites 16 can be coated with pure gold or with tin. - The photoresist is then removed by stripping in a suitable solvent such as propylene carbonate.
- Once the
lower dendrites 16 are formed, a layer ofepoxy dielectric 18 is applied across the upper surface ofsubstrate 12. The dielectric 18 thus covers thesubstrate 12, thefirst surface metal 14 and thelower dendrites 16. Theadhesive dielectric layer 18 typically is in the range of 1 mil. to 5 mil. in thickness. In the preferred embodiment of the invention, the epoxy baseddielectric 18 is Morton LB 404. Other suitable adhesives include, but are not limited to, BT-resin, polyimide, Teflon, and polysiloxanes. The dielectric may be applied by vacuum lamination, screen coating, curtain coating, or roller coating. In the preferred embodiment of the invention, the adhesive is applied by vacuum lamination of a dry film. - The top of the
layer 10 is asecond substrate 20. Thesecond substrate 20 in the preferred embodiment of the invention, is made of epoxy glass. Asecond surface metal 22 is situated on the lower surface ofsecond substrate 20 and covers some portion ofsecond substrate 20. Thesecond surface metal 22 forms a second conductive surface. In the preferred embodiment of the invention, thesecond surface metal 22 is made of a copper material. - The
first substrate 12 and thesecond substrate 20 may be made of the same material, but are not required to be. Thefirst surface metal 14 may be made of the same material as thesecond surface metal 22, but is not required to be. -
Upper dendrites 24 are formed at selected locations on thesecond surface metal 22. Theupper dendrites 24 typically are made in the same manner and have the same composition as thelower dendrites 16. However, this is not required. The upper dendrites preferably are formed to a height of 0.1 to 1.5 mil. If desired, theupper dendrites 24 also can be coated with a metal, as described above. - The
second substrate 20, having thesecond surface metal 22 and theupper dendrites 24, then is attached compressively to thefirst substrate 12 that has thedielectric layer 18. After compression, theseparation 26 between thefirst surface metal 14 and thesecond surface metal 22 is about 0.2 to 2 mil. As a result of the compression, theupper dendrites 24 are in contact with thelower dendrites 16, thereby forming an electrical connection between thefirst surface metal 14 and thesecond surface metal 22. - The
upper dendrites 24 penetrate theadhesive layer 18 without any need for pre-drilled holes. To facilitate the mating process of theupper dendrites 24 to thelower dendrites 16, the adhesive 18 may be heated to facilitate flow. The dielectric 18 will cure by heating after the mating is completed. - To achieve optimum electrical connection, the
upper dendrites 24 should be positioned on theupper surface metal 22 to correspond with the position of thelower dendrites 16 on thelower surface metal 14. Registration tolerance is large. Overlap of 1 mil. is desirable as long as 1 mil. clearance to an adjacent conductor is maintained. - The advantages of the
dendrites dendrites first surface metal 14 and thesecond surface metal 22. Second, the electrical connection is achieved without the need to drill or punch and plate through-holes or vias thereby simplifying the manufacturing process. - Dendrites also can be used as electrical connectors when there are more than two layers involved. In an alternative embodiment of the invention, a circuitized core with dendrites formed in selected areas on it is deposited wherever a “through via” would exist in more traditional manufacturing. A “through via” is one that is intended to make contact with a conductor on the corresponding layer. The via in the core is used only to provide electrical connection for the dendrites for the through connection from surface metal on one substrate to surface metal on another substrate.
- FIG. 2 depicts the second embodiment of the invention. FIG. 2 shows a
circuitized core 120 with a via 122. Surface metal such as 114, 124, and 134 is attached to certain areas of thecircuit board core 120, theupper surface 132 and thelower surface 112.Dendrites surface metal dielectric adhesive 118 holds thedendrites upper surface 132 andlower surface 112. - The entire process described with respect to the two embodiments can be repeated to create more layers interconnected by dendrites as described above.
- FIG. 3 is a flow chart in accordance with the method of the present invention.
- Although specific embodiments have been described herein for purposes of illustration, various modifications may be made without departing from the spirit or scope of the invention.
Claims (47)
1. A method for electrically connecting two conductive surfaces in an electronic circuit package comprising the steps of:
applying to a first substrate a first surface metal forming a first conductive surface;
applying lower dendrites to selected areas of the first surface metal;
applying a dielectric material to cover the first surface metal and the lower dendrites;
applying to a second substrate a second surface metal forming a second conductive surface;
applying upper dendrites to selected areas of the second surface metal;
compressively attaching the first substrate to the second substrate such that the upper dendrites are mated to the lower dendrites.
2. The method of , wherein the first substrate is made of glass-reinforced epoxy.
claim 1
3. The method of , wherein the first surface metal is made of a copper material.
claim 1
4. The method of , wherein the step of applying the lower dendrites further comprises:
claim 1
applying a photoresist material to the area of the first surface metal;
exposing and developing the photoresist material;
applying a layer of nickel to the first surface metal;
applying a layer of palladium over the layer of nickel;
forming the lower dendrites on the palladium layer by ultrasonic plating of palladium; and
removing the photoresist material.
5. The method of , wherein the lower dendrites are formed to a height of approximately 1 mil.
claim 1
6. The method of , wherein the lower dendrites are made of palladium material.
claim 1
7. The method of , wherein the adhesive is an epoxy based dielectric.
claim 1
8. The method of wherein the adhesive is selected from a group comprising BT-resin, polyimide, Teflon, and polysiloxanes.
claim 1
9. The method of , wherein the adhesive is applied by vacuum lamination.
claim 1
10. The method of , wherein the second substrate is made of glass reinforced epoxy resin.
claim 1
11. The method of , wherein the second surface metal is made of a copper material.
claim 1
12. The method of , wherein the step of applying the upper dendrites further comprises:
claim 1
applying a photoresist material to the area of the first surface metal;
exposing and developing the photoresist material;
applying a layer of nickel to the second surface metal;
applying a layer of palladium over the layer of nickel;
forming the lower dendrites on the palladium layer by ultrasonic plating of palladium; and
removing the photoresist material.
13. The method of , wherein the upper dendrites are formed to a height of approximately 1 mil.
claim 1
14. The method of , wherein the upper dendrites are made of palladium material.
claim 1
15. The method of , wherein the method is repeated as needed to meet the manufacturing requirements for a multi-layer electronic circuit package.
claim 1
16. An electronic circuit package comprising:
a first substrate;
a first surface metal forming a first conductive surface on top of the first substrate;
lower dendrites formed on selected areas of the first surface metal;
a second substrate;
a second surface metal forming a second conductive surface on the lower surface of the second substrate;
upper dendrites formed on selected areas of the second surface metal; and
means for mating the upper dendrites to the lower dendrites.
17. The electronic circuit package of , wherein the first substrate is glass reinforced epoxy.
claim 16
18. The electronic circuit package of , wherein the first surface metal is made of a copper material.
claim 16
19. The electronic circuit package of , wherein the lower dendrites are formed to a height of approximately 1 mil.
claim 16
20. The electronic circuit package of , wherein the lower dendrites are made of palladium material.
claim 16
21. The electronic circuit package of , wherein the second substrate is glass reinforced epoxy.
claim 16
22. The electronic circuit package of , wherein the second surface metal is made of a copper material.
claim 16
23. The electronic circuit package of , wherein the upper dendrites are formed to a height of approximately 1.5 mil.
claim 16
24. The electronic circuit package of , wherein the upper dendrites are made of palladium material.
claim 16
25. The electronic circuit package of wherein the means for mating is an adhesive.
claim 16
26. The electronic circuit package of wherein the adhesive is an epoxy based dielectric.
claim 25
27. The electronic circuit package of wherein the adhesive is selected from a group comprising BT-resin, polyimide, Teflon, and polysiloxanes.
claim 25
28. The electronic circuit package of wherein the adhesive is applied by vacuum lamination.
claim 25
29. A method for electrically connecting multiple conductive surfaces in an electronic circuit package comprising the steps of:
applying to a first substrate a first surface metal forming a first conductive surface;
applying lower dendrites to selected areas of the first surface metal;
applying a dielectric material to cover the first surface metal and the lower dendrites;
applying to a second substrate a second surface metal forming a second conductive surface;
applying second-level dendrites to selected areas of the second surface metal;
applying to the second substrate a third surface metal forming a third conductive surface;
applying third-level dendrites to selected areas of the third surface metal;
applying a dielectric material to cover the third surface metal and the third-level dendrites;
applying to a third substrate a fourth surface metal forming a fourth conductive surface;
applying upper dendrites to selected areas of the fourth surface metal;
compressively attaching the first substrate to the second substrate such that the lower dendrites are mated to the second-level dendrites; and
compressively attaching the second substrate to the third substrate such that the third-level dendrites are mated to the upper dendrites.
30. The method of , wherein at least one substrate is made of glass-reinforced epoxy.
claim 29
31. The method of , wherein at least one surface metal is made of a copper material.
claim 29
32. The method of , wherein the step of applying the dendrites further comprises:
claim 29
applying a photoresist material to the area of surface metal;
exposing and developing the photoresist material;
applying a layer of nickel to the surface metal;
applying a layer of palladium over the layer of nickel;
forming the dendrites on the palladium layer by ultrasonic plating of palladium; and
removing the photoresist material.
33. The method of , wherein the dendrites are formed to a height of approximately 1 mil.
claim 29
34. The method of , wherein the dendrites are made of palladium material.
claim 29
35. The method of , wherein the adhesive is an epoxy based dielectric.
claim 29
36. The method of , wherein the adhesive is selected from a group comprising BT-resin, polyimide, Teflon, and polysiloxanes.
claim 29
37. The method of , wherein the adhesive is applied by vacuum lamination.
claim 29
38. The method of , wherein the method is repeated as needed to meet the manufacturing requirements for a multi-layer electronic circuit package.
claim 29
39. An electronic circuit package comprising:
a first substrate;
a first surface metal forming a first conductive surface on top of the first substrate;
lower dendrites formed on selected areas of the first surface metal;
a second substrate;
a second surface metal forming a second conductive surface on the lower surface of the second substrate;
second-level dendrites formed on selected areas of the second surface metal;
a third surface metal forming a third conductive surface on the upper surface of the second substrate;
third-level dendrites formed on selected areas of the third surface metal;
a third substrate;
a fourth surface metal forming a fourth conductive surface on the lower surface of the third substrate;
upper dendrites formed on selected areas of the fourth surface metal;
means for mating the lower dendrites to the second-level dendrites; and
means for mating the third-level dendrites to the upper dendrites.
40. The electronic circuit package of , wherein the first substrate is glass reinforced epoxy.
claim 39
41. The electronic circuit package of , wherein at least one surface metal is made of a copper material.
claim 39
42. The electronic circuit package of , wherein the dendrites are formed to a height of approximately 1 mil.
claim 39
43. The electronic circuit package of , wherein the dendrites are made of palladium material.
claim 39
44. The electronic circuit package of wherein the means for mating is an adhesive.
claim 39
45. The electronic circuit package of wherein the adhesive is an epoxy based dielectric.
claim 44
46. The electronic circuit package of wherein the adhesive is selected from a group comprising BT-resin, polimide, Teflon, and polysiloxanes.
claim 44
47. The electronic circuit package of wherein the adhesive is applied by vacuum lamination.
claim 44
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/859,690 US6427323B2 (en) | 1997-08-25 | 2001-05-17 | Method for producing conductor interconnect with dendrites |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/918,084 US6300575B1 (en) | 1997-08-25 | 1997-08-25 | Conductor interconnect with dendrites through film |
US09/315,305 US6256874B1 (en) | 1997-08-25 | 1999-05-20 | Conductor interconnect with dendrites through film and method for producing same |
US09/859,690 US6427323B2 (en) | 1997-08-25 | 2001-05-17 | Method for producing conductor interconnect with dendrites |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/315,305 Division US6256874B1 (en) | 1997-08-25 | 1999-05-20 | Conductor interconnect with dendrites through film and method for producing same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010034937A1 true US20010034937A1 (en) | 2001-11-01 |
US6427323B2 US6427323B2 (en) | 2002-08-06 |
Family
ID=25439775
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/918,084 Expired - Fee Related US6300575B1 (en) | 1997-08-25 | 1997-08-25 | Conductor interconnect with dendrites through film |
US09/315,305 Expired - Fee Related US6256874B1 (en) | 1997-08-25 | 1999-05-20 | Conductor interconnect with dendrites through film and method for producing same |
US09/859,690 Expired - Fee Related US6427323B2 (en) | 1997-08-25 | 2001-05-17 | Method for producing conductor interconnect with dendrites |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/918,084 Expired - Fee Related US6300575B1 (en) | 1997-08-25 | 1997-08-25 | Conductor interconnect with dendrites through film |
US09/315,305 Expired - Fee Related US6256874B1 (en) | 1997-08-25 | 1999-05-20 | Conductor interconnect with dendrites through film and method for producing same |
Country Status (2)
Country | Link |
---|---|
US (3) | US6300575B1 (en) |
KR (1) | KR100278570B1 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6847529B2 (en) * | 1999-07-15 | 2005-01-25 | Incep Technologies, Inc. | Ultra-low impedance power interconnection system for electronic packages |
US20030214800A1 (en) | 1999-07-15 | 2003-11-20 | Dibene Joseph Ted | System and method for processor power delivery and thermal management |
JP3708005B2 (en) * | 2000-08-09 | 2005-10-19 | 日本無線株式会社 | Hole filling method for printed wiring boards |
TW491452U (en) * | 2001-06-05 | 2002-06-11 | Darfon Electronics Corp | Soft circuit board |
FR2828334A1 (en) * | 2001-08-03 | 2003-02-07 | Schlumberger Systems & Service | Restoration of electrical and mechanical connectability to an electrical device with a face equipped with contact studs using an fixing layer crossed by conducting tracks |
US7015580B2 (en) * | 2003-11-25 | 2006-03-21 | International Business Machines Corporation | Roughened bonding pad and bonding wire surfaces for low pressure wire bonding |
FR2866753B1 (en) * | 2004-02-25 | 2006-06-09 | Commissariat Energie Atomique | MICROELECTRONIC INTERCONNECTION DEVICE WITH LOCALIZED CONDUCTIVE RODS |
JP2006147867A (en) * | 2004-11-19 | 2006-06-08 | Sharp Corp | Method of manufacturing printed wiring board |
US7666008B2 (en) * | 2006-09-22 | 2010-02-23 | Onanon, Inc. | Conductive elastomeric and mechanical pin and contact system |
CN103094737A (en) * | 2011-11-05 | 2013-05-08 | 宝宸(厦门)光学科技有限公司 | Pin structure and pin connecting structure |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3359145A (en) | 1964-12-28 | 1967-12-19 | Monsanto Res Corp | Electrically conducting adhesive |
US3795047A (en) * | 1972-06-15 | 1974-03-05 | Ibm | Electrical interconnect structuring for laminate assemblies and fabricating methods therefor |
JPS5357481A (en) | 1976-11-04 | 1978-05-24 | Canon Inc | Connecting process |
FR2387529A1 (en) | 1977-04-15 | 1978-11-10 | Ibm | CONTACTS AND ELECTRICAL CONNECTIONS TO DENDRITES |
US5137461A (en) | 1988-06-21 | 1992-08-11 | International Business Machines Corporation | Separable electrical connection technology |
EP0360971A3 (en) | 1988-08-31 | 1991-07-17 | Mitsui Mining & Smelting Co., Ltd. | Mounting substrate and its production method, and printed wiring board having connector function and its connection method |
US5298685A (en) | 1990-10-30 | 1994-03-29 | International Business Machines Corporation | Interconnection method and structure for organic circuit boards |
US5371654A (en) * | 1992-10-19 | 1994-12-06 | International Business Machines Corporation | Three dimensional high performance interconnection package |
EP0647090B1 (en) * | 1993-09-03 | 1999-06-23 | Kabushiki Kaisha Toshiba | Printed wiring board and a method of manufacturing such printed wiring boards |
JPH07288385A (en) * | 1994-04-19 | 1995-10-31 | Hitachi Chem Co Ltd | Multilayer wiring board and its manufacture |
US5509200A (en) | 1994-11-21 | 1996-04-23 | International Business Machines Corporation | Method of making laminar stackable circuit board structure |
US5939786A (en) * | 1996-11-08 | 1999-08-17 | International Business Machines Corporation | Uniform plating of dendrites |
US5977642A (en) * | 1997-08-25 | 1999-11-02 | International Business Machines Corporation | Dendrite interconnect for planarization and method for producing same |
-
1997
- 1997-08-25 US US08/918,084 patent/US6300575B1/en not_active Expired - Fee Related
-
1998
- 1998-08-25 KR KR1019980034391A patent/KR100278570B1/en not_active IP Right Cessation
-
1999
- 1999-05-20 US US09/315,305 patent/US6256874B1/en not_active Expired - Fee Related
-
2001
- 2001-05-17 US US09/859,690 patent/US6427323B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6256874B1 (en) | 2001-07-10 |
US6427323B2 (en) | 2002-08-06 |
KR19990023840A (en) | 1999-03-25 |
US6300575B1 (en) | 2001-10-09 |
KR100278570B1 (en) | 2001-01-15 |
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