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Publication numberUS20010035546 A1
Publication typeApplication
Application numberUS 09/841,105
Publication dateNov 1, 2001
Filing dateApr 25, 2001
Priority dateApr 27, 2000
Also published asUS6347048
Publication number09841105, 841105, US 2001/0035546 A1, US 2001/035546 A1, US 20010035546 A1, US 20010035546A1, US 2001035546 A1, US 2001035546A1, US-A1-20010035546, US-A1-2001035546, US2001/0035546A1, US2001/035546A1, US20010035546 A1, US20010035546A1, US2001035546 A1, US2001035546A1
InventorsTakashi Kumagai, Masahiro Takeuchi, Satoru Kodaira, Takafumi Noda
Original AssigneeSeiko Epson Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory device
US 20010035546 A1
Abstract
A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.
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Claims(12)
What is claimed is:
1. A semiconductor memory device comprising:
a memory cell which includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein:
the memory cell has first and second gate electrode layers, first and second drain-drain connecting layers, first and second drain-gate connecting layers, and a source contact layer;
the first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor;
the second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor;
a source region of the first and second driver transistors is located in a region between the first and second gate electrode layers;
the source contact layer is located in the region between the first and second gate electrode layers;
the first and second drain-drain connecting layers are located higher than the first and second gate electrode layers;
the first and second gate electrode layers are located between the first and second drain-drain connecting layers;
the first drain-drain connecting layer connects a drain region of the first driver transistor to a drain region of the first load transistor;
the second drain-drain connecting layer connects a drain region of the second driver transistor to a drain region of the second load transistor;
the first and second drain-gate connecting layers are located higher than the first and second gate electrode layers;
the first and second drain-gate connecting layers are located in a different layer from the first and second drain-drain connecting layers;
the first drain-gate connecting layer connects the first drain-drain connecting layer to the second gate electrode layer; and
the second drain-gate connecting layer connects the second drain-drain connecting layer to the first gate electrode layer.
2. The semiconductor memory device as defined in
claim 1
,
wherein the width of the source region is approximately uniform.
3. The semiconductor memory device as defined in
claim 1
,
wherein the source contact layer is located in the source region.
4. The semiconductor memory device as defined in
claim 1
, further comprising a word line, wherein:
the word line is located on the side of the first and second driver transistors;
the word line includes gate electrodes of the first and second transfer transistors; and
the word line has a linear pattern.
5. The semiconductor memory device as defined in
claim 4
, further comprising:
another memory cell which includes a third transfer transistor and a fourth transfer transistor;
first and second bit lines;
another word line; and
a well contact region, wherein:
the other memory cell is located adjacent to the memory cell;
the first and third transfer transistors use in common a first source/drain region to which the first bit line is connected;
the second and fourth transfer transistors use in common a second source/drain region to which the second bit line is connected;
the other word line includes gate electrodes of the third and fourth transfer transistors;
the other word line has a linear pattern;
the well contact region is located between the word line and the other word line; and
the memory cell and the other memory cell uses in common the well contact region.
6. The semiconductor memory device as defined in
claim 5
,
wherein the word line is located between the source region and the well contact region.
7. The semiconductor memory device as defined in
claim 5
, further comprising a contact pad layer, wherein:
the contact pad layer is used to connect the well contact region and the source region of the first and second driver transistors to a ground line; and
the contact pad layer is located in the same layer as the first and second drain-drain connecting layers.
8. The semiconductor memory device as defined in
claim 1
, wherein:
the first and second driver transistors are n-type;
the first and second load transistors are p-type;
the first and second transfer transistors are n-type;
the memory cell includes first, second, third and fourth conductive layers;
the first and second gate electrode layers and a subword line are located in the first conductive layer;
the first and second drain-drain connecting layers, a power supply line, and first, second and third contact pad layers are located in the second conductive layer;
the first and second drain-gate connecting layers, a main-word line, and fourth, fifth and sixth contact pad layers are located in the third conductive layer;
first and second bit lines and a ground line are located in the fourth conductive layer;
the sub-word line extends in a first direction;
the power supply line is connected to source regions of the first and second load transistors;
the first contact pad layer is used to connect the first bit line to a source/drain region of the first transfer transistor;
the second contact pad layer is used to connect the second bit line to a source/drain region of the second transfer transistor;
the third contact pad layer is used to connect the source region of the first and second driver transistors to the ground line;
the main-word line extends in the first direction;
the fourth contact pad layer is used to connect the first bit line to the source/drain region of the first transfer transistor;
the fifth contact pad layer is used to connect the second bit line to the source/drain region of the second transfer transistor;
the sixth contact pad layer is used to connect the source region of the first and second driver transistors to the ground line; and
the first and second bit lines extend in a second direction which is perpendicular to the first direction.
9. The semiconductor memory device as defined in
claim 1
, further comprising:
a plurality of the memory cells, a plurality of well contact regions of a primary conductivity type, and a plurality of well contact regions of a secondary conductivity type;
wherein each of the well contact regions of the primary conductivity type is provided for a group of a predetermined number of memory cells arrayed in a first direction among the plurality of the memory cells; and
wherein each of the well contact regions of the secondary conductivity type is provided for a group of two of the memory cells arrayed in a second direction which is perpendicular to the first direction.
10. The semiconductor memory device as defined in
claim 9
,
wherein the primary conductivity type is n-type and the secondary conductivity type is p-type.
11. The semiconductor memory device as defined in
claim 1
,
wherein each of the first and second gate electrode layers and the first and second drain-drain connecting layers has a linear pattern; and
wherein the first and second gate electrode layers and the first and second drain-drain connecting layers are parallel to each other.
12. The semiconductor memory device as defined in
claim 1
,
wherein each of the memory cells is 4.5 μm2 or less in area.
Description
TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory device such as a static random access memory (SRAM).

BACKGROUND

[0002] An SRAM, which is one type of semiconductor memory device, does not need refreshing. Therefore, the SRAM enables the system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for portable devices such as portable telephones.

[0003] There has been a demand for miniaturization of portable devices. To deal with this demand, the memory cell size of the SRAM must be reduced.

SUMMARY

[0004] An objective of certain embodiments of the present invention is to provide a semiconductor memory device having memory cells of a reduced size.

[0005] According to one embodiment of the present invention, there is provided a semiconductor memory device comprising:

[0006] a memory cell which includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein:

[0007] the memory cell has first and secondgate electrode layers, first and second drain-drain connecting layers, first and second drain-gate connecting layers, and a source contact layer;

[0008] the first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor;

[0009] the second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor;

[0010] a source region of the first and second driver transistors is located in a region between the first and second gate electrode layers;

[0011] the source contact layer is located in the region between the first and second gate electrode layers;

[0012] the first and second drain-drain connecting layers are located higher than the first and second gate electrode layers;

[0013] the first and second gate electrode layers are located between the first and second drain-drain connecting layers;

[0014] the first drain-drain connecting layer connects a drain region of the first driver transistor to a drain region of the first load transistor;

[0015] the second drain-drain connecting layer connects a drain region of the second driver transistor to a drain region of the second load transistor;

[0016] the first and second drain-gate connecting layers are located higher than the first and second gate electrode layers;

[0017] the first and second drain-gate connecting layers are located in a different layer from the first and second drain-drain connecting layers;

[0018] the first drain-gate connecting layer connects the first drain-drain connecting layer to the second gate electrode layer; and

[0019] the second drain-gate connecting layer connects the second drain-drain connecting layer to the first gate electrode layer.

[0020] The semiconductor memory device according to this embodiment of the present invention includes the gate electrode layers which become gates of inverters, the drain-drain connecting layers for connecting drains of the inverters, and the drain-gate connecting layers for connecting the gate of one inverter to the drain of the other inverter. In this semiconductor memory device, a flip-flop is formed of three layers (gate electrode layer, drain-drain connecting layer, and drain-gate connecting layer). Therefore, the pattern of each layer can be simplified (linear pattern, for example) in comparison with the case of forming a flip-flop of two layers. According to this semiconductor memory device, since the pattern of each layer can be thus simplified, a semiconductor memory device with a memory cell size of 4.5 μm2 or less can be fabricated, for example.

[0021] According to this semiconductor memory device, the first gate and second gate electrode layers are located between the first drain-drain connecting layer and the second drain-drain connecting layer. Therefore, the source contact layer of the driver transistors can be disposed at the center of the memory cell. Moreover, a wiring layer which is formed in the same layer as the drain-drain connecting layer and to which the source contact layer is connected can be disposed at the center of the memory cell. This increases the degree of freedom relating to the formation of the first and second drain-gate connecting layers, whereby the memory cell size can be reduced. In the present invention, the source contact layer is a conductive layer used to connect the source region of the driver transistor to the wiring layer.

[0022] According to this semiconductor memory device, the drain-gate connecting layers are located higher than the gate electrode layers and the drain-drain connecting layers. Therefore, the source contact layer can be located in the region between gate electrode layers (or region between the first gate electrode layer and second gate electrode layer) while preventing the drain-gate connecting layer from coming in contact with the source contact layer. Therefore, parasitic resistance of the driver transistors can be decreased. Moreover, the pattern of the source region can be simplified (for example, a pattern with a uniform width such as an approximately linear pattern or rectangular pattern), whereby reproducibility of the pattern of the source region can be improved in a photolithography process. This increases dimensional accuracy of the channel width of the driver transistors, whereby the operation of the memory cell can be stabilized.

[0023] In this semiconductor memory device, the width of the source region may be approximately uniform.

[0024] The source contact layer may be located in the source region.

[0025] This semiconductor memory device may further comprise a word line, wherein: the word line is located on the side of the first and second driver transistors; the word line includes gate electrodes of the first and second transfer transistors; and the word line has a linear pattern.

[0026] According to this configuration, since the pattern of the word line is linear, the length of the word line can be decreased in comparison with a word line having a partly curved pattern. Therefore, according to this configuration, the resistance of the word line can be decreased. The width of a word line having a partly curved pattern tends to be decreased at the curved section. This causes the narrow line effect of silicide to occur in a salicide of the word line, whereby the resistance of the word line locally increases. According to this configuration, since the pattern of the word line is linear and does not have a curved section, occurrence of the narrow line effect of silicide caused by the curved section can be prevented, thereby preventing a local increase in the resistance of the word line due to the narrow line effect of silicide.

[0027] This semiconductor memory device may further comprise:

[0028] another memory cell which includes a third transfer transistor and a fourth transfer transistor;

[0029] first and second bit lines;

[0030] another word line; and

[0031] a well contact region, wherein:

[0032] the other memory cell is located adjacent to the memory cell;

[0033] the first and third transfer transistors use in common a first source/drain region to which the first bit line is connected;

[0034] the second and fourth transfer transistors use in common a second source/drain region to which the second bit line is connected;

[0035] the other word line includes gate electrodes of the third and fourth transfer transistors;

[0036] the other word line has a linear pattern;

[0037] the well contact region is located between the word line and the other word line; and

[0038] the memory cell and the other memory cell uses in common the well contact region.

[0039] According to this configuration, since the above word line and the other word line have a linear pattern, the well contact region can be located between the above word line and the other word line without increasing the memory cell area. Therefore, the size of the semiconductor memory device can be reduced.

[0040] According to this configuration, occurrence of latchup in the semiconductor memory device can be prevented. The reasons therefor are described below. Generally, when drain current flows by operating a transistor, substrate current (current from end section of drain to well contact region) flows. In particular, a large amount of substrate current flows in a driver transistor of which a word line is selected. An increase in the electric potential equivalent to the product of the substrate current and substrate resistance (well resistance) causes latchup to occur. According to this configuration, however, the well contact region can be disposed in the memory cell as well as in the well in which the driver transistors and the transfer transistors are formed. Moreover, the well contact region can be disposed in every memory cell in the direction of the word line. Therefore, the driver transistors and the well contact region can be located close together, whereby the substrate resistance can be decreased. Because of this, according to this configuration, occurrence of latchup can be prevented. In addition, the well contact region is preferably p-type.

[0041] In this semiconductor memory device, the word line may be located between the source region and the well contact region.

[0042] This semiconductor memory device may further comprise a contact pad layer, wherein:

[0043] the contact pad layer is used to connect the well contact region and the source region of the first and second driver transistors to a ground line; and

[0044] the contact pad layer is located in the same layer as the first and second drain-drain connecting layers.

[0045] According to this configuration, since a plurality of contacts can be disposed from the contact pad layer to the ground line, the parasitic resistance of the source region can be reduced. According to this configuration, the first and second gate electrode layers are located between the first drain-drain connecting layer and the second drain-drain connecting layer, and the contact pad layer is located between the first gate electrode layer and the second gate electrode layer. The contact pad layer and each gate electrode layer have a relation in which one is the upper layer and the other is the lower layer. Therefore, the contact pad layer can be disposed in the same layer as the drain-drain connecting layers without increasing the memory cell size. According to this configuration, the memory cell and the other memory cell can use in common the contact pad layer having a linear pattern.

[0046] In this semiconductor memory device,

[0047] the first and second driver transistors may be n-type;

[0048] the first and second load transistors may be p-type;

[0049] the first and second transfer transistors may be n-type;

[0050] the memory cell may include first, second, third and fourth conductive layers;

[0051] the first and second gate electrode layers and a subword line may be located in the first conductive layer;

[0052] the first and second drain-drain connecting layers, a power supply line, and first, second and third contact pad layers may be located in the second conductive layer;

[0053] the first and second drain-gate connecting layers, a main-word line, and fourth, fifth and sixth contact pad layers may be located in the third conductive layer;

[0054] first and second bit lines and a ground line may be located in the fourth conductive layer;

[0055] the sub-word line may extend in a first direction;

[0056] the power supply line may be connected to source regions of the first and second load transistors;

[0057] the first contact pad layer may be used to connect the first bit line to a source/drain region of the first transfer transistor;

[0058] the second contact pad layer may be used to connect the second bit line to a source/drain region of the second transfer transistor;

[0059] the third contact pad layer may be used to connect the source region of the first and second driver transistors to the ground line;

[0060] the main-word line may extend in the first direction;

[0061] the fourth contact pad layer may be used to connect the first bit line to the source/drain region of the first transfer transistor;

[0062] the fifth contact pad layer may be used to connect the second bit line to the source/drain region of the second transfer transistor;

[0063] the sixth contact pad layer may be used to connect the source region of the first and second driver transistors to the ground line; and

[0064] the first and second bit lines may extend in a second direction which is perpendicular to the first direction.

[0065] According to this configuration, various properties (such as miniaturization, reliability, stability, and speed) required for semiconductor memory devices can be well-balanced and improved.

[0066] This semiconductor memory device may further comprise a plurality of the memory cells, a plurality of well contact regions of a primary conductivity type, and a plurality of well contact regions of a secondary conductivity type;

[0067] wherein each of the well contact regions of the primary conductivity type may be provided for a group of a predetermined number of memory cells arrayed in a first direction among the plurality of the memory cells; and

[0068] wherein each of the well contact regions of the secondary conductivity type may be provided for a group of two of the memory cells arrayed in a second direction which is perpendicular to the first direction.

[0069] In this configuration, the well contact region of the secondary conductivity type can be provided for every two memory cells arrayed in the second direction. This is because the source contact layer can be located in the region between gate electrode layers as described above, thereby creating an areal margin near the boundary between the adjoining memory cells. Note that the predetermined number of memory cells may be 32 or 64, for example.

[0070] In this configuration, the primary conductivity type may be n-type and the secondary conductivity type may be p-type. According to this configuration, the well contact region of the well on which an n-type transistor is formed becomes p-type, and the well contact region of the well on which a p-type transistor is formed becomes n-type. This improves the latchup prevention effect. The reasons therefor are described below.

[0071] An increase in the electric potential equivalent to the product of the substrate current and the substrate resistance (well resistance) causes latchup to occur. Generally, the amount of the substrate current is greater in the n-type transistor than in the p-type transistor. For example, when the substrate current in the n-type transistor is 110−6 A/μm, the substrate current in the p-type transistor can be 110−9 A/μm, which is three digits smaller. The substrate resistance (well resistance) increases as the distance between the memory cell and the well contact region increases.

[0072] In this configuration, since the p-type well contact region is disposed in every two memory cells, the memory cell is located relatively close to the well contact region. Therefore, the substrate resistance (well resistance) can be relatively reduced. This ensures that the substrate resistance (well resistance) is relatively small even if the substrate current in the n-type transistor is relatively large, thereby preventing the product of the substrate current and the substrate resistance (well resistance) from increasing.

[0073] Since each n-type well contact region is provided for a group of a predetermined number (32, for example) of memory cells, some memory cells are located at a relatively long distance from the well contact region. Therefore, the substrate resistance (well resistance) relatively increases. However, since the substrate current in the p-type transistor is relatively small, the product of the substrate current and the substrate resistance (well resistance) can be prevented from increasing even if the substrate resistance (well resistance) is relatively large. These are reasons for improvement in the latchup prevention effect.

[0074] According to this configuration, the p-type well contact region can be connected to the ground line in the memory cell. This eliminates the need for a ground line used only for the p-type well contact region, whereby the size of the semiconductor memory device can be reduced.

[0075] In this semiconductor memory device, each of the first and second gate electrode layers and the first and second drain-drain connecting layers may have a linear pattern; and the first and second gate electrode layers and the first and second drain-drain connecting layers may be parallel to each other.

[0076] According to this configuration, since the pattern of each layer is simple, a semiconductor memory device with a minute memory cell size can be fabricated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0077]FIG. 1 is a plan view showing first, second and third conductive layers in part of a memory cell array of the embodiment of the present invention.

[0078]FIG. 2 is a plan view showing a field in part of the memory cell array of the embodiment of the present invention.

[0079]FIG. 3 is a plan view showing the first conductive layer in part of the memory cell array of the embodiment of the present invention.

[0080]FIG. 4 is a plan view showing plugs 61 in part of the memory cell array of the embodiment of the present invention.

[0081]FIG. 5 is a plan view showing the second conductive layer in part of the memory cell array of the embodiment of the present invention.

[0082]FIG. 6 is a plan view showing plugs 73 in part of the memory cell array of the embodiment of the present invention.

[0083]FIG. 7 is a plan view showing plugs 75 in part of the memory cell array of the embodiment of the present invention.

[0084]FIG. 8 is a plan view showing the third conductive layer in part of the memory cell array of the embodiment of the present invention.

[0085]FIG. 9 is a plan view showing plugs 81 in part of the memory cell array of the embodiment of the present invention.

[0086]FIG. 10 is a plan view showing a fourth conductive layer in part of a memory cell array of the embodiment of the present invention.

[0087]FIG. 11 is a plan view showing the field, first conductive layer, and plugs 61 in the embodiment of the present invention.

[0088]FIG. 12 is a plan view showing the second conductive layer and the plugs 73 and 75 in the embodiment of the present invention.

[0089]FIG. 13 is a plan view showing the third conductive layer and the plugs 81 in the embodiment of the present invention.

[0090]FIG. 14 is a cross-sectional view of the embodiment of the present invention taken along the line B1-B2 of FIG. 2.

[0091]FIG. 15 is a cross-sectional view of the embodiment of the present invention taken along the line C1-C2 of FIG. 2.

[0092]FIG. 16 is an equivalent circuit diagram of the SRAM according to the embodiment of the present invention.

DETAILED DESCRIPTION

[0093] An embodiment of the semiconductor memory device according to the present invention will be described below. The present embodiment illustrates the case where the semiconductor memory device according to the present invention is applied to an SRAM. The outline of the structure of the present embodiment, the details of the structure, and the major effects of the present embodiment are described below.

[0094] 1. Outline of Structure of the Present Embodiment

[0095] The semiconductor memory device of the present embodiment is a type of memory in which one memory cell is formed by six MOS field effect transistors. The outline of the structure of the present embodiment is described below by separately describing the structure of a section which forms a flip-flop of the memory cell and the structure of the memory cell.

[0096] (a) Structure of Section which Forms Flip-flop of Memory Cell

[0097]FIG. 1 is a plan view showing a first conductive layer, a second conductive layer, and a third conductive layer in part of a memory cell array of the present embodiment. The first conductive layer, the second conductive layer, and the third conductive layer are individually described to ensure that FIG. 1 is readily understood.

[0098] Gate electrode layers 21 a and 21 b and sub-word lines 23 are disposed in the first conductive layer, as shown in FIG. 3. Drain-drain connecting layers 31 a and 31 b and the like are disposed in the second conductive layer, as shown in FIG. 5. Drain-gate connecting layers 41 a and 41 b and the like are disposed in the third conductive layer, as shown in FIG. 8. The structure shown in FIG. 5 is positioned on the structure shown in FIG. 3, and the structure shown in FIG. 8 is positioned on the structure shown in FIG. 5. FIG. 1 shows these structures collectively.

[0099]FIG. 1 shows a section which forms a flip-flop. This section is described below focusing on a region A. One memory cell is formed in the region A. The region A shown in other Figures has the same meaning.

[0100] In the region A, six MOS field effect transistors including n-channel transfer transistor Q1 and Q2, n-channel driver transistors Q3 and Q4, and p-channel load transistors Q5 and Q6 are formed. The driver transistor Q3 and the load transistor Q5 forms one CMOS inverter. The driver transistor Q4 and the load transistor Q6 forms one CMOS inverter. A flip-flop is formed by cross-coupling these two CMOS inverters. FIG. 16 shows an equivalent circuit of the circuit formed by the six MOS field effect transistors in the region A.

[0101] The gate electrode layer 21 a and the gate electrode layer 21 b respectively have a linear pattern, as shown in FIG. 1. The gate electrode layer 21 a forms gate electrodes of the driver transistor Q3 and the load transistor Q5 and connects these gate electrodes. The gate electrode layer 21 b forms gate electrodes of the driver transistor Q4 and the load transistor Q6 and connects these gate electrodes.

[0102] Drain of the driver transistor Q3 and drain of the load transistor Q5 are connected by the drain-drain connecting layer 31 a. Drain of the driver transistor Q4 and drain of the load transistor Q6 are connected by the drain-drain connecting layer 31 b. The drain-drain connecting layer 31 a and the drain-drain connecting layer 31 b respectively have a linear pattern.

[0103] The gate electrode (gate electrode layer 21 a) of the driver transistor Q3 and the load transistor Q5 and the drain-drain connecting layer 31 b are connected by the drain-gate connecting layer 41 b. The gate electrode (gate electrode layer 21 b) of the driver transistor Q4 and the load transistor Q6 and the drain-drain connecting layer 31 a are connected by the drain-gate connecting layer 41 a. The drain-gate connecting layer 41 a and the drain-gate connecting layer 41 b respectively have a pattern in the shape of the letter L. The angle formed the first side and the second side of the L-shaped pattern are approximately 90. The first side of the drain-gate connecting layer 41 a faces the first side of the drain-gate connecting layer 41 b. The second side of the drain-gate connecting layer 41 a faces the second side of the drain-gate connecting layer 41 b. The drain-gate connecting layer 41 a and the drain-gate connecting layer 41 b are approximately point-symmetrical.

[0104] The gate electrode layer 21 a, the gate electrode layer 21 b, the drain-drain connecting layer 31 a, and the drain-drain connecting layer 31 b are disposed in parallel. The gate electrode layers 21 a and 21 b are located between the drain-drain connecting layer 31 a and the drain-drain connecting layer 31 b.

[0105] (b) Structure of Memory Cell

[0106] The structure of the memory cell of the present embodiment is described below. The memory cell of the present embodiment has a structure in which the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are laminated on a field through interlayer dielectrics. The field is a region in which active regions 11, 13, 15, and 17 and element isolation regions 19 are located, as shown in FIG. 2. Bit lines 51 and the like are located in the fourth conductive layer, as shown in FIG. 10. The memory cell of the present embodiment has a structure in which the first conductive layer, the second conductive layer and the third conductive layer shown in FIG. 1 are located on the field shown in FIG. 2. The fourth conductive layer shown in FIG. 10 is located on the third conductive layer.

[0107] 2. Details of Structure of the Present Embodiment

[0108] The details of the structure of the present embodiment are described below with reference to FIGS. 2 to 15 in the order from the lower layers. Note that a line B1-B2 and a line C1-C2 are drawn in FIGS. 2 to 13. FIG. 14 is a view showing the cross section taken along the line B1-B2. FIG. 15 is a view showing the cross section taken along the line C1-C2.

[0109] (a) Field and First Conductive Layer

[0110]FIG. 11 is a plan view showing the field and the first conductive layer. First, the field is described with reference to FIGS. 2, 14, and 15. FIG. 2 is a plan view showing the field. The field includes the active regions 11, 13, 15, and 17 and the element isolation regions 19. The active regions 11, 13, 15, and 17 are formed on the surface of a silicon substrate.

[0111] The active regions 11 have a rectangular shape with a rectangular opening formed therein. In FIG. 2, a plurality of the active regions 11 is arrayed in the X-axial direction. The transfer transistors Q1 and Q2 and the driver transistors Q3 and Q4 shown in FIG. 1 are formed in the active regions 11.

[0112] The active regions 13 resemble the letter H in shape. In FIG. 2, a plurality of the active regions 13 is arrayed in the X-axial direction. The load transistors Q5 and Q6 shown in FIG. 1 are formed in the active regions 13.

[0113] The active regions 15 are formed in every 32 memory cells arrayed in the X-axial direction, for example. A well contact region of an n well is formed in the active region 15. An n well corresponding to 32 memory cells is connected to a VDD line (power supply line) through the well contact region.

[0114] The active regions 17 are formed in every two memory cells arrayed in the Y-axial direction. A well contact region of a p well is formed in the active region 17. A p well corresponding to two memory cells is connected to a VSS line (ground line) through the well contact region.

[0115] The active regions 11, 13, 15, and 17 are isolated from one another by the element isolation regions 19 (thickness: 400 nm, for example). The element isolation regions 19 are formed by STI (Shallow Trench Isolation), for example.

[0116]FIGS. 14 and 15 show the cross sections of the field taken along the line B1-B2 and the line C1-C2 shown in FIG. 2, respectively. The active regions 11 and 13 and the element isolation region 19 are shown in these cross sections.

[0117] The first conductive layer located on the field is described below with reference to FIGS. 3, 11, 14, and 15. FIG. 3 is a plan view showing the first conductive layer. A plurality of the gate electrode layers 21 a and 21 b and a plurality of the sub-word lines 23 (sub-word lines 23 a and 23 b are shown in FIG. 3) are disposed in the first conductive layer. The gate electrode layers 21 a and 21 b and the sub-word lines 23 have a structure in which a salicide layer is formed on a polysilicon layer, for example.

[0118] The gate electrode layers 21 a and 21 b respectively have a linear pattern extending in the Y-axial direction in FIG. 3. A pair of the gate electrode layers 21 a and 21 b is disposed in parallel in each memory cell region. The gate electrode layers 21 a and 21 b become the gate electrodes of the driver transistors Q3 and Q4 and the load transistors Q5 and Q6 shown in FIG. 1. The gate length of the driver transistors Q3 and Q4 is 0.18 μm, for example. The gate length of the load transistors Q5 and Q6 is 0.20 μm, for example.

[0119] The sub-word lines 23 have a linear pattern extending in the X-axial direction in FIG. 3. The sub-word lines 23 are located on the driver transistor side. The sub-word lines 23 are activated or deactivated by a main-word line located in the upper layer. The sub-word lines 23 become the gate electrodes of the transfer transistors (sub-word line 23 a becomes the gate electrodes of the transfer transistors Q1 and Q2 shown in FIG. 1). The gate length of the transfer transistors is 0.24 μm, for example.

[0120]FIGS. 14 and 15 show the cross sections of the first conductive layer taken along the line B1-B2 and the line C1-C2 shown in FIG. 3, respectively. The sub-word lines 23 a and 23 b and the gate electrode layer 21 b are shown in these cross sections.

[0121] Source/drain regions and the like formed in the active regions are described below. n+-type source/drain regions 11 a are formed in the active regions 11, as shown in FIG. 11. A p+-type source/drain regions 13 a are formed in the active regions 13. An n+-type well contact region 15 a is formed in the active region 15. p+-type well contact regions 17 a are formed in the active regions 17.

[0122] The source/drain region is a region which functions as at least either the source or drain. The transfer transistor Q1 and a transfer transistor Q7 which uses the sub-word line 23 b as the gate electrode uses an n-type source/drain region 11 a 2 among the n+-type source/drain regions 11 a. The transfer transistor Q2 and a transfer transistor Q8 which uses the sub-word line 23 b as the gate electrode uses an n+-type source/drain region 11 a 3 among the n+-type source/drain regions 11 a.

[0123] An interlayer dielectric 65 (not shown in FIG. 11) such as a silicon oxide layer is formed to cover the field and the first conductive layer. The interlayer dielectric 65 is planarized using CMP, as shown in FIGS. 14 and 15. A plurality of contact holes 63 for exposing the n+-type source/drain regions 11 a and the like is formed in the interlayer dielectric 65. The contact holes 63 are filled with plugs 61. The plugs 61 are connected to the n+-type source/drain regions 11 a, the p+-type source/drain regions 13 a, the n+-type well contact region 15 a, and the p+-type well contact region 17 a. FIG. 4 is a plan view showing the pattern of the plugs 61. As a material for the plugs 61, tungsten and the like can be used. The diameter at the upper end of the contact holes 63 is 0.30 μm, for example. The diameter at the lower end of the contact holes 63 is 0.24 μm, for example.

[0124] (b) Second Conductive Layer

[0125] The second conductive layer is located on the structure shown in FIG. 11. A plurality of the drain-drain connecting layers 31 a and 31 b, VDD line 33, a plurality of BL (bit line, bit line/) contact pad layers 35 a and 35 b, and a plurality of VSS local interconnects 37 are disposed in the second conductive layer, as shown in FIG. 5. For example, these layers and lines have a structure in which a titanium nitride layer (thickness: 135 nm, for example) is formed on a titanium layer (thickness: 8.5 nm, for example) which is an underlay. The VSS local interconnects 37 also function as contact pad layers.

[0126] The drain-drain connecting layers 31 a and 31 b respectively have a linear pattern extending in the Y-axial direction in FIG. 5. The width of a body section 31 a 3 of the drain-drain connecting layers 31 a is smaller than the width of end sections 31 a 1 and 31 a 2 of the drain-drain connecting layers 31 a. The width of a body section 3 b 3 of the drain-drain connecting layers 31 b is smaller than the width of end sections 31 b 1 and 31 b 2 of the drain-drain connecting layers 31 b. The width of the body sections 31 a 3 and 31 b 3 is a minimum design-rule width. A pair of the drain-drain connecting layers 31 a and 31 b is disposed in each memory cell region. A pair of the gate electrode layers 21 a and 21 b is located between the drain-drain connecting layer 31 a and the drain-drain connecting layer 31 b, as shown in FIG. 1.

[0127] The VSS local interconnects 37 have a linear pattern extending in the Y-axial direction in FIG. 5. The width of the end sections of the VSS local interconnect 37 is greater than the width of the body section. The VSS local interconnects 37 are located between the end section 31 a 2 of the drain-drain connecting layer 31 a and the end section 31 b 2 of the drain drain connecting layer 31 b. The VSS local interconnects 37 extend from this location to between the end section 31 a 2 of the drain-drain connecting layer 31 a and the end section 31 b 2 of the drain-drain connecting layer 31 b in the memory cell located below in FIG. 5. One VSS local interconnect 37 is disposed in two memory cells.

[0128] The BL contact pad layers 35 a function as pad layers for connecting the bit lines to the n+-type source/drain regions 11 a (see FIG. 11). The BL contact pad layers 35 b function as pad layers for connecting the bit lines/ to the n+-type source/drain regions 11 a.

[0129] The BL contact pad layers 35 a are located between the drain-drain connecting layer 31 a of one memory cell and the drain-drain connecting layer 31 a of the memory cell located below in FIG. 5. The BL contact pad layers 35 b are located between the drain-drain connecting layer 31 b of one memory cell and the drain-drain connecting layer 31 b of the memory cell located below in FIG. 5. Each of the BL contact pad layers 35 a and 35 b is disposed in two memory cells.

[0130] The VDD line 33 has a linear pattern extending in the X-axial direction in FIG. 5. The VDD line 33 extends so as to three-dimensionally intersect the n+-type well contact region 15 a (see FIG. 11). The VDD line 33 has branched sections 33 a and 33 b above the n+-type well contact region 15 a.

[0131] The drain-drain connecting layers 31 a and 31 b, the VDD line 33, the BL contact pad layers 35 a and 35 b, and the VSS local interconnects 37 which are disposed in the second conductive layer shown in FIG. 5 are connected to the plugs 61 shown in FIG. 11. These connections are indicated by contact sections 61 m in FIG. 5.

[0132] The cross section of the second conductive layer shown in FIG. 5 taken along the line B1-B2 is shown in FIG. 14. The drain-drain connecting layer 31 b and the BL contact pad layer 35 b are shown in this cross section.

[0133] An interlayer dielectric 71 (not shown in FIG. 5) such as a silicon oxide layer is formed to cover the second conductive layer. The interlayer dielectric 71 is planarized using CMP, as shown in FIGS. 14 and 15. A plurality of through-holes 79 for exposing the drain-drain connecting layers 31 b and the like is formed in the interlayer dielectric 71, as shown in FIG. 14. The through-holes 79 are filled with plugs 75. A through-hole 77 for exposing the gate electrode layer 21 b is formed in the interlayer dielectrics 71 and 65, as shown in FIG. 15. The through-holes 77 are filled with plugs 73. FIG. 12 shows a planar relation between the plugs 73 and 75 and the second conductive layer.

[0134] The plugs 73 are described below. FIG. 6 is a plan view showing the pattern of the plugs 73. The plugs 73 are connected to the gate electrode layers 21 a and 21 b (see FIG. 3). The cross section of the plugs 73 is described below with reference to FIG. 15. The plugs 73 are buried in the through-holes 77 formed through the interlayer dielectrics 65 and 71. In this cross section, the plug 73 is connected to the gate electrode layer 21 b. As a material for the plugs 73, tungsten and the like can be used. The diameter at the upper end of the through-holes 77 is 0.32 μm, for example. The diameter at the lower end of the through-holes 77 is 0.24 μm, for example.

[0135] The plugs 75 are described below. FIG. 7 is a plan view showing the pattern of the plugs 75. The plugs 75 are connected to the drain-drain connecting layers 31 a and 31 b, the branched sections 33 a and 33 b of the VDD line 33, the BL contact pad layers 35 a and 35 b, and the VSS local interconnects 37, as shown in FIG. 12. The cross section of the plugs 75 is described below with reference to FIG. 14. The plugs 75 are buried in the through-holes 79 formed through the interlayer dielectric 71. In this cross section, the plugs 75 are connected to the drain-drain connecting layer 31 b and the BL contact pad layer 35 b. As a material for the plugs 75, tungsten and the like can be used. The diameter at the upper end of the through-holes 79 is 0.30 μm, for example. The diameter at the lower end of the through-holes 79 is 0.24 μm, for example.

[0136] (c) Third Conductive Layer

[0137] The third conductive layer is located on the structure shown in FIG. 12. A plurality of the drain-gate connecting layers 41 a and 41 b, main-word line 43, a plurality of BL contact pad layers 45 a and 45 b, a plurality of VSS contact pad layers 47, and a plurality of VDD contact pad layers 49 are disposed in the third conductive layer, as shown in FIG. 8. These layers and lines have a structure in which a titanium nitride layer, an aluminum-copper alloy layer, a titanium layer, and a titanium nitride layer are laminated in that order, for example.

[0138] Each drain-gate connecting layer 41 a includes a body section 41 a 3 and two end sections 41 a 1 and 41 a 2. The body section 41 a 3 extends in the X-axial direction in FIG. 8. The end section 41 a 1 is bent toward the drain-gate connecting layer 41 b. Each drain-gate connecting layer 41 b includes a body section 41 b 3 and two end sections 41 b 1 and 41 b 2. The body section 41 b 3 extends in the X-axial direction in FIG. 8. The end section 41 b 1 is bent toward the drain-gate connecting layer 41 a. A pair of the drain-gate connecting layers 41 a and 41 b is disposed in each memory cell region.

[0139] The BL contact pad layers 45 a function as pad layers for connecting the bit lines to the n+-type source/drain regions 11 a. The BL contact pad layers 45 b function as pad layers for connecting the bit lines/to the n+-type source/drain regions 11 a. One BL contact pad layer 45 a and one BL contact pad layer 45 b are respectively disposed in two memory cells.

[0140] The VSS con tact pad layers 47 extend in the Y-axial direction in FIG. 8 and have two end sections. The VSS contact pad layers 47 are located between the BL contact pad layers 45 a and the BL contact pad layers 45 b. One VSS contact pad layer 47 is disposed in two memory cells.

[0141] The main-word line 43 extends linearly in the X-axial direction in FIG. 8. The main-word line 43 is located above the VDD line 33 shown in FIG. 5. The VDD contact pad layers 49 are located above the branched sections 33 a and 33 b of the VDD line 33 shown in FIG. 5.

[0142] Each of the end sections 41 a 1 of the drain-gate connecting layers 41 a and the end sections 41 b 1 of the drain-gate connecting layers 41 b is connected to the plugs 73 shown in FIG. 12. These connections are indicated by contact sections 73 m in FIG. 8. Each of the end sections 41 a 2 of the drain-gate connecting layers 41 a, the end sections 41 b 2 of the drain-gate connecting layers 41 b, the BL contact pad layers 45 a and 45 b, the VSS contact pad layers 47, and the VDD contact pad layers 49 is connected to the plugs 75 shown in FIG. 12. These connections are indicated by contact sections 75 m in FIG. 8.

[0143]FIGS. 14 and 15 show the cross sections of the third conductive layer taken along the line B1-B2 and the line C1-C2 shown in FIG. 8, respectively. The drain-gate connecting layers 41 a and 41 b, the BL contact pad layer 45 b, and the main-word line 43 are shown in these cross sections. Hard mask layers 40 formed of a silicon oxide layer are formed on the third conductive layer including these layers and lines. The third conductive layer is patterned using the hard mask layers 40 as masks. This is because it is difficult to pattern the third conductive layer using only a resist as a mask due to miniaturization of memory cells.

[0144] An interlayer dielectric such as a silicon oxide layer is formed to cover the third conductive layer. This interlayer dielectric 85 is planarized using CMP, as shown in FIGS. 14 and 15. Through-holes 83 for exposing the BL contact pad layers 45 a and the like are formed in the interlayer dielectric 85. The through-hole 83 is filled with plug 81. FIG. 13 is a plan view showing this configuration. The plugs 81 are connected to the BL contact pad layers 45 a and 45 b, the VSS contact pad layers 47, and the VDD contact pad layers 49, as shown in FIG. 13. FIG. 9 is a plan view showing the pattern of the plugs 81. As a material for the plugs 81, tungsten and the like can be used. The diameter at the upper end of the through-holes 83 is 0.36 μm, for example. The diameter at the lower end of the through-holes 83 is 0.28 μm, for example.

[0145] (d) Fourth Conductive Layer

[0146] The fourth conductive layer is located on the structure shown in FIG. 13. A plurality of bit lines 51, a plurality of bit lines/53, a plurality of VSS lines 55, and a VDD line 57 are disposed in the fourth conductive layer, as shown in FIG. 10. These lines extend linearly in the Y-axial direction in FIG. 10. The VSS lines 55 are disposed between the bit lines 51 and the bit lines/ 53 at the center of the memory cells. One VDD line 57 is disposed in every 32 memory cells arrayed in the X-axial direction. Each of these lines is connected to the plugs 81 shown in FIG. 13. These connections are indicated by contact sections 81 m in FIG. 10. The bit lines 51 and the like have a structure in which a titanium nitride layer, an aluminum-copper alloy layer, and a titanium nitride layer are laminated in that order, for example.

[0147] The cross section of the fourth conductive layer shown in FIG. 10 taken along the line B1-B2 is shown in FIG. 14. The bit line/53 is shown in this cross section. A signal which compensates a signal flowing through the bit lines 51 flows through the bit lines/53. The details of the structure of the present embodiment are described above.

[0148] The patterns shown in FIGS. 1 to 13 are design patterns. These patterns have corner sections. However, in a pattern actually formed on the semiconductor substrate, a line which specifies the corner sections is curved due to the proximity effect of light.

[0149] 3. Major Effects of Present Embodiment

[0150] Major effects of the present embodiment are described below.

[0151] (1) According to the present embodiment, the size of the SRAM can be reduced. The reasons therefor are as follows. In the present embodiment, information is stored using a flip-flop of the memory cell. A flip-flop is formed by connecting an input terminal (gate electrode) of a first inverter to an output terminal (drain) of a second inverter, and connecting an input terminal (gate electrode) of the second inverter to an output terminal (drain) of the first inverter. Specifically, the flip-flop is formed by cross-coupling the first inverter and the second inverter. In the case of forming a flip-flop using two layers, the inverters can be cross-coupled by forming each of a drain-drain connecting layer for connecting the drains of the inverters and a drain-gate connecting layer for connecting the gate and the drain of the inverters as one conductive layer.

[0152] According to this structure, these conductive layers are formed over regions including a region in which the drain of one inverter is located, a region in which the gate of the other inverter is located, and a region for connecting these regions. Therefore, the conductive layer has a pattern with three ends (for example, a pattern having a branched section in the shape of the letters T or h), or a spiral pattern in which the arms are intricate. For example, Japanese Patent Application Laid-open No. 10-41409 discloses a pattern in the shape of the letter T in FIG. 1. A pattern in the shape of the letter h is disclosed by M. Ishida, et al. in IEDM Technical Digest, 1998, page 203, FIG. 4(b), for example. An example of a spiral pattern is disclosed by M. Ishida, et al. in IEDM Technical Digest, 1998, page 203, FIG. 3(b). These complicated patterns make it difficult to accurately reproduce the shape of a minute pattern in a photoetching process, whereby a desired pattern cannot be obtained. This hinders miniaturization of the memory cell size.

[0153] According to the present embodiment, the gate electrode layers (21 a, 21 b) which become the gates of the CMOS inverters, the drain-drain connecting layers (31 a, 31 b) for connecting the drains of the CMOS inverters, and the drain-gate connecting layers (41 a, 41 b) for connecting the gate of one CMOS inverter to the drain of the other CMOS inverter are respectively formed in different layers. Therefore, a flip-flop is formed using these three layers. Because of this, the pattern of each layer can be simplified (linearly, for example) in comparison with a case of forming a flip-flop using two layers. According to the present embodiment, since the pattern of each layer can be thus simplified, an SRAM of the 0.18 μm generation with a memory cell size of 4.5 μm2 or less can be fabricated, for example.

[0154] (2) According to the present embodiment, parasitic resistance in the source region of the driver transistor can be decreased. Moreover, the pattern of the source region can be simplified. First, terms used to describe the reasons for these advantages (a region between gate electrode layers, an n+-type source region 11 a 1, and a source contact layer 61 a) are described below before describing the reasons.

[0155] These terms are described below with reference to FIG. 11. The region between gate electrode layers is a region between the gate electrode layer 21 a and the gate electrode layer 21 b. Specifically, the region between gate electrode layers is specified by the side of the gate electrode layer 21 a, a line 87 which connects the end section 21 a 1 of the gate electrode layer 21 a to the end section 21 b 1 of the gate electrode layer 21 b, the side of the gate electrode layer 21 b, and a line (not shown) which connects the end section 21 b 2 of the gate electrode layer 21 b to the end section 21 a 2 of the gate electrode layer 21 a. The n+-type source region 11 a 1 is a region which becomes the source of the driver transistors Q3 and Q4 among the n+-type source/drain regions 11 a. The source contact layer 61 a is the plug 61 formed in the source region 11 a 1.

[0156] The above reasons are described below with reference to FIGS. 1 and 11. Assume that the drain-gate connecting layers 41 a and 41 b (see FIG. 13) are located in the same layer as the drain-drain connecting layers 31 a and 31 b. In this structure, the source contact layer 61 a of the driver transistors Q3 and Q4 cannot be located in the region between gate electrode layers. This is because the source contact layer 61 a is in contact with the drain-gate connecting layer 41 b. In order to avoid this, at least part of the source contact layer 61 a is formed outside the region between gate electrode layers (specifically, at least part of the source contact layer 61 a crosses the line 87). This increases the area of the source region 11a1, thereby leading to the following two problems. One of these problems is that parasitic resistance in the source region increases since the source contact layer 61 a is apart from the channels of the driver transistors Q3 and Q4. The other problem is that the pattern of the source region 11 a 1 becomes complicated.

[0157] According to the present embodiment, the drain-gate connecting layer 41 b (see FIG. 13) is located in a layer above the gate electrode layers 21 a and 21 b. Because of this, the source contact layer 61 a can be located in the region between gate electrode layers while preventing the drain-gate connecting layer 41 b from being in contact with the source contact layer 61 a. Therefore, according to the present embodiment, the parasitic resistance of the driver transistors Q3 and Q4 can be decreased, and the pattern of the source region 11 a 1 can be simplified (for example, a pattern with a uniform width such as a rectangular pattern).

[0158] (3) According to the present embodiment, the resistance of the sub-word lines 23 can be decreased while preventing the narrow line effect of silicide of the sub-word lines 23 from occurring. The reasons therefor are described below with reference to FIG. 11. In the case of the above structure in which at least part of the source contact layer 61 a is located outside the region between gate electrode layers, part of the sub-word line 23 a must be curved toward the sub-word line 23 b in order to prevent the sub-word line 23 a from coming in contact with the source contact layer 61 a. According to the present embodiment, since the source contact layer 61 a can be located in the region between gate electrode layers, the pattern of the sub-word lines 23 can be linear while reducing the memory cell size.

[0159] According to the present embodiment, since the sub-word line 23 has a linear pattern, the length of the sub-word lines 23 can be decreased in comparison with a sub-word line of which part of the pattern is curved. Therefore, according to the present embodiment, the resistance of the sub-word line 23 can be decreased. A sub-word line of which part of the pattern is curved tends to be thinned at the curved section, thereby causing the narrow line effect of silicide to occur. According to the present embodiment, since the pattern of the sub-word lines 23 is linear and has not curved section, occurrence of the narrow line effect of silicide caused by the curved section can be prevented, thereby preventing a local increase in the resistance of the sub-word lines 23 due to the narrow line effect of silicide. In the present embodiment, the word line consists of the sub-word lines 23 and the main-word line 43. The word line may have a one-layer structure consisting of only the sub-word lines 23.

[0160] (4) According to the present embodiment, the number of memory cells which can be formed on one chip can be increased. The reasons therefor are as follows. In the case of sub-word lines having a pattern with a curved section, as described above, there is no room for forming a well contact region between the sub-word lines due to the curved section. Therefore, the well contact region must be formed in every set of a predetermined number of memory cells by providing a space therefor. However, the memory cells are not formed in these spaces, whereby the number of memory cells which can be formed in one chip decreases equivalent to the number of these dead spaces.

[0161] According to the present embodiment, since the sub-word lines 23 have a linear pattern, as shown in FIG. 11, the p+-type well contact region 17 a can be located between the sub-word line 23 a and the sub-word line 23 b. As a result, according to the present embodiment, the number of memory cells which can be formed on one chip can be increased.

[0162] (5) The p+-type well contact region 17 a is formed in every two memory cells arrayed in the Y-axial direction. The active region 15 which becomes the well contact region of the n well is formed in every 32 memory cells arrayed in the X-axial direction, for example. Therefore, latchup can be prevented according to the present embodiment, as described above.

Classifications
U.S. Classification257/296, 257/E27.099
International ClassificationH01L21/8244, H01L27/11
Cooperative ClassificationY10S257/903, H01L27/1104
European ClassificationH01L27/11F
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