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Publication numberUS20010038542 A1
Publication typeApplication
Application numberUS 09/780,607
Publication dateNov 8, 2001
Filing dateFeb 12, 2001
Priority dateFeb 11, 2000
Also published asDE60101694D1, DE60101694T2, EP1128535A2, EP1128535A3, EP1128535B1, US6421257
Publication number09780607, 780607, US 2001/0038542 A1, US 2001/038542 A1, US 20010038542 A1, US 20010038542A1, US 2001038542 A1, US 2001038542A1, US-A1-20010038542, US-A1-2001038542, US2001/0038542A1, US2001/038542A1, US20010038542 A1, US20010038542A1, US2001038542 A1, US2001038542A1
InventorsStephen MacKay, Stephen Berry
Original AssigneeMackay Stephen John, Stephen Berry
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Power converter control loop
US 20010038542 A1
Abstract
An apparatus for and method of control of a switch (102) in an electrical power converter (100) using pulse width modulation to regulate output voltage (112) and current. The method allows precise output voltage regulation to be achieved whilst accurately controlling the proportion of load-current supplied by multiple modules connected in parallel. A ramped waveform (408), consisting of a component representing the instantaneous current and a component representing the input voltage applied since the switch (102) switched on in the current PWM cycle, is compared with an error signal (406) to determine the width of each PWM pulse.
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Claims(14)
1. An apparatus for applying a pulse width modulated signal to a power supply unit, the apparatus including:
means for providing an input demand signal;
an error amplifier means for generating an error signal in accordance with the input demand signal;
a waveform generator means for generating a ramped voltage waveform;
an oscillator means for providing a clock signal to the waveform generator means; and
a phase comparator means for comparing the ramped voltage waveform with the error signal and generating the pulse width modulated signal.
2. An apparatus according to
claim 1
, wherein the ramped voltage waveform has a current feedback component and a voltage feed-forward component.
3. An apparatus according to claims 1 or 2, wherein the phase comparator means generates the pulse width modulated signal in accordance with the clock signal, the pulse width modulated signal cycling between an ‘ON’ state and an ‘OFF’ state.
4. An apparatus according to
claim 3
, wherein the onset of each ‘ON’ state is arranged to coincide with the onset of each pulse in the clock signal.
5. An apparatus according to
claim 4
, wherein the onset of each ‘OFF’ state is controlled by the result of the comparison between the ramped voltage waveform with the error signal.
6. An apparatus according to any one of
claims 1
to
5
, wherein the waveform generator means includes a capacitor and a voltage to current converter.
7. An apparatus according to any one of the preceding claims, wherein the input demand signal is modified by a feedback correction signal.
8. A method for generating a pulse width modulated signal which regulates both output voltage and output current in a power converter, including the steps of:
a) providing an input demand signal;
b) generating an error signal in accordance with the input demand signal;
c) providing a clock signal;
d) generating a ramped voltage waveform in accordance with the clock signal;
e) comparing the ramped voltage waveform with the error signal; and
f) generating the pulse width modulated signal in accordance with the result of the comparison step e).
9. A method according to
claim 8
, wherein the pulse width modulated signal generated in step f) is generated in accordance with the clock signal, the pulse width modulated signal cycling between an ‘ON’ state and an ‘OFF’ state.
10. A method according to
claim 9
, wherein step f) further includes arranging the onset of each ‘ON’ state to coincide with the onset of each pulse in the clock signal.
11. A method according to
claim 10
, wherein step f) further includes arranging the onset of each ‘OFF’ state to be controlled by the result of the comparison step f).
12. A method according to any one of
claims 8
to
11
, wherein step d) includes summing a current feedback component and a voltage feed-forward component.
13. A method according to any one of
claims 8
to
12
, wherein step b) further includes modifying the input demand signal in accordance with a feedback correction signal.
14. An apparatus substantially as hereinbefore described with reference to the accompanying FIG. 4.
Description

[0001] The present invention relates to a power converter control loop. More particularly the invention relates to a method of control for electrical power supply units, each unit having a plurality of power converter modules. The method allows precise output voltage regulation to be achieved at the same time as accurately controlling the proportion of load current supplied by the power converter modules connected in parallel.

[0002] The method may be implemented in any electrical power converter unit using pulse width modulation (PWM) to regulate output voltage or current and is suitable for any application where the outputs of multiple power converter modules are connected in parallel. A PWM signal controls the state of a semiconductor switch, for example, a power transistor, an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gate tun-off thyristor.

[0003] Voltage feed-forward is a prior art method of PWM regulation for achieving an accurate output voltage. A ramped waveform is fed-forward through a PWM comparator which in tun controls the width of each PWM pulse. Voltage feed-forward does not, however, permit current sharing of multiple modules.

[0004] Parallel connections are desirable for many reasons. Connecting multiple power converter modules in parallel increases the maximum output power beyond that available from a single module, provides redundancy in the event of failure of one or more modules and reduces costs by allowing the use of smaller, standard components.

[0005] Current mode control is a prior art method of PWM regulation for achieving accurate current control that enables multiple modules to be connected in parallel within a power converter unit. Current mode power converter units themselves nay be set in parallel to one another.

[0006] A known drawback of current mode power conversion is the existence of instability when the ratio of PWM ‘ON’-time to ‘OFF’-time, the duty cycle, exceeds 50%. The accepted technique for stabilising current mode control schemes is known as ‘slope compensation’ in which a compensating voltage signal is summed with a reference voltage signal used to generate the PWM signal. Nevertheless, slope compensation reduces open loop voltage accuracy (the voltage accuracy in the absence of feedback) and subsequently closed loop voltage accuracy (the voltage accuracy with feedback).

[0007] It is therefore an object of the invention to obviate or at least mitigate the aforementioned problems.

[0008] In accordance with the present invention, there is provided an apparatus for applying a pulse width modulated signal to a power supply unit, the apparatus including:

[0009] means for providing an input demand signal;

[0010] an error amplifier means for generating an error signaling accordance with an input demand signal;

[0011] a waveform generator means for generating a ramped voltage waveform;

[0012] an oscillator means for providing a clock signal to the ramped voltage waveform generator;

[0013] a phase comparator means, for comparing the ramped voltage waveform with the error signal and generating the pulse width modulated signal.

[0014] Preferably, the ramped voltage waveform has a current feedback component and a voltage feed-forward component.

[0015] Advantageously, the phase comparator means generates the pulse width modulated signal in accordance with the clock signal, the pulse width modulated signal cycling between an ‘ON’ state and an ‘OFF’ state.

[0016] The onset of each ‘ON’ state nay be arranged to coincide with the onset of each pulse in the clock signal.

[0017] The onset of each ‘OFF’ state is preferably controlled by the result of the comparison between the ramped voltage waveform with the error signal.

[0018] The waveform generator means preferably includes a capacitor and a voltage to current converter.

[0019] The input demand signal may be modified by a feedback correction signal.

[0020] In accordance with a further aspect of the present invention, there is provided a method for generating a pulse width modulated signal which is regulates both output voltage and output current in a power converter, including the steps of:

[0021] a) providing an input demand signal.

[0022] b) generating an error signal in accordance with the input demand signal;

[0023] c) providing a clock signal,

[0024] d) generating a ramped voltage waveform in accordance with the clock signal;

[0025] e) comparing the ramped voltage waveform with the error signal; and

[0026] f) generating the pulse width modulated signal in accordance with the result of the comparison step e).

[0027] The pulse width modulated signal generated in step f) is preferably generated in accordance with the clock signal, the pulse width modulated signal cycling between an ‘ON’ state and an ‘OFF’ state.

[0028] Step f) may further include arranging the onset of each ‘ON’ state to coincide with the onset of each pulse in the clock signal.

[0029] Advantageously, step f) also includes arranging the onset of each ‘OFF’ state to be controlled by the result of the comparison step i).

[0030] Preferably, step d) includes summing a current feedback component and a voltage feed-forward component.

[0031] Step b) may filer include modifying the input demand signal in accordance with a feedback correction signal.

[0032] The invention is particularly suitable for applications where a power-converter unit supplies highly inductive, capacitive or non-linear loads. The use of a simple error integrator control loop compensates for the phase shifts in the output to input transfer functions which are inevitable at certain frequencies in a power supply having inductive and capacitive components. Power converters having only resistor loads are simpler to compensate for at higher frequencies since they introduce no phase shift. Optimum phase margin and gain margin are thus achieved without the need for, or performance degradation introduced by, additional gain/phase shaping.

[0033] For a better understanding of the present invention, reference will now be made, by way of example only, to the accompanying drawings in which:

[0034]FIG. 1 shows a schematic circuit diagram of a buck converter;

[0035]FIG. 2 shows a schematic circuit diagram of a voltage mode control apparatus;

[0036]FIG. 3 shows a schematic circuit diagram of a current mode control apparatus;

[0037]FIG. 4 shows a schematic diagram of a dual current-voltage regulating apparatus according to the present invention; and

[0038]FIG. 5 shows a graphical representation of a typical loop gain frequency profile for the feedback loop in the present invention.

[0039] A buck power converter 100 has the basic structure shown in FIG. 1. A series switch S1 102 chops the input voltage 116 under the control of a PWM signal 118 and applies the now pulsed input voltage across a transformer 110 to an averaging LC filter and rectifier 120 having an inductor L1 104 connected in series with a load 114 and a capacitor C1 106 connected in parallel with said load 114. The LC filter 120 is needed to filter variations in the output voltage caused by the PWM switching of the series switch 102. A diode 108 serves to complete a circuit in the ‘OFF’-time of the switch S1. It will be noted that such a converter will produce an output voltage which is always lower than the input voltage level.

[0040] Voltage mode control of a buck power converter is illustrated in FIG. 2. The control circuit 200, which generates the PWM signal applied to the switch S1, includes an error amplifier 204, a PWM phase comparator 210, an oscillator 220 and a logic means 214. The error amplifier 204 generates a voltage error signal 206. The voltage error signal 206 is continually compared with a ramp waveform 208 by the PWM comparator 210. The PWM comparator 210 outputs a pulse 212 when the ramp waveform 208 has an amplitude equal to the voltage error signal 206. The output pulse 212 from the PWM comparator 210 corresponds to the end of the ‘ON’-time of a latched signal 216 produced by the logic means 214. The onset of the ‘ON’-time of the latched signal 216 coincides with a clock signal 222 produced by an oscillator 220. The latched signal 216 is applied to the switch S1 of the buck converter circuit 100. Thus the duration of the ‘ON’-time corresponds to a portion of the cycle in which the p waveform 208 is less than the voltage error signal 206.

[0041] The oscillator 220 also applies a pulse train 224 to a capacitor 226. In the absence of an oscillator pulse 224, the capacitor discharges and generates the ramp waveform 208.

[0042] Voltage regulation is achieved by feeding back the output voltage signal VOUT 112 to the error amplifier 204. The output voltage signal 112 is compared with a reference voltage signal 202 by the error amplifier 204. Voltage feed forward regulation may additionally be achieved by controlling the current charging the capacitor 226 inn accordance with the supply voltage. The result of the comparison is the error voltage signal 206.

[0043]FIG. 3 illustrates current mode control of a buck power converter 100. Again, the control circuit 300 which generates the PWM signal applied to the switch S1 includes an error amplifier 304, a PWM phase comparator 310, an oscillator 320 and a logic means 314. These components are however connected in a distinct manner.

[0044] As in voltage mode, the error amplifier 304 generates a voltage error signal 306 and the voltage error signal 306 is continually compared with a signal derived from the output inductor current 308 by the PWM comparator 310. The PWM comparator 310 outputs a pulse 312 the instant the inductor current signal 308 is equal to the voltage error signal 306. The output 312 from the PWM comparator 310 corresponds to the end of the ‘ON’-time of a latched signal 316 produced by the logic means 314 and applied to the switch S1 of the buck converter circuit. The onset of the ‘ON’-time of the latched signal 316 is under the control of a clock signal 322 produced by all oscillator 320.

[0045] As before, the output voltage signal 112 is compared with a reference voltage signal 302 by the error amplifier 304. The result of the comparison is the error voltage signal 306.

[0046] Crucial to current mode regulation is the feedback of a voltage signal 308 corresponding to inductor current detected at the switch S1 as the inductor signal VS 122. The slope of the inductor current signal 308 responds immediately to any line voltage changes. Thus regulation of the current flowing in the buck converter 100 is achieved by feedback of both output voltage 112 and the inductor current signal 308.

[0047] As mentioned above, slope compensation is required to stabilise the control loop for large ramps in duty cycle.

[0048] The power converter of the present invention combines features of both current and voltage modes.

[0049]FIG. 4 shows a basic circuit layout according to the present invention. As before, a switch S1102 is controlled by a PWM signal 118 and an LC averaging filter 120 removes any variations caused by the PWM signal 118.

[0050] It will be noted that, for simplicity, the switching power supply 100 shown being controlled by the PWM signal 118 is a buck regulator and not a converter. A buck converter as shown in FIG. 1 has an additional transformer between the control circuit and the filter circuit 120 but otherwise operates identically to a buck regulator. A practical buck converter often includes a means for converting electrical feedback signals into optical signals in the filter circuit 120 and corresponding means for converting the optical feedback signals into electrical signals for use by the control circuit. By addition of an optical stage in the feedback of signals to the control circuit, the isolation of the filter circuit 120 from the control circuit can be achieved.

[0051] In an operating control circuit, oscillator 430 generates a clock signal 434. The clock signal 434 is applied as a first input signal to a logic means 426 and, via a clock diode 424, to a ramp capacitor C1, 442. The logic means 426 also receives a second input signal 432 from the PWM comparator 422 and acts as a latch for each PWM pulse.

[0052] In FIG. 4, each PWM pulse is inverted at an inverter gate 428 and the resulting PWM pulse 436 is applied to the switch S1 102. The PWM comparator, the clock diode 424, the logic means 426 and the inverter gate 428 may all be provided upon a single integrated PWM circuit 420.

[0053] The input voltage for both the LC filter 120 and a voltage to current converter 440 is supplied by a voltage source 450. A current transformer 452, a resistor burden 444 and a diode 446 form a current loop 454. The current transformer 452 boosts the current across the current transformer burden 444 in the current loop 454.

[0054] Free-running oscillator pulses 434 start each PWM cycle and reset the voltage across the ramp capacitor C1, 442 The PWM ‘ON’-time is terminated when a ramped waveform 408 VRAMP becomes equal to an error integrator output voltage 406 VE.

[0055] The ramped waveform 408 is generated by superimposing a signal from the voltage to current converter 440 and the voltage across the ramp capacitor C1 442. VRAMP is thus a time-varying signal consisting of a component representing the instantaneous current VR/sense summed with a component representing the integral of VIN 116 from the start of each PWM cycle.

V RAMP(t)= V R/sense+{fraction (1/t)}∫

V IN dt

[0056] The error amplifier output voltage 406 VE is generated in a similar manner to that in voltage or current mode. An input voltage demand signal 402 is input into an error integrator 410. The error integrator 410 comprises an amplifier 412 and a capacitor 414 in parallel, The output of the error integrator 410, the error integrator output voltage 406 VE, is applied to one input of a PWM phase comparator 422.

[0057] The PWM phase comparator 422 compares the ramped waveform 408 VRAMP and the error integrator output voltage 406 VE thus controlling the end of the PWM ‘ON’-time in each PWM cycle.

[0058] Typically, the input voltage demand signal 402 is varied by the user in a range from 0 to −5V which corresponds to output voltage in the range 0 to 100%. The output voltage feedback signal 112 is attenuated to produce 5V at 100% output voltage. The current feedback signal 454 scaled to produce 1V at 100% full-load current. The capacitor 414 of the error amplifier integrator 410 is chosen so that the integrator 410 has unity loop-gain at less than 25% of the PWM switching frequency.

[0059] With the error amplifier integrator output voltage 406 in the range 0 to 5V comprising: the current loop voltage in the range 0 to 1V; and voltage at capacitor C1, VC1, in the range 0 to 4V. The error amplifier integrator output voltage 406 ramps down by 25%, i.e. 1.25V, during the ‘ON’-time in each PWM cycle. The error amplifier integrator output amplitude at PWM frequency must be greater than 0.5 volts to provide the 50% ‘slope compensation’ needed to ensure closed-loop stability of the 1V current mode proportion of VRAMP at duty cycles greater than 50%.

[0060] The oscillator low period is arranged to be long enough to allow the ramp capacitor C1 442 to fully discharge but short enough to avoid the need for additional circuitry at low duty cycles.

[0061] The present invention achieves both maximum voltage accuracy and current-sharing accuracy at all frequencies from DC up to 25% of switching frequency and without the need for any additional large or expensive power components. In essence, the lower the frequency of a signal passing across the error amplifier integrator 410, the greater the averaging effect of the integrator.

[0062]FIG. 5 illustrates the above effect: if the oscillator signal had an inherent switching accuracy (at a switching frequency of 20 kHz) of ±1% and provided the loop gain is arranged to be unity at 25% of switching frequency, the switching accuracy at 5 kHz is also ±1% but at 500 Hz the switching accuracy is up to ±0.1%: a real increase in accuracy is seen for lower frequency signals. It should be noted that while the gain effectively falls to zero for frequencies above the switching frequency, it is possible that two signals having frequencies above the switching frequency can still have an effect at lower frequencies. When the two signals have a small frequency difference between them they can interfere to cause low frequency beats.

[0063] It will be readily understood that the present invention operates with any type of buck-derived power converter or regulator circuit topology including single-ended, push-pull, half bridge, fit-bridge (or H-bridge) and soft-switching configurations. Where necessary, the PWM signal may control the behaviour of a plurality of switches.

[0064] Extra circuitry may be added to reset ramp capacitor C1 442 as soon as the phase-comparator terminates the PWM pulse and provide a minimum off-time.

[0065] It will be readily accepted that certain additional components will be necessary to realise a practical circuit, for example, a reset circuit for current transformer 452 core in implementations where a half-bridge is used.

[0066] One advantage of the inventive device is that proprietary PWM integrated circuits may be used to integrate various circuit functions.

[0067] A voltage feed-forward signal may be taken from the output voltage before the filter 120 in order to remove errors introduced by switch S1 as well as transformer (and when present rectifier) losses. Removal of these errors requires a further high-speed differential amplifier.

[0068] Additional closed loop feedback may be needed from VOUT 112 either locally or at the load.

Classifications
U.S. Classification363/41
International ClassificationH02M3/156
Cooperative ClassificationH02M3/156
European ClassificationH02M3/156
Legal Events
DateCodeEventDescription
Feb 21, 2014REMIMaintenance fee reminder mailed
Dec 17, 2009FPAYFee payment
Year of fee payment: 8
Aug 12, 2008ASAssignment
Owner name: SIEMENS AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIEMENS MAGNET TECHNOLOGY LIMITED;REEL/FRAME:021371/0471
Effective date: 20080716
Jul 7, 2008ASAssignment
Owner name: SIEMENS MAGNET TECHNOLOGY LIMITED, UNITED KINGDOM
Free format text: CHANGE OF NAME;ASSIGNOR:OXFORD MAGNET TECHNOLOGY LIMITED;REEL/FRAME:021194/0223
Effective date: 20040630
Jan 12, 2006FPAYFee payment
Year of fee payment: 4
May 11, 2001ASAssignment
Owner name: OXFORD MAGNET TECHNOLOGY LIMITED, UNITED KINGDOM
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MACKAY, STEPHEN JOHN;BERRY, STEPHEN;REEL/FRAME:011797/0015
Effective date: 20010315
Owner name: OXFORD MAGNET TECHNOLOGY LIMITED EYNSHAM, WITNEY,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MACKAY, STEPHEN JOHN /AR;REEL/FRAME:011797/0015