|Publication number||US20010038566 A1|
|Application number||US 09/773,221|
|Publication date||Nov 8, 2001|
|Filing date||Jan 31, 2001|
|Priority date||Jan 31, 2000|
|Also published as||DE10004109A1, DE10004109C2, EP1124231A1, US6388944|
|Publication number||09773221, 773221, US 2001/0038566 A1, US 2001/038566 A1, US 20010038566 A1, US 20010038566A1, US 2001038566 A1, US 2001038566A1, US-A1-20010038566, US-A1-2001038566, US2001/0038566A1, US2001/038566A1, US20010038566 A1, US20010038566A1, US2001038566 A1, US2001038566A1|
|Inventors||Peter Schrogmeier, Stefan Dietrich, Torsten Partsch, Thomas Hein, Patrick Heyne, Thilo Marx|
|Original Assignee||Peter Schrogmeier, Stefan Dietrich, Torsten Partsch, Thomas Hein, Patrick Heyne, Thilo Marx|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (8), Classifications (11), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 The invention relates to a memory component having a cell array with a plurality of memory cells configured such that a number of bits are synchronously accessible.
 In the case of memory components which are clocked synchronously, a specific number of stored bits are to be accessed simultaneously. As a rule, the number is eight, sixteen or thirty-two bits. In this context, “simultaneously” means that all bits which are to be read synchronously have to be brought to an output of the memory component within a predefined, fixed period of time, and from the output they are transferred further as an “information packet.” This period of time is typically in the range of nanoseconds.
 In an electronic data processing system, such as e.g. a computer, the maximum clock frequency is limited by that unit which requires the maximum time for performing a process step. Thus, no unit is allowed to require significantly more time than the rest of the units for performing a process step. This means, inter alia, that the access time to a desired number of bits in a memory chip must not exceed the time of one clock cycle. If this were the case, then an additional clock cycle would be required until the information packet were conveyed further, since the information packet waiting at the output of the memory chip can only be conveyed further clock cycle by clock cycle. The processing units which are coupled to the memory component and require this information packet in order to perform their work would each have their work interrupted for the length of one clock cycle.
 The access time required both when reading and when storing bits is thus a parameter whose value should be as small as possible.
FIG. 3 shows a schematic structure of a cell array 1 of a memory component according to the prior art. The cell array 1 includes a plurality of cell array strips 2 which are separated from one another by local data line strips 3 which are parallel to the cell array strips 2 and are adjacent on both sides. The cell array strips 2 essentially include a plurality of memory cells 7. The local data line strips 3 have a plurality of local data lines 4. The cell array 1 additionally has output amplifiers 6 to which a main data line 5 is in each case connected. This main data line 5 runs perpendicularly both to the cell array strips 2 and to the local data line strips 3.
 If a specific memory cell 7 is to be accessed, then it must be activated. To that end, a plurality of word lines 11 are provided, which run parallel to the local data line strips 3 and within a specific cell array strip 2. Furthermore, a plurality of column lines 12 are provided, which run parallel to the main data lines 5 and intersect the word lines 11 at crossover points 13. Each memory cell 7 can be assigned to one of the crossover points 13 in an unambiguous manner. The activation of a crossover point 13 takes place through the activation of the corresponding word and column line 11, 12. If the crossover point 13 is activated, then the assigned memory cells 7 can be accessed.
FIG. 5 shows a schematic illustration of the path covered by a bit when it is read from a memory component or written to a memory component. Once a bit stored in a memory cell 7 has been activated via a word line 11 and a column line 12 (cf. FIG. 4) it is brought via a bit line 8 to a preamplifier 9, which is provided on a local data line 4 of a local data line strip 3 and constitutes a connecting element between the bit line 8 and the local data line 4. The bit amplified by the preamplifier then passes via the local data line 4 to a switch 10, which lies on a main data line 5 and constitutes a connecting element between the local data line 4 and the main data line 5. This switch 10 forwards the signal via the main data line 5 to an output amplifier 6, which raises the signal to a desired output level and subsequently forwards it to an output of the memory chip.
 In the case of Synchronous Dynamic Random Access Memory chips (SDRAMS) which synchronously access sixteen bits, it is customary to assign in each case four memory cells 7 to a specific crossover point 13 (cf. FIG. 4). Thus, if a crossover point 13 is selected by way of the activation of the corresponding word line 11 and/or column line 12, then the associated four memory cells 7 are activated and the bits stored therein are brought via the bit line 8 to the respective preamplifiers 9, or bits to be stored are delivered via the preamplifiers 9 to the memory cells 7.
 Thus, four bits are read or written through the activation of a specific crossover point 13. This means that in the event of an access to sixteen bits, precisely four crossover points 13, i.e. precisely two word lines 11 and two column lines 12, have to be activated.
 In order to avoid data collisions on the bit lines and the local data lines, care must be taken, therefore, to ensure that two adjacent cell array strips 2 or two word lines 11 within the same cell array strip 2 are never activated simultaneously. This is indicated in FIG. 3 by the arrow brackets A and B, which each represent one of the possible combinations of activated cell array strips 2.
 It is accordingly an object of the invention to provide a memory component which overcomes the above-mentioned disadvantages of the heretofore-known memory components of this general type and which minimizes the access time to a desired number of bits in the event of a synchronous access.
 With the foregoing and other objects in view there is provided, in accordance with the invention, a memory component, including:
 a cell array having a plurality of memory cells disposed in the cell array, the cell array being configured such that n bits are synchronously accessible in a synchronous memory access, n being an integer number;
 a plurality of bit lines connected to respective ones of the memory cells;
 a plurality of preamplifiers connected to respective ones of the bit lines;
 a plurality of local data lines connected to respective ones of the preamplifiers;
 a plurality of switches connected to respective ones of the local data lines;
 a plurality of main data lines connected to respective ones of the switches;
 a plurality of output amplifiers connected to respective ones of the main data lines; and
 the switches being disposed such that a longest possible propagation time of a bit in given ones of the local data lines used for the synchronous memory access is shorter, the further away from associated ones of the output amplifiers the given ones of the local data lines are relative to further ones of the local data lines which are simultaneously required for the synchronous memory access.
 In other words, the object of the invention is achieved with a memory module having a plurality of memory cells disposed within a cell array, the cells are in each case connected via a bit line to a preamplifier and, from the latter, via a local data line and a main data line connected to the local data line by a switch, to an output amplifier, a number of n bits being accessed synchronously, wherein switches are disposed in such a way that the longest possible propagation time of a bit in the local data lines is shorter, the further away from the output amplifiers the local data lines are relative to the other local data lines which are simultaneously required in the event of a synchronous memory access.
 In accordance with another feature of the invention, the cell array is formed of a plurality of cell array strips; and local data line strips are disposed parallel to one another and adjacent on both sides of the cell array strips such that the cell array strips are separated from one another by the local data line strips.
 In accordance with yet another feature of the invention, the local data line strips include at least four of the local data lines.
 In accordance with a further feature of the invention, the main data lines are disposed perpendicular to the cell array strips.
 In accordance with another feature of the invention, the cell array strips define an axis which is centrally centered with respect to the cell array strips and parallel to the main data lines; and in each case two of the switches which lie on a same one of the local data line strips are disposed at a substantially identical distance from the axis.
 In accordance with another feature of the invention, the cell array is configured such that eight, sixteen, thirty-two or sixty-four bits are accessed in the synchronous memory access.
 In accordance with yet another feature of the invention, the plurality of output amplifiers are eight, sixteen, thirty-two or sixty-four output amplifiers.
 Each bit stored in a memory cell traverses, once it has been activated, an individual path to an output amplifier assigned to the bit. This path is principally composed of a path portion covered by the bit on a local data line strip, and of a path portion covered by the bit on a main data line. This means that the individual paths of the individual bits have six different path lengths depending on the position of the memory cells, of the associated switches and thus of the associated output amplifiers. The propagation times of the individual bits from the memory cell as far as the output amplifier differ, therefore. Since, in the event of a synchronous memory access, the bits brought to an output of the memory component can only be conveyed further when all of the bits are present, the bit having the longest propagation time is crucial for the access time.
 The central idea of the invention is to configure the individual paths of the individual bits in such a way as to avoid individual paths having a long propagation time. For compensation, the path length of the individual paths having a short propagation time is increased. The largely equal distribution of the number of individual paths having short, medium and long propagation times is thus redistributed into a small number of individual paths having short and long propagation times and a high number of individual paths having a medium propagation time.
 A further feature of the invention is that the configuration of the individual parts is preferably implemented by way of the configuration or placement of the switches on the local data line strips which are formed of local data lines. The length of the individual path covered by the bit on the local data line strip can be varied in a targeted manner by way of the position of the switches. In this case, the placement or positioning of the switches on a local data line strip which is farthest away from the output amplifiers relative to the other local data line strips which are simultaneously required for a synchronous memory access is configured in such a way that these switches lie as far as possible in the middle of the local data line strip. This makes it possible to avoid maximal signal propagation distances and thus maximal propagation times on the local data lines since at most half a length of the local data line strip then has to be traversed.
 Other features which are considered as characteristic for the invention are set forth in the appended claims.
 Although the invention is illustrated and described herein as embodied in a memory component with short access time, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
 The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
FIG. 1 is a schematic plan view of an embodiment of the memory component according to the invention;
FIG. 2 is a schematic plan view of an embodiment of a memory component according to the prior art;
FIG. 3 is a schematic plan view of the structure of a memory component according to the prior art;
FIG. 4 is a schematic view of a detail of FIG. 3 illustrating memory cells at two crossover points; and
FIG. 5 is a circuit diagram illustrating a path of a bit from a memory cell to an output amplifier.
 Referring now to the figures of the drawings in detail, in which same reference symbols are used for corresponding structural parts, and first, particularly, to FIG. 1 thereof, there is shown a particularly preferred embodiment of a memory component according to the invention. This memory component is configured for a synchronous access to sixteen bits. In each case two switches 10 which lie on an identical local data line strip 14, 15, 16, 17, 18 are at an identical distance 20 from an axis 19 of the memory component. The further away from the output amplifiers 6 the local data line strips 14, 15, 16, 17, 18 are, the nearer to the axis 19 are the outer switches 10 which lie on the local data line strips 14, 15, 16, 17, 18. A V-shaped configuration structure of the switches 10 is thus produced.
 This configuration structure may, for example, be repeated periodically with increasing distance from the output amplifiers 6 and can also be transferred to memory components having synchronous access to more or fewer than sixteen bits, for example thirty-two bits.
 Since the switches 10 which lie on the local data line strip 14 have the longest signal propagation time with respect to the main data line 5, the maximum signal propagation distance 21 therefor must be kept as small as possible. This is achieved by the switches 10 being centered in the middle with respect to the cell array strips 2 on the local data line strips 14. Maximum signal propagation distances 21 which are longer than half the length of a local data line strip, as shown for example in FIG. 2, are thus avoided. As a result, the maximum propagation time of a bit is reduced, which makes it possible to have a higher clock rate for the memory chip.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6711091||Sep 27, 2002||Mar 23, 2004||Infineon Technologies Ag||Indication of the system operation frequency to a DRAM during power-up|
|US6809914||May 13, 2002||Oct 26, 2004||Infineon Technologies Ag||Use of DQ pins on a ram memory chip for a temperature sensing protocol|
|US6873509||May 13, 2002||Mar 29, 2005||Infineon Technologies Ag||Use of an on-die temperature sensing scheme for thermal protection of DRAMS|
|US6952378||Jan 25, 2005||Oct 4, 2005||Infineon Technologies Ag||Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations|
|US6985400||Sep 30, 2002||Jan 10, 2006||Infineon Technologies Ag||On-die detection of the system operation frequency in a DRAM to adjust DRAM operations|
|US7362650||Mar 30, 2006||Apr 22, 2008||Infineon Technologies Ag||Memory arrangement having a plurality of RAM chips|
|US20050122832 *||Jan 25, 2005||Jun 9, 2005||Infineon Technologies North America Corp.||On-die detection of the system operation frequency in a DRAM to adjust DRAM operations|
|WO2005038811A1 *||Sep 17, 2004||Apr 28, 2005||Michael Hausmann||Memory arrangement comprising a plurality of ram modules|
|International Classification||G11C11/401, H01L27/10, G11C11/409, G11C11/407, G11C7/18, G11C8/00, G11C7/00, G11C7/12|
|Jun 18, 2001||AS||Assignment|
|Sep 17, 2002||CC||Certificate of correction|
|Nov 10, 2005||FPAY||Fee payment|
Year of fee payment: 4
|Nov 9, 2009||FPAY||Fee payment|
Year of fee payment: 8
|May 28, 2010||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG,GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHROGMEIER, PETER;DIETRICH, STEFAN;PARTSCH, TORSTEN;ANDOTHERS;SIGNING DATES FROM 20010316 TO 20010918;REEL/FRAME:024456/0406
|Jun 14, 2010||AS||Assignment|
Owner name: QIMONDA AG,GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:024626/0001
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|May 8, 2015||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
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Effective date: 20141009