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Publication numberUS20010039119 A1
Publication typeApplication
Application numberUS 09/447,309
Publication dateNov 8, 2001
Filing dateNov 22, 1999
Priority dateNov 26, 1998
Also published asEP1005069A2, EP1005069A3, US6352927, US20020037650
Publication number09447309, 447309, US 2001/0039119 A1, US 2001/039119 A1, US 20010039119 A1, US 20010039119A1, US 2001039119 A1, US 2001039119A1, US-A1-20010039119, US-A1-2001039119, US2001/0039119A1, US2001/039119A1, US20010039119 A1, US20010039119A1, US2001039119 A1, US2001039119A1
InventorsJun Kishimoto
Original AssigneeJun Kishimoto
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor wafer and method for fabrication thereof
US 20010039119 A1
Abstract
There is disclosed a semiconductor wafer obtained, at least, by removing a mechanical damage layer by etching both surfaces of the wafer, flattening one of the surfaces by a surface-grinding means, polishing both of the surfaces, and then subjecting a front surface of the wafer to a finishing mirror-polishing when defining the surface subjected to surface-grinding as a back surface of the wafer, and a method for fabricating it. There can be provided a method for fabricating a semiconductor wafer wherein grinding striations which remain on a semiconductor wafer even when double side polishing and finishing mirror-polishing are conducted after a conventional step of surface-grinding of the front surface or the both surfaces, are eliminated to improve quality of the front surface of the wafer, and the back surface having a quality suitable for the device process can be obtained, and a semiconductor wafer obtained thereby.
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Claims(5)
What is claimed is:
1. A semiconductor wafer obtained, at least, by removing a mechanical damage layer by etching both surfaces of the wafer, flattening one of the surfaces by a surface-grinding means, polishing both of the surfaces, and then subjecting a front surface of the wafer to a finishing mirror-polishing when defining the surface subjected to surface-grinding as a back surface of the wafer.
2. A method for fabricating a semiconductor wafer comprising at least slicing a wafer from a semiconductor ingot, lapping both surfaces of the wafer, removing a mechanical damage layer by etching treatment, flattening one of the surfaces by a surface-grinding means, polishing both of the surfaces, and then subjecting a front surface of the wafer to a finishing mirror-polishing when defining the surface subjected to surface-grinding as a back surface of the wafer.
3. The method for fabricating a semiconductor wafer according to
claim 2
wherein mirror edge polishing is conducted before or after polishing both of the surfaces.
4. The method for fabricating a semiconductor wafer according to
claim 2
wherein the etching treatment is conducted by a wet etching method using an alkali solution as an etching solution.
5. The method for fabricating a semiconductor wafer according to
claim 3
wherein the etching treatment is conducted by a wet etching method using an alkali solution as an etching solution.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor wafer, and especially a method for fabrication of a single crystal silicon wafer.

[0003] 2. Description of the Related Art

[0004] Generally, a conventional method for fabricating a semiconductor wafer comprises a slicing step to obtain wafers of a thin disc shape by slicing a single crystal silicon ingot pulled with a single crystal pulling apparatus; a coarse chamfering step to chamfer a peripheral edge portion of the sliced wafer in order to prevent cracking or breakage of the wafer; a lapping step to flatten both of the front surface and the back surface of the chamfered wafer; a cleaning or etching step to remove a remaining mechanical damage layer formed by the chamfering step and lapping step; and a mirror-polishing step to mirror-polish the front surface of the etched wafer. As shown in FIG. 1[B], adding to these steps, there can be conducted by combination of a step of surface-grinding the front surface or the both surfaces of the wafer, a double side polishing step for polishing both surfaces of the surface-ground wafer, a finishing chamfering step to mirror-polish a peripheral edge portion of the wafer before and after the double side polishing step, the finishing polishing step to mirror-polish the wafer subjected to the double side polishing, and a cleaning step for removing a polishing agent remaining on the polished wafer and contaminant in order to improve cleanness.

[0005] In the above-mentioned method for fabrication, the surface-grinding step has been introduced to support the lapping process, since high flatness of the wafer cannot be achieved only by the lapping process when a diameter of the wafer is large, especially more than 300 mm.

[0006] However, in the surface-ground wafer, grinding striations (streaks) remain as observed with a magic mirror, even after it is polished in a considerable amount. Furthermore, if it is polished in a considerable amount, the wafer may lose its proper shape, and flatness thereof is degraded.

[0007] For example, grinding striations formed at the most peripheral portion during surface-grinding of the front surface or the both surfaces of the wafer have a P-V value of about 0.2 to 0.1 μm and a striation interval of about 1 to 10 mm. Accordingly, the shape of the polishing cloth is copied (followed) to the shape of the grinding striations when it is subjected to double side polishing, so that grinding striations remain as micro roughness having a P-V value of about 30 to 50 nm, even after a finishing mirror-polishing step.

[0008] In the case of the wafer having high flatness wherein both surfaces are subjected to mirror-polishing, flatness on the back surface is too good, which may easily cause problems in a device process, such as indistinguishability of the front surface from the back surface, necessity of re-adjustment of sensing sensitivity, difficulty of chucking and releasing the wafer, and liabilities in a conveying line such as contamination.

SUMMARY OF THE INVENTION

[0009] The present invention has been accomplished to solve the above-mentioned conventional problems, and an object of the invention is to eliminate the grinding striations which remain on the front surface even when double side polishing and front surface finishing mirror-polishing are conducted after the above-mentioned conventional step of surface-grinding of the front surface or the both surfaces, to improve the quality of the front surface of the wafer, and to provide the semiconductor wafer having a proper quality in the back surface suitable for the device process, and a method for fabricating it.

[0010] To achieve the above-mentioned object, the present invention provides a semiconductor wafer obtained, at least, by removing a mechanical damage layer by etching both surfaces of the wafer, flattening one of the surfaces by a surface-grinding means, polishing both of the surfaces, and then subjecting a front surface of the wafer to a finishing mirror-polishing when defining the surface subjected to surface-grinding as a back surface of the wafer.

[0011] The wafer is excellent in flatness on both surfaces, and condition of the surfaces is different from each other. For example, the front surface is finished to be a mirror surface having no micro roughness formed during surface-grinding, and the back surface is finished to be a surface on which micro roughness (P-V value=about 30 to 50 nm, interval=about 1 to 10 mm) remains as grinding striations.

[0012] When the wafer of the present invention is used, there are no grinding striations remaining on the front surface which are formed in the case of the conventional wafer fabricated by conducting lapping of the both surfaces, surface-grinding of the front surface or the both surfaces, double side polishing, and mirror-polishing. Furthermore, when the wafer of the present invention is chucked at the back surface thereof, there are no problems, which may be easily caused in a device process because of too good flatness of the back surface, such as indistinguishability of the front surface from the back surface, necessity of re-adjustment of sensing sensitivity, difficulty of chucking and releasing the wafer, and liabilities in a conveying line such as contamination. Furthermore, the grinding striations on the back surface are never transferred on the front surface in fabrication of the wafer of the present invention. Accordingly, it can be used in a process of highly integrated devices, productivity and yield of a device can be improved, and cost can be significantly reduced.

[0013] The present invention also provides a method for fabricating a semiconductor wafer comprising at least slicing a wafer from a semiconductor ingot, lapping both surfaces of the wafer, removing a mechanical damage layer by etching treatment, flattening one of the surfaces by a surface-grinding means, polishing both of the surfaces, and then subjecting a front surface of the wafer to a finishing mirror-polishing when defining the surface subjected to surface-grinding as a back surface of the wafer.

[0014] According to the above-mentioned method comprising the double side lapping step, the single side surface-grinding step, the double side polishing step and the step of subjecting the other surface than the above ground surface to a finishing mirror-polishing, a wafer having high flatness can be easily fabricated at low cost, as compared with the conventional method comprising a double side lapping step, a step of grinding a front surface or both surfaces, a double side polishing step and a mirror-polishing step. Furthermore, a problem of grinding striations remaining on the surface, which is one of disadvantages in the conventional method, can be solved, and a wafer having a front surface comprising a mirror surface without grinding striations and micro roughness and a back surface with desired grinding striations, can be fabricated easily and at low cost.

[0015] In this case, it is preferable to conduct mirror edge polishing before or after polishing both of the surfaces described above.

[0016] When the mirror edge polishing (mirror-polishing on chamfered edge) is conducted before or after the double side polishing step, defects such as cracking or breakage of the wafer can be prevented during polishing or in a device process. The mirror edge polishing is more effective, since it is conducted after the peripheral edge portion of the wafer is ground for coarse chamfering before the lapping step in order to prevent cracking or breakage of the wafer or the like during lapping and a surface-grinding.

[0017] It is preferable to etch the wafer by a wet etching method using an alkali solution as a etching solution.

[0018] Thereby, it is possible to remove a mechanical damage layer of the wafer, maintaining flatness achieved by the double side lapping step, and to conduct a polishing step effectively with maintaining high flatness, in cooperation with the following single side grinding. A stock removal of the wafer in the etching treatment can be minimal for removing the mechanical damage layer.

[0019] As described above, according to the present invention, a semiconductor wafer having the front surface which is a mirror surface with high flatness and high brightness and without micro roughness and the back surface having appropriate fine grinding striations can be fabricated easily and at low cost. Accordingly, when the wafer is chucked in a device process, the grinding striations on the back surface are never transferred on the front surface of the wafer of the present invention, and it can be used in a process of highly integrated devices, productivity and yield of a device can be improved in a device process, and cost can be significantly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1(A) is a flow chart showing a method of fabricating a semiconductor wafer from a semiconductor ingot according to the present invention, and a surface condition of the wafer.

[0021]FIG. 1(B) is a flow chart showing a conventional method of fabricating a semiconductor wafer from a semiconductor ingot, and a surface condition of the wafer.

[0022]FIG. 2 is a schematic view showing a double side lapping apparatus used in the method of the present invention.

[0023]FIG. 3 is a schematic view showing a single side surface-grinding apparatus used in the method of the present invention.

[0024]FIG. 4 is a schematic view showing a double side polishing apparatus used in the method of the present invention.

[0025]FIG. 5 is a schematic view showing a single side finishing mirror-polishing apparatus used in the method of the present invention.

DESCRIPTION OF THE INVENTION AND EMBODIMENT

[0026] The present invention will now be described in detail, but the present invention is not limited thereto.

[0027] The inventors of the present invention have found that it is preferable to use a surface formed by lapping without grinding striations as a front surface, and to use the other surface with grinding striations easily remaining after surface-grinding as a back surface of the wafer, in order to fabricate a wafer wherein grinding striations are eliminated which remain on the front surface even when double side polishing and finishing mirror-polishing are conducted, after a conventional lapping step and a step of surface-grinding a front surface or both surfaces of the wafer described above, and wherein there is no damage or problem relating to the back surface condition formed in a device process, and thereby both quality of the front surface and condition of the back surface can be improved, and have completed the present invention by defining combination of each step such as a lapping step, a surface-grinding step, a polishing step and a mirror-polishing step, and various conditions thereof.

[0028] An example of a method for fabricating a semiconductor wafer from a semiconductor ingot will be explained below with reference to drawings. FIG. 1(A) is a flow chart schematically showing a method of fabrication according to the present invention, and a surface condition of the wafer obtained in each step.

[0029] The method of fabrication shown in FIG. 1(A) substantially comprises the following eight steps.

[0030] (1) A slicing step of slicing a semiconductor single crystal ingot into a thin disc-shape wafer 1 (see FIG. 1[A](a)).

[0031] (2) A coarse chamfering step of chamfering a peripheral edge portion of the wafer 1 obtained through the slicing step. At a chamfered portion of the wafer 1 subjected to the coarse chamfering, mechanical damage 2 is generated (see FIG. 1[A](b)).

[0032] (3) A lapping step of flattening a chamfered wafer, where both surfaces of the wafer are ground with pouring a lapping solution containing abrasive grains by a lapping apparatus. Mechanical damage 2 is generated on the lapped wafer 1 (see FIG. 1[A](c)).

[0033] (4) The lapping powder adhered to the both surface of the lapped wafer 1 is removed by cleaning or etching. The mechanical damage 2 can be removed to some extent or almost completely by cleaning or etching. At the same time, etch pit 3 is generated on the wafer 1 by etching (see FIG. 1[A](d)).

[0034] (5) One surface 1 a of the cleaned or etched wafer 1 is subjected to surface-grinding to achieve high flatness of the surface. The mechanical damage 2 and the grinding striations 4 are generated on the surface 1 a of the wafer 1 subjected to surface-grinding (see FIG. 1[A](e)).

[0035] (6) A polishing step of polishing both surfaces 1 a, 1 b of the wafer 1 wherein one surface 1 a is ground. The mechanical damage 2 and the etch pit 3 on the both surfaces 1 a, 1 b of the wafer 1 are removed by the polishing step, but grinding striations remain on the surface 1 a which was surface-ground (see FIG. 1[A](f)).

[0036] (7) The peripheral edge portion of the wafer 1 is mirror-polished before or after the double side polishing step. Thereby, the mechanical damage 2 and the etch pit 3 at the peripheral edge portion of the wafer 1 are removed. (see FIG. 1[A](f)).

[0037] (8) The surface 1 a of the wafer 1 which is surface-ground is defined as a back surface, and a front surface of the wafer 1 subjected to the double side polishing is subjected to a finishing mirror-polishing. Thereby, there can be obtained the semiconductor wafer having a front surface 1 b and a back surface 1 a which is surface-ground (see FIG. 1[A](g)).

[0038] (9) A cleaning step of cleaning and drying the wafer after polishing (not shown).

[0039] Next, a lapping apparatus, a surface-grinding apparatus and a polishing apparatus used in the present invention and processing condition will be explained below.

[0040] In a flattening step, a lapping apparatus is used at first. FIG. 2 shows an example of double side lapping apparatus used in the method of the present invention.

[0041] A sliced wafer 1 is set between the lapping turn tables (the upper turn table 11 and the lower turn table 12) which are faced each other vertically. Lapping solution 17, which is generally a mixture of alumina or silicon carbide abrasive grains and glycerol is poured from a lapping solution nozzle 16 to a space between the lapping table and the wafer, in order to mechanically grind both surface of the wafer by rotating the lapping table for rubbing with pressing it on the wafer under pressure.

[0042] The upper turn table 11 and the lower turn table 12 are rotated in opposite directions to each other. A center gear (sun gear) 13 is provided on the lower turn table 12, and an internal gear 14 is provided on the outer periphery of the lower turn table 12. Plural geared carriers 15 carrying plural wafers 1 each set in a wafer receiving hole, are interposed between the upper and lower lapping turn tables, and rotated and revolved between the center gear 13 and the internal gear 14. Thereby, the plural wafers 1 can be lapped at the same time under an adequate pressure applied by the upper turn table 11.

[0043] Next, the surface-grinding apparatus will be explained. It is an apparatus for grinding the wafer with a grinding wheel (grinding stone) after lapping and etching treatment to achieve higher flatness. As such an apparatus, a double side grinding apparatus for grinding both surfaces of the wafer at the same time, an infeed surface-grinding apparatus for grinding one surface or the like, are well known. In the method of the present invention, the latter is used. One example of the apparatus is shown in FIG. 3.

[0044] In the infeed surface-grinding apparatus 20, the wafer 1 lapped as described above is fixed on a rotatable suction plate 21 having a suction type fixing mechanism, and rotated by a suction plate driving motor 24, and the front surface or the back surface of the wafer can be ground with a cup-like grinding wheel 22 driven at high speed by a grinding wheel driving motor 23. When the wafer 1 is fixed with vacuum, a vacuum source (not shown) to which a vacuum pipe 25 is connected, is used.

[0045] The double side polishing apparatus used in a double side polishing step is for mechanochemically polishing both surfaces of the wafer having stable thickness accuracy and flatness accuracy, subjected to the slicing step, the chamfering step, the flattening step and the etching step.

[0046] Various polishing methods can be applied to the double side polishing described above. For example, the double side polishing apparatus shown in FIG. 4 will be explained below.

[0047] A wafer 1 subjected to surface-grinding is set between polishing pads 33, 34 consisting of polyurethane foamed layer or the like adhered on the turn tables (the upper turn table 31 and the lower turn table 32) of the double side polishing apparatus 30 which are faced each other vertically. With pouring a polishing solution 39 generally consisting of polishing abrasive grains such as silica suspended in an alkali solution from a polishing solution nozzle 38 to a space between the polishing pad and the wafer, to mechanochemically polish both surfaces of the wafer by rotating them for rubbing under pressure.

[0048] The upper turn table 31 and the lower turn table 32 are rotated in opposite directions to each other. A center gear (sun gear) 35 is provided on the lower turn table 32, and an internal gear 36 is provided on the outer periphery of the lower turn table 32. A plurality of geared carriers 37 carrying plural wafers 1 each set in a wafer receiving hole, are interposed between the upper and lower turn tables, and are rotated and revolved between the center gear 35 and the internal gear 36. Thereby, both surfaces of the plural wafers 1 can be polished at the same time under an adequate pressure applied by the upper turn table 31.

[0049] The finishing mirror-polishing is conducted on one surface of the wafer in the method of the present invention. For example, it is conducted through use of a single side polishing apparatus 40 shown in FIG. 5 as follows. The back surface of the wafer 1 is fixed to a wafer holder 42 rotating with a holder shaft 47, using an adhesive such as wax which can be easily removed in the later cleaning step. With pouring a polishing agent 44 generally consisting of polishing abrasive grains such as silica suspended in an alkali solution from a nozzle 43 for a polishing agent to a space between the polishing cloth 45 and the wafer 1, a polishing cloth 45 consisting of polyurethane foamed layer or the like adhered on the turn table 41 is rotated with a turn table rotating shaft 46 at relative speed, with being loaded, to mirror-polish only front surface of the wafer mechanochemically.

[0050] In that case, other than the above-mentioned method wherein the back surface of the wafer is held by adhering it with wax, there is a method wherein the back surface of the wafer is held by a vacuum suction revolving carrier without using wax, or a method wherein the back surface of the wafer is held with a soft resin without using wax. Any other methods can be used in the present invention, and the method of the finishing mirror-polishing is not restricted to the above.

[0051] In the cleaning step, cleaning is conducted with, for example, SC-1 essentially comprising aqueous ammonia and hydrogen peroxide aqueous solution or SC-2 essentially comprising hydrochloric acid and hydrogen peroxide aqueous solution, in order to remove a polishing agent or the like adhered on the front surface of the wafer produced in the above-mentioned front surface finishing mirror-polishing step, and improve cleanness of the front and back surface.

[0052] In the wet etching step in the present invention, the mechanical damage layer formed on the front and back surface of the wafer formed in a flattening step according to a double side lapping method can be removed by chemical etching. An etching solution can be acid, alkali or the like. However, the flatness may be lowered depending on the kinds of the etching solution, a stirring condition of the etching solution during etching treatment, and progressing condition of the reaction. According to the present invention, the flatness does not need to be cared so much since the flatness can be improved by the later surface grinding step. However, it is preferable to conduct etching without spoiling the flatness obtained in the lapping step. The inventors made experiments, and revealed that the best etching solution is an alkali solution such as a 45 to 50% aqueous solution of sodium hydroxide or potassium hydroxide.

EXAMPLE

[0053] The following example is being submitted to further explain specific embodiment of the present invention. This example is not intended to limit the scope of the present invention.

Example

[0054] Semiconductor wafers were fabricated from a semiconductor ingot according to the method shown in FIG. 1[A](a) to (g). 200 of them were determined as for their quality.

[0055] The apparatuses described above, namely, a double side lapping apparatus, a single side grinding apparatus, a double side polishing apparatus, a single side finishing mirror-polishing apparatus or the like were mainly used.

[0056] The wafers having a diameter of 300 mm and a thickness of 975 μm were obtained as a starting material by a slicing step, and subjected to lapping, grinding, polishing and the like.

[0057] The steps of lapping, grinding and polishing were conducted as follows with varying conditions therefor.

[0058] The double side lapping step was conducted varying a stock removal in the range from 80 to 200 μm as a value of those of both surfaces put together.

[0059] The etching step was conducted using an alkali solution or acid solution with a sufficient stock removal to remove a mechanical damage layer formed during lapping.

[0060] The single side grinding was conducted using a grinding wheel such as a resin bond of #2000 to #4000 with a stock removal of 10 to 20 μm.

[0061] The double side polishing was conducted with a stock removal of 10 to 20 μm as a value of those of both surfaces put together, provided that the stock removal was determined so that the mechanical damage layer formed during a single side grinding can be removed.

[0062] The double side polishing was conducted using a foamed urethane polishing cloth or a rigid urethane polishing pad (polishing cloth) as a polishing cloth. A polishing agent containing colloidal silica was used.

[0063] Even after the above-mentioned double side polishing, grinding striations remained. The grinding striation is different from the mechanical damage, but is a shape formed on the surface by a grinding wheel, namely like undulation, which remains even after the double side polishing.

[0064] The surface on which the grinding striations remained was determined as a back surface, the other surface, namely the front surface was subjected to a finishing mirror-polishing. The polishing was conducted with a stock removal of 1 to 2 μm by a copying polishing method wherein only the front surface of the wafer was mechanochemically polished to be a mirror surface.

[0065] After subjected to the cleaning step as a final step, the wafers were evaluated, and revealed excellent as follows.

[0066] (1) the flatness of the wafer was quite excellent as 0.20 μm as represented by SBIRmax.

[0067] The flatness was measured through use of an electric capacitive sensing thickness measuring apparatus (Galaxy-AFS manufactured by ADE corporation), and represented by SBIRmax (Site Back-side Ideal Range: a standardized value according to SEMI standard M1 or the like, a cell size of 25×25).

[0068] (2) The front surface of the wafer was finished as a mirror surface having high brightness with no grinding striations nor micro roughness similar thereto.

[0069] (3) On the back surface, there remained grinding striations as micro roughness having a P-V value of about 30 to 50 mm and an interval of about 1 to 10 mm. However, they were very fine, and therefore, the grinding striations on the back surface were not transferred to the front surface of the wafer when the wafer was chucked during device process.

[0070] P-V value shows a kind of microroughness, and is measured through use of NANOMETRO 330F (a laser displacement measuring apparatus manufactured by Kuroda Seikousha) in an area of 20 mm×5 mm. The P-V value is a maximal difference between a peak and a valley.

[0071] The wafer of the present invention were determined in the device step as for the problems in a device process, such as indistinguishability of the front surface from the back surface, necessity of re-adjustment of sensing sensitivity, difficulty of chucking and releasing the wafer, and liabilities in a conveying line such as contamination, which were easily caused in the case of the wafer wherein both surfaces were mirror-polished and had high flatness because flatness on the back surface was too good. Such problems were not caused in the wafer of the present invention.

[0072] The present invention is not limited to the above-described embodiment. The above-described embodiment is a mere example, and those having the substantially same structure as that described in the appended claims and providing the similar action and effects are included in the scope of the present invention.

[0073] For example, the silicon wafer having a diameter of 300 mm (12 inches) was processed in the embodiment of the present invention. However, the present invention is applicable to the wafer having a large diameter such as 200 mm (8 inches) to 400 mm (16 inches) or more. Therefore, these modifications are included within the scope of the present invention.

[0074] Furthermore, the method of the embodiment of the present invention comprises the steps shown in FIG. 1[A]. The present invention is not limited to the steps shown there. There can be further added a heat treatment step, a cleaning step or the like, some of the steps can be omitted, and the sequence of the steps can be changed.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6743722Jan 29, 2002Jun 1, 2004StrasbaughMethod of spin etching wafers with an alkali solution
US6796523Mar 1, 2002Sep 28, 2004X-Spooler, Inc.Wire winding machine with wire clamping and cutting assembly
US7160808Jun 1, 2004Jan 9, 2007StrasbaughChuck for supporting wafers with a fluid
US7250368 *Apr 24, 2003Jul 31, 2007Shin-Etsu Handotai Co., Ltd.Semiconductor wafer manufacturing method and wafer
US7456106 *Oct 1, 2004Nov 25, 2008Sumitomo Mitsubishi Silicon CorporationMethod for producing a silicon wafer
US7648890 *Aug 15, 2006Jan 19, 2010Sumco Corporationusing aqueous acid solution which contains hydrogen fluoride, nitric acid, and phosphoric acid in single-wafer etching step; capable of performing a high level of flattening
US7686891 *Jun 28, 2005Mar 30, 2010Sumco Techxiv CorporationMethod and apparatus for collecting chemicals from semiconductor wafer
US8080113Feb 4, 2010Dec 20, 2011Komatsu Denshi Kinzoku Kabushiki KaishaMethod and apparatus for collecting chemicals from semiconductor wafer
US8444455 *May 5, 2010May 21, 2013Siltronic AgPolishing pad and method for polishing a semiconductor wafer
US20100330882 *May 5, 2010Dec 30, 2010Siltronic AgPolishing Pad and Method For Polishing A Semiconductor Wafer
WO2003065431A1 *Jan 29, 2003Aug 7, 2003StrasbaughMethod of spin etching wafers with an alkali solution
Classifications
U.S. Classification438/690, 438/689, 257/E21.237
International ClassificationH01L21/306, H01L21/304
Cooperative ClassificationH01L21/02008
European ClassificationH01L21/02D2M
Legal Events
DateCodeEventDescription
May 2, 2006FPExpired due to failure to pay maintenance fee
Effective date: 20060305
Mar 6, 2006LAPSLapse for failure to pay maintenance fees
Sep 21, 2005REMIMaintenance fee reminder mailed
Nov 22, 1999ASAssignment
Owner name: SHIN-ETSU HANDOTAI CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KISHIMOTO, JUN;REEL/FRAME:010406/0778
Effective date: 19991019
Owner name: SHIN-ETSU HANDOTAI CO., LTD. TOGIN BLDG., 4-2, MAR