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Publication numberUS20010041306 A1
Publication typeApplication
Application numberUS 09/385,929
Publication dateNov 15, 2001
Filing dateAug 30, 1999
Priority dateAug 30, 1999
Also published asUS6387596
Publication number09385929, 385929, US 2001/0041306 A1, US 2001/041306 A1, US 20010041306 A1, US 20010041306A1, US 2001041306 A1, US 2001041306A1, US-A1-20010041306, US-A1-2001041306, US2001/0041306A1, US2001/041306A1, US20010041306 A1, US20010041306A1, US2001041306 A1, US2001041306A1
InventorsDaniel C. Cole, Edward W. Conrad, David V. Horak, Randy W. Mann, Paul W. Pastel, Jed H. Rankin, Andrew J. Watts
Original AssigneeDaniel C. Cole, Edward W. Conrad, David V. Horak, Randy W. Mann, Paul W. Pastel, Jed H. Rankin, Andrew J. Watts
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of forming resist images by periodic pattern removal
US 20010041306 A1
Abstract
The present invention provides a method of forming nested and isolated images in a photosensitive resist. In the disclosed method, the entire surface of the photosensitive resist or selected regions thereof is exposed to a first mask having a set of nested, i.e. repeating pattern or grid images thereon, and then exposed to a second mask in order to remove unwanted portions of the nested image, so as to provide regions of nested and regions of isolated images in said photosensitive resist. The method may also be used to form regions having images in proximity to one another and regions having isolated images by exposing the entire surface of the photosensitive resist to a first mask having repeating patterns, and then removing entire or portions of the repeating patterns by exposure of the photosensitive resist with a second mask.
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Claims(23)
Having thus described our invention in detail, what we claim as new and desire to secure by the letters Patent is:
1. A method of forming resist images in a photosensitive resist comprising the steps of:
(a) exposing a photosensitive resist to a first mask having a grid pattern image thereon so as to form a repeating pattern image on said photosensitive resist; and
(b) exposing the photosensitive resist containing said repeating pattern image to a trim mask having a predetermined pattern thereon so as to remove unwanted portions of the repeating pattern image in said photosensitive resist.
2. The method of
claim 1
wherein said photosensitive resist is formed on a substrate.
3. The method of
claim 2
wherein said substrate is a semiconductor chip, wafer, interconnect structure or circuit board.
4. The method of
claim 2
wherein said substrate is composed of, or contains, a semiconducting material selected from the group consisting of Si, Ge, GaAs, InAs, InP and other like III/V compounds.
5. The method of
claim 1
wherein said photosensitive resist is a dry or liquid photosensitive material.
6. The method of
claim 1
wherein said photosensitive resist is a radiation sensitive material selected from the group consisting of a negative working resist, a positive working resist and mixtures thereof.
7. The method of
claim 1
wherein step (a) is carried out under conditions effective to provide harden areas in said photosensitive resist.
8. The method of
claim 1
wherein step (a) is carried out using off-axis illumination.
9. The method of
claim 8
wherein said off-axis illumination is annular.
10. The method of
claim 1
wherein step (a) is carried out at an energy of from about 10 millijoules/cm2 to about 30 millijoules/cm2 using a 193 nm or 248 nm light source.
11. The method of
claim 1
wherein said first mask comprises light blocking regions corresponding to features to be printed and open, light transmitting areas surrounding the features.
12. The method of
claim 11
wherein said features comprise an opaque layer of chrome formed on quartz.
13. The method of
claim 1
wherein step (b) is carried using off-axis illumination.
14. The method of
claim 13
wherein said off-axis illumination is annular.
15. The method of
claim 1
wherein said step (b) exposure is substantially less than said step (a) exposure.
16. The method of
claim 1
further comprises a postbake step after step (b).
17. The method of
claim 1
wherein said predetermined pattern is a repeating pattern.
18. The method of
claim 1
wherein a portion of said predetermined pattern is a repeating pattern.
19. The method of
claim 1
further comprising a development step after step (b) which removes unexposed areas of said photosensitive resist.
20. The method of
claim 1
wherein said trim mask has larger features than said first mask.
21. The method of
claim 1
wherein a common grid mask is used for making multiple part numbers.
22. A method of forming resist images in a photosensitive resist comprising the steps of:
(a) exposing a photosensitive resist to a first mask having a grid pattern image thereon so as to form a nested image on said photosensitive resist; and
(b) exposing the photosensitive resist containing said nested image to a trim mask having a predetermined pattern thereon so as to remove unwanted portions of the nested image providing an isolated image in said photosensitive resist.
23. A method of forming resist images in a photosensitive resist comprising the steps of:
(a) exposing a photosensitive resist to a first mask having a grid pattern image having a first periodicity thereon so as to form a nested image on said photosensitive resist; and
(b) exposing the photosensitive resist containing said first periodicity to a trim mask having a predetermined pattern having a second periodicity thereon so as to remove unwanted portions of the first periodicity providing a semi-nested image having a third periodicity in said photosensitive resist, said second and third periodicities being the same but different from said first periodicity.
Description
DESCRIPTION

[0001] 1. Field of the Invention

[0002] The present invention relates to photolithography, and more specifically to a method of forming resist images by utilizing a grid mask containing a periodic set of images to produce a nested set of identical images over an entire chip surface or selected regions thereof and then removing any unwanted portions of said nested set of identical images with a trim mask.

[0003] 2. Background of the Invention

[0004] As the minimum feature size in semiconductor integrated circuit technology is pushed near or below the wavelength of light used in micro-lithographic projection printing, diffraction effects introduce significant differences between the patterns used on micro-lithographic reticles and the resulting printed structures on a semiconductor wafer. Similarly, the smaller the circuit elements become, the more difficult it is to create the desired pattern shapes on the wafer due to factors such as localized etch variations, mask distortions, lens distortions, topography variations, and non-uniform material composition.

[0005] These physical factors introduce deviations in isolated versus nested printed structures, with the degree of variation being highly dependent on the degree of proximity of nearby shapes. In order to maximize circuit performance and speed, it has been found highly desirable to make the device structure dimensions as identical as possible, e.g. to try to make isolated gates and nested gates print as identically as possible. These effects become increasing important as the physical dimensions of the circuit elements decrease.

[0006] Across Chip Linewidth Variation (ACLV) is one major problem in semiconductor device manufacturing. Image size variations can affect transistor speed matching and resistivity and conductance matching from one portion of the chip to another. One significant cause of printed pattern size variation is the diffraction component of imaging, which results in structures on a reticle being imaged differently depending upon what other structures are present in the local neighborhood.

[0007] A common form of this is differences between nested and isolated images. FIG. 1 shows a prior art mask intended to produce holes in a negative resist. FIG. 2 shows the resultant resist images with the isolated images being overexposed and smaller. In actuality, the printed shapes in FIG. 2 occur as rounded structures because each corner on a mask ends up as a printed rounded corner on the wafer. The isolated structure prints much differently than a nested structure. The degree that they print differently depends on the degree of proximity of nearby structures, as well as the size of nearby structures, the periodicity of nearby structures, and exposure tool illumination conditions.

[0008] It should be further appreciated that prior art photolithographic techniques require multiple custom masks to provide a nested and isolated image on the surface of a semiconductor wafer having improved ACLV. An example of such a technique, is described, for example, in U.S. Pat. No. 5,424,154 which discloses a method of enhancing the lithographic resolution of randomly laid out isolated structures, wherein a first mask comprising an active layer with isolated features such as gates is used. Portions of the active layer have a reduced dimension typical of periodic structures. The first mask disclosed in the '154 patent additionally has complementary features provided along side the reduced active features to provide periodicity. Accordingly, the resolution of the lithographic process is enhanced, and other enhanced resolution technologies additionally can be used to best advantage to form a patterned photosensitive layer having isolated features of reduced width. The photosensitive resist is then exposed to a second mask which exposes the complementary features so that they are removed from the latent image in the photosensitive resist. This second exposure reportedly improves resolution by enhancing contrast between exposed and unexposed regions.

[0009] While such prior art techniques can be used in printing resist images, it would be highly desirable to provide a method of forming resist images using a non-custom first mask (or a non-custom common grid mask useable for many designs) and a single custom trim mask to provide the nested and isolated images. This provides a significant reduction in manufacturing cost.

SUMMARY OF THE INVENTION

[0010] The present invention provides a method of overcoming the problems associated with prior art photolithographic techniques, especially those caused by ACLV, by first printing a set of nested images using a grid mask over the entire surface of a semiconductor chip or critical regions thereof; and then removing unwanted images with a trim mask. The grid mask can be fabricated and selected to be a nearly perfect mask for each chip size, so only the less critical trim mask is personalized for a given chip design.

[0011] Specifically, the method of the present invention comprises the steps of:

[0012] (a) exposing a photosensitive resist to a first mask having a grid pattern image thereon so as to form a repeating pattern image on said photosensitive resist; and

[0013] (b) exposing the photosensitive resist containing said repeating pattern image to a trim mask having a predetermined pattern thereon so as to remove unwanted portions of the repeating pattern image in said photosensitive resist.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 represents a prior art mask used for forming holes in a negative resist layer.

[0015]FIG. 2 shows the resultant resist image produced using the mask shown in FIG. 1.

[0016] FIGS. 3A-G show the various processing steps and masks that are employed in the present invention in printing a nested and isolated resist image when a negative working resist is used.

[0017]FIG. 4 shows a grid mask for fabricating lines when a positive working resist is used.

[0018]FIG. 5 shows the trim mask that is employed to remove unwanted portions of the grid provided using the grid mask shown in FIG. 4.

[0019]FIG. 6 shows the resultant nested and isolated resist image produced using the masks shown in FIGS. 4 and 5.

DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention, which provides a method of forming nested and isolated resist images by periodic pattern removal, will now be described in greater detail by referring to the drawings that accompany this application. It should be noted that in the drawings like and corresponding elements are referred to by like reference numerals.

[0021] Reference is made first to FIG. 3A which shows a structure comprising a substrate 10 having a layer of photosensitive resist 12 formed on the surface thereof.

[0022] Substrate 10 employed in the present invention is typically a semiconductor chip, wafer, interconnect structure, circuit board or other like semiconductor structures. The substrate is typically composed of, or contains, a semiconducting material such as Si, Ge, GaAs, InAs, InP or other like III/V compounds. The substrate may contain active device regions, wiring regions or other like regions. For clarity these regions are not shown in the drawings of the present application, but nevertheless, may be present therein.

[0023] Photosensitive resist 12 is composed of any conventional photosensitive material including dry resists and liquid resists which is capable of receiving an image during exposure. Examples of some suitable photosensitive resists that can be employed in the present invention include Shipley CGR2205 negative resist and Shipley UV5 positive resist as examples. Other negative or positive resists can also be employed in the present invention. Mixtures of negative and positive resists are also contemplated in the present invention.

[0024] The photosensitive resist is formed on the surface of substrate 10 using conventional deposition processes well known to those skilled in the art. Suitable deposition processes that can be employed in the present invention in forming photosensitive resist 12 on the surface of substrate 10 include: spin-on coating, dip coating, chemical vapor deposition, sputtering and other like deposition techniques.

[0025] Next, a suitable first mask having a desired grid image thereon is selected. The mask having the desired grid image (hereinafter “grid mask”) comprises light blocking regions corresponding to features to be printed and open, light transmitting areas surrounding the features. Typically, the features of the grid mask comprise an opaque layer of, for example, chrome formed on a reticle base of quartz.

[0026] One such mask is shown in FIG. 3B, wherein reference numerals 14 are the feature regions composed of chrome and reference numeral 16 is the light transmitting area surrounding features 14. The grid mask of FIG. 3B would be used with a negative resist to form, for example, via images. The grid in FIG. 3B is shown as an array of square features 14. Feature 14 may be other shapes, and may even be comprised of combinations of two or more sub-features.

[0027] An alternative grid mask that can be employed in the present invention is shown in FIG. 4. In FIG. 4, feature 14 is a lattice. The grid mask of FIG. 4 would be used with a positive resist to form, for example, line images. It is noted that the grid mask employed in the present invention is one which is capable of forming nested images in the photosensitive resist during grid exposure.

[0028] The photosensitive resist is exposed to radiation through the grid mask structure using a commercially available exposure device to form a latent nested image of the grid mask in the photosensitive resist. Exposure conditions can be conventional circular illumination or off-axis illumination such as annular, dipole or quadrupole illumination. Exposure is typically carried in the present invention at an energy of from about 10 to about 30 millijoules/cm2 using a 193 nm or 248 nm light source; i.e. laser, arc lamp and etc.

[0029] The above exposure process causes the formation of latent nested images 12′ in photosensitive resist 12 that are harder than the adjacent areas which were not subjected to exposure. The structure containing the latent nested image on the photosensitive resist is shown in FIG. 3C.

[0030] Next, a trim mask is selected containing features of a desired pattern thereon so as to isolate certain regions of the nested image. The trim mask, like the grid mask disclosed above, is composed of light blocking regions corresponding to features to be printed and open, light transmitting areas surrounding the features. Typically, the features comprise an opaque layer of, for example, chrome formed on a reticle base of quartz.

[0031] A typical trim mask that can be employed in the present invention is shown in FIG. 3D, wherein reference numerals 14 represent feature regions composed of chrome and reference numeral 16 represents light transmitting areas surrounding features 14. The trim mask of FIG. 3D would be used with a negative resist to form, for example, via images.

[0032] An alternative trim mask that can be employed in the present invention is shown in FIG. 5. The trim mask of FIG. 5 would be used with a positive resist to form, for example, line images. As is seen in those figures, the trim mask employed in the present invention has larger features than those of the grid mask, so as to be able to provide an isolated image on the surface of the photosensitive resist. However the exact relationship in size and overlay between the grid and trim masks may be adjusted based on the final image desired. For example, the trim mask of FIG. 5 may be adjusted to compensate for the intersections of the grid mask image in FIG. 4 so the resist images illustrated in FIG. 6 are uniform rather than variable in width along their lengths.

[0033] The photosensitive resist is exposed through the trim mask to radiation using a commercially available device using exposure conditions to modify the latent grid image in the photosensitive resist so as to remove unwanted portions of the nested latent image creating a latent isolated image in the photosensitive resist. Exposure conditions can be conventional circular illumination or off-axis illumination such as annular, dipole and quadrupole illumination. Exposure is typically carried in the present invention at an energy of from about 5 to about 30 millijoules/cm2 using a 193 nm or 248 nm light source.

[0034] The trim mask exposure step also causes the formation of areas 12′ on photosensitive resist layer 12 that are harder than the adjacent areas which were not subjected to exposure. The patterned structure may, if required, be subjected to additional trim exposure steps.

[0035] After trim exposure, the photosensitive resist may optionally be postbaked at a temperature of from about 70 to about 160 C. for a time period of from about 30 to about 120 seconds for Shipley CGR 2205 or at a temperature of from about 100 to about 160 C. for a time period of from about 30 to about 120 seconds for Shipley UV5. Other baking temperatures and times are also contemplated by the present invention.

[0036] Areas of photosensitive resist 12 that were not exposed in either grid or trim mask exposure steps are then developed, i.e. removed, using a suitable solvent that is capable of removing the non-exposed regions of the photosensitive resist, yet selective enough to leave behind the harden areas 12′ containing the desired nested and isolated image pattern therein when the resist is a positive working resist. When the resist is a positive working resist, the developer is usually an aqueous basic solution capable of removing the exposed regions of the photosensitive layer, yet selective enough to leave behind the unexposed areas.

[0037] The final structure after exposing thru the trim mask and development is shown in FIGS. 3F and 3G for the case of a negative resist. FIG. 3F is a side view and FIG. 3G is a top view of a portion of the substrate containing the developed resist layer. Alternatively, FIG. 6. is a top view of a portion of the substrate containing the developed resist layer when a positive resist is used. As are shown therein, the substrate 10 contains a resist image 12′ thereon which may have nested regions and isolated regions.

[0038] In some cases it may be useful to leave every other or every third or similar groupings of grid images. This can be achieved by exposing the photosensitive resist to the grid mask where the images are arranged in a first periodic pattern and then exposing the photosensitive resist to a trim mask having images arranged in a second periodic pattern. This results in unwanted portions of the grid mask images being removed in a third periodic pattern. The second and third periodicities are the same but different from the first periodicity.

[0039] It should be noted that by employing the method of the present invention it is possible to print images having nearly the same size as the masks utilized. Moreover, there are no gross image size differences using the method of the present invention. More specifically, some of the minor pattern dependent effects, such as those due to diffraction from the edge of the trim mask will still remain after employing the method of the present invention. These minor effects are, however, greatly offset by the fact that the present method removes the major contributor to proximity effects. In general, the trim mask has much larger dimensions than the dimension of the single structures so edge to edge proximity diffraction effects will be a much smaller contributor using the method of the present invention.

[0040] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the scope and spirit of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6884551Sep 4, 2002Apr 26, 2005Massachusetts Institute Of TechnologyMethod and system of lithography using masks having gray-tone features
US7306881May 27, 2004Dec 11, 2007Massachusetts Institute Of TechnologyMethod and system of lithography using masks having gray-tone features
US7387871 *Aug 26, 2004Jun 17, 2008Seagate Technology LlcMask complementary multiple exposure technique
US7399709 *Sep 27, 2002Jul 15, 2008Taiwan Semiconductor Manufacturing Co., Ltd.Complementary replacement of material
US7651821Apr 8, 2005Jan 26, 2010Massachusetts Institute Of TechnologyMethod and system of lithography using masks having gray-tone features
US7919377 *Feb 22, 2008Apr 5, 2011Intel CorporationContactless flash memory array
US8139199Feb 28, 2008Mar 20, 2012Nikon CorporationExposure method, exposure apparatus, light converging pattern formation member, mask, and device manufacturing method
WO2003079111A1 *Sep 4, 2002Sep 25, 2003Massachusetts Inst TechnologyA method and system of lithography using masks having gray-tone features
WO2008123535A2 *Mar 26, 2008Oct 16, 2008Nippon Kogaku KkExposure method, exposure apparatus and device manufacturing method
Classifications
U.S. Classification430/312, 430/5, 430/311
International ClassificationG03F7/20
Cooperative ClassificationG03F7/70466, G03F7/70125, G03F7/203
European ClassificationG03F7/70D10, G03F7/70J8, G03F7/20B4
Legal Events
DateCodeEventDescription
Aug 30, 1999ASAssignment
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:COLE, DANIEL C.;CONRAD, EDWARD W.;HORAK, DAVID V.;AND OTHERS;REEL/FRAME:010214/0333;SIGNING DATES FROM 19990825 TO 19990826
Sep 14, 2005FPAYFee payment
Year of fee payment: 4
Dec 21, 2009REMIMaintenance fee reminder mailed
May 14, 2010LAPSLapse for failure to pay maintenance fees
Jul 6, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100514