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Publication numberUS20010041434 A1
Publication typeApplication
Application numberUS 08/730,016
Publication dateNov 15, 2001
Filing dateOct 11, 1996
Priority dateOct 13, 1995
Also published asUS6399466
Publication number08730016, 730016, US 2001/0041434 A1, US 2001/041434 A1, US 20010041434 A1, US 20010041434A1, US 2001041434 A1, US 2001041434A1, US-A1-20010041434, US-A1-2001041434, US2001/0041434A1, US2001/041434A1, US20010041434 A1, US20010041434A1, US2001041434 A1, US2001041434A1
InventorsAkihiro Nakamura
Original AssigneeAkihiro Nakamura
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of manufacturing non-volatile semiconductor memory device storing charge in gate insulating layer therein
US 20010041434 A1
Abstract
A method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer and a gate electrode, comprising the steps of forming the gate insulating layer on a semiconductor substrate, introducing an impurity into a channel region of the semiconductor substrate after forming the gate insulating layer, or forming a gate electrode on the gate insulating layer.
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Claims(12)
What is claimed is:
1. A method of manufacturing a non-volatile semiconductor memory device, including the steps of forming a gate insulating layer on a semiconductor substrate, forming a gate electrode on the gate insulating layer and introducing impurities into a channel region in a surface area of the semiconductor substrate beneath the gate insulating layer, characterized in that
in the step of forming the gate insulating layer, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer are formed and stacked in that order,
after the step of forming the gate insulating layer, the step of introducing impurities is carried out.
2. A method according to
claim 1
, further comprising a step of forming a refractory metal silicide layer on the polycrystalline silicon layer to form a gate electrode.
3. A method of forming a non-volatile semiconductor memory device, according to
claim 1
, wherein said second oxide layer is formed by a thermal oxidation process on a surface of the silicon nitride layer.
4. A method of manufacturing a non-volatile semiconductor memory device, including the steps of forming a gate insulating layer on a semiconductor substrate, forming a polycrystalline silicon layer on the gate insulating layer and introducing impurities into a channel region in a surface area of the semiconductor substrate beneath the gate insulating layer, characterized in that
in the step of forming the gate insulating layer, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer are formed and stacked in that order,
after the step of forming the polycrystalline silicon layer, the step of introducing impuritis is carried out.
5. A method according to
claim 4
, further comprising a step of forming a refractory metal silicide layer on the polycrystalline silicon layer to form a gate electrode.
6. A method of forming a non-volatile semiconductor memory device, according to
claim 4
, wherein said second oxide layer is formed by a thermal oxidation process on a surface of the silicon nitride layer.
7. A method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer including a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and a gate electrode, comprising the steps of
forming the gate insulating layer on a semiconductor substrate,
introducing an impurity into a channel region of the semiconductor substrate after forming the gate insulating layer, and
forming a gate electrode on the gate insulating layer.
8. A method according to
claim 7
, further comprising a step of forming a refractory metal silicide layer on the polycrystalline silicon layer to form a gate electrode.
9. A method according to 7, wherein said second silicon oxide layer is formed by oxidizing the silicon nitride layer.
10. A method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer including a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and a gate electrode, comprising the steps of
forming the gate insulating layer on a semiconductor substrate,
forming a polycrystalline silicon layer composed of the gate electrode on the gate insulating layer, and
introducing an impurity into a channel region of the semiconductor substrate after forming the polycrystalline silicon layer.
11. A method according to
claim 10
, further comprising a step of forming a refractory metal silicide layer on the polycrystalline silicon layer to form a gate electrode.
12. A method according to
claim 10
, wherein said second silicon oxide layer is formed by oxidizing the silicon nitride layer.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a method of manufacturing an electrically programmable non-volatile semiconductor memory device, more particularly a method of manufacturing a non-volatile semiconductor memory device with a threshold voltage which is controlled by impurity implantation in a channel region.
  • [0003]
    2. Description of the Related Art
  • [0004]
    In recent years, there has been much activity in development of flash EEPROMs. There are now mainly two types of flash memory EEPROMs. One is the floating gate type flash EEPROM, which can erase and program data by controlling the charge stored in a floating gate formed between a gate insulating layer and a controlling gate via an insulating layer.
  • [0005]
    The other is the metal-oxide-nitride-oxide-semiconductor (MONOS) type flash EEPROM, which can erase and program data by controlling the charge stored in a gate insulating layer including a nitride layer.
  • [0006]
    Further, flash EEPROMs may be classified by the arrangement of the memory cell or the means for programming into a common-source, parallel-array type (NOR type), a separate-source, parallel-array type (AND type), a series type (NAND type), a divided-bit-line, parallel array type (DINOR type), and so on.
  • [0007]
    A flash memory requires implantation of impurities into a channel region in order to control the threshold voltage or to make a depletion mode transistor. However, the impurities doped in the channel region are re-diffused by the heating process after forming the gate insulating layer, so the profile of the impurities is modified. This prevents the fabrication of high density memory devices.
  • [0008]
    A MONOS type flash memory, in particular, requires a depletion mode transistor, so punch through occurs easily and makes fabrication of a high density memory device difficult.
  • SUMMARY OF THE INVENTION
  • [0009]
    An object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device which can maintain its impurity profile in its channel region and therefore enables fabrication of a high density memory device.
  • [0010]
    According to one aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer and a gate electrode, comprising the steps of forming the gate insulating layer on a semiconductor substrate, introducing an impurity into a channel region of the semiconductor substrate after forming the gate insulating layer, and forming a gate electrode on the gate insulating layer.
  • [0011]
    According to another aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer and a gate electrode, comprising the steps of forming the gate insulating layer on a semiconductor substrate, forming a polycrystalline silicon layer composed of the gate electrode on the gate insulating layer, and introducing an impurity into a channel region of the semiconductor substrate after forming the polycrystalline silicon layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0012]
    These and other objects and features of the present invention will become clear from the following description of the present invention referring to the accompanying drawings, in which:
  • [0013]
    [0013]FIG. 1 is a sectional view of a memory cell of a MONOS type non-volatile semiconductor memory device;
  • [0014]
    [0014]FIGS. 2A to 2I are sectional views of a memory cell of a MONOS type non-volatile semiconductor memory device at various stages of a manufacturing method in the related art;
  • [0015]
    [0015]FIG. 3 is a view showing the impurity profile in the MONOS type non-volatile semiconductor memory device shown in FIGS. 2A to 2I;
  • [0016]
    [0016]FIGS. 4A to 4I are cross-sectional views of a memory cell of the MONOS type non-volatile semiconductor memory device shown in FIG. 1 at other stages of the manufacturing method according to the present invention; and
  • [0017]
    [0017]FIG. 5 is a view showing the impurity profile in the MONOS type non-volatile semiconductor memory device shown in FIGS. 4A to 4I.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0018]
    Before describing the preferred embodiments of the present invention, the related arts will be described for background with reference to the drawings.
  • [0019]
    [0019]FIG. 1 is a view showing the basic configuration of a MONOS type non-volatile semiconductor memory device.
  • [0020]
    As shown in FIG. 1, the MONOS type non-volatile semiconductor memory device 10 has two n+ diffusion regions 12 a, 12 b and two ndiffusion regions which serve as the source and drain in a semiconductor substrate, a gate insulating layer 14 formed on the substrate layer 11, and a control gate 15 formed on the gate insulating layer 14. Side walls 16 are formed on each side of the control gate 15 and an insulating layer 17 covers the gate insulating layer 14, control gate 15, and side walls 16. Interconnections 19 a, 19 b composed of aluminum are connected to the n+ diffusion regions 12 a, 12 b via contact holes 18 a, 18 b formed through the insulating layer 17. An n+ impurity such as phosphorus is implanted in a channel region 11A in the substrate 11 to control the threshold voltage or to create a depletion mode transistor. In FIG. 1, reference numeral 20 shows a junction isolation area (LOCOS).
  • [0021]
    The gate insulating layer 14 is composed of a first oxide layer (tunnel oxide) 141 which is composed of SiO2, a silicon nitride (Si3N4) layer 142 on the first oxide layer 141, and a second oxide layer 143 which is composed of SiO2 on the silicon nitride layer 142.
  • [0022]
    The control gate 15 is composed of a polycrystalline silicon layer 151 and a refractory metal silicide layer 152 such as tungsten.
  • [0023]
    Data is stored in the MONOS type non-volatile semiconductor memory by the accumulation of a charge in the silicon nitride layer 142 of the gate insulating layer 14. The threshold voltage in the write and erase mode is controlled, that is, the amount of the charge is controlled, by changing the voltage applied to the control gate 15.
  • [0024]
    Next, referring to FIGS. 2A to 2I, a method of manufacturing the MONOS non-volatile semiconductor device 10 described above as a related art will be explained.
  • [0025]
    First, as shown in FIG. 2A, a field oxide layer 20 is grown on the substrate 11 to a thickness of 400 nm by thermal oxidation of the substrate 11 at 950° C. for about 4 hours.
  • [0026]
    Next, an n-type impurity such as phosphorus is implanted in the substrate 11 between the field oxide layers 20.
  • [0027]
    The oxide layer on the substrate 11 between the field oxide layers 20 is removed, then a tunnel oxide layer 141 is grown to a thickness of 2 nm by thermal oxidation at 750° C. for about 1 minute.
  • [0028]
    As shown in FIG. 2B, a silicon nitride layer 142 is deposited on the tunnel oxide layer 141 to a thickness of 5 to 20 nm by low pressure chemical vapor deposition.
  • [0029]
    Next, as shown in FIG. 2C, a top oxide layer 143 is formed to a thickness of 4 nm by thermal oxidation of the surface of the silicon nitride layer 142, using, for example, pyrogenic oxide at 950° C. for 50 minutes.
  • [0030]
    Next, as shown in FIG. 2D, a polycrystalline silicon layer 151 of the control gate 15 is deposited by the CVD method etc. The thickness of the polycrystalline silicon layer 151 is not limited, but is preferably less than about 200 nm.
  • [0031]
    As shown in FIG. 2E, after forming the polycrystalline silicon layer 151, a tungsten silicide layer 152 is formed on the polycrystalline silicon layer 151 by the CVD method.
  • [0032]
    Next, as shown in FIG. 2F, a mask 30 is formed on the area where the gate electrode is to be formed, then the control gate 15 is patterned in the shape of a gate electrode as shown in FIG. 2G by etching, using reactive ion etching (RIE) etc., the silicide layer 152 and the polycrystalline silicon layer 151.
  • [0033]
    Next, as shown in FIG. 2H, n-type ions (n) such as phosphorus (P) or arsenic (As) are implanted, whereby low impurity concentration regions 13 a, 13 b serving as the LDD are created. Then a silicon oxide layer is deposited by CVD and etched by anisotropic etching, so side walls are formed beside the gate insulating layer 14.
  • [0034]
    n+ type ions such as phosphorus (P) or arsenic (As) are implanted at 25 keV at a dosage of 1×1015 cm2 to 5×1015/cm2, whereby high impurity concentration regions 13 a, 13 b serving as the source and drain are created.
  • [0035]
    Then annealing is performed to activate the impurities.
  • [0036]
    Next, as shown in FIG. 2I, after forming the insulating layer 17 on the surface of the substrate, contact holes 18 a, 18 b are formed through the insulating layer 17 to reach the n+ diffusion regions 12 a, 12 b, and aluminum interconnections 19 a, 19 b are formed, whereby the non-volatile semiconductor memory device 10 as shown in FIG. 1 is completed.
  • [0037]
    The forming-annealing process is performed at 400° C. for about 60 minutes.
  • [0038]
    The method of manufacturing the MONOS type non-volatile semiconductor memory device shown in FIGS. 2A to 2I has disadvantages, however. Since the impurities are implanted into the channel region 11A before forming the gate insulating layer 14, the impurity profile of the channel region may become distorted as shown in FIG. 3 due to the heat process for forming the gate insulating layer 14.
  • [0039]
    This disadvantage will be explained in more detail as follows. The top oxide layer 143 of the gate insulating layer 14 is formed by thermal oxidation of the silicon nitride layer 142. The thickness of the top oxide layer 143 must be about 2 to 6 nm in a MONOS type non-volatile semiconductor memory device. The heat process to produce the top oxide layer 143 should processing at 950° C. for 30 to 80 minutes. It is necessary to maintain the impurity profile in the channel region 11A in the case of a semiconductor device having fine dimensions, but the profile may become distorted when forming the top oxide layer 143. This prevents the formation of a high density memory device.
  • [0040]
    A MONOS type in particular requires a depletion type transistor, so punch-through occurs easily and reduction of the cell size is harder than another type of memory device.
  • [0041]
    Next, a preferred embodiment of method of manufacturing a MONOS type semiconductor memory device according to the present invention will be described with reference to FIGS. 4A to 4I.
  • [0042]
    First, as shown in FIG. 4A, a field oxide layer 20 is formed on the substrate 11 to a thickness of 400 nm by thermal oxidation of the substrate 11 at 950° C. for about 4 hours.
  • [0043]
    The oxide layer on the surface of the substrate 11 between the field oxide layers 20 is removed, then a tunnel oxide layer 141 is grown to a thickness of 2 nm by thermal oxidation at 7504° C. for about 1 minute.
  • [0044]
    As shown in FIG. 4B, a silicon nitride layer 142 is deposited on the tunnel oxide layer 141 to a thickness of 5 to 20 nm by low pressure chemical vapor deposition.
  • [0045]
    Next, as shown in FIG. 4C, a top oxide layer 143 is formed to a thickness of 4 nm by thermal oxidation for oxidizing the surface of the silicon nitride layer 142 using for example pyrogenic oxide at 950° C. for 50 minutes.
  • [0046]
    Next, as shown in FIG. 4D, the polycrystalline silicon layer 151 of the control gate 15 is formed by CVD etc. The thickness of the polycrystalline silicon layer 151 is not limited, but preferably is less than about 200 nm.
  • [0047]
    Next, an impurity such as phosphorus is implanted at a dosage of 3.0×1012/cm2 at an energy of 35 keV in the substrate 11 between the field oxide layers 20.
  • [0048]
    As shown in FIG. 4E, a tungsten silicide layer 152 is formed on the polycrystalline silicon layer 151 by CVD.
  • [0049]
    Next, as shown in FIG. 4F, a mask 30 is formed on the area where the gate electrode is to be formed, then the control gate 15 is patterned in the shape of a gate electrode as shown in FIG. 4G by etching the silicide layer 152 and the polycrystalline silicon layer 151 using for example RIE.
  • [0050]
    Next, as shown in FIG. 4H, n-type ions (n) such as phosphorus (P) or arsenic (As) are implanted, whereby low impurity concentration regions 13 a, 13 b serving as LDD are formed. Then, a silicon oxide layer is deposited by CVD and etched by anisotropic etching, whereby side walls 16 a, 16 b are formed on each side of the gate insulating layer 14.
  • [0051]
    n+ type ions such as phosphorus (P) or arsenic (As) are implanted at 25 keV at a dosage of 1×1015 to 5.0×1015/cm2, whereby high impurity concentration regions 12 a, 12 b serving as the source and drain are created.
  • [0052]
    Then, annealing is performed to activate the impurities.
  • [0053]
    Next, as shown in FIG. 4I, an insulating layer 17 is formed on the surface of the substrate, contact holes 18 a, 18 b are formed through the insulating layer 17 to reach the n+ diffusion regions 12 a, 12 b, and aluminum interconnections 19 a, 19 b are formed, thereby completing the non-volatile semiconductor memory device 10 as shown in FIG. 1.
  • [0054]
    A forming-annealing process is performed at 400° C. for about 60 minutes.
  • [0055]
    The MONOS type non-volatile semiconductor memory device fabricated as described above maintains its impurity profile as shown in FIG. 5 and includes the impurity in its gate insulating layer 14 at a concentration of 1×1017 to 1×1018/cm3 in contrast with the device of a related art shown in FIG. 3.
  • [0056]
    The MONOS type non-volatile semiconductor memory device fabricated by the process described in FIGS. 4A to 4I displays the same data retention as the MONOS type non-volatile semiconductor memory device fabricated by the process described in FIGS. 2A to 2I.
  • [0057]
    As described above, according to the embodiment shown in FIGS. 4A to 4I, an impurity is implanted in the channel region 11A after forming the gate insulating layer 14 and the polycrystalline silicon layer 151 constituting the control gate 15, so this MONOS type non-volatile semiconductor memory device has the advantages that the impurity profile in the channel region 11A can be maintained and the size of the memory cells can be reduced.
  • [0058]
    In addition, the impurity is introduced into the channel region 11A after forming the polycrystalline silicon layer 151, so a hydrofluoric acid solution can be used for later cleaning and contamination with organic compounds and heavy metals can be avoided.
  • [0059]
    Further, there is the advantage that the silicon nitride layer 142 sustains damage by the ion implantation etc., which increases the traps in the silicon nitride layer 142.
  • [0060]
    In the above embodiment, the impurity implantation was conducted after forming the gate insulating layer 14, but this can also be done after forming the polycrystalline silicon layer 151 constituting the gate electrode 15.
  • [0061]
    Note that the present invention is not limited to the above embodiments and can be modified in various ways within the scope of the present invention.
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US20040069990 *Oct 15, 2002Apr 15, 2004Matrix Semiconductor, Inc.Thin film transistor with metal oxide layer and method of making same
US20050023644 *Aug 31, 2004Feb 3, 2005Denso CorporationStabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET
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Classifications
U.S. Classification438/591, 257/E29.156, 257/E29.309, 257/E21.423, 438/287, 438/289, 257/E21.21, 257/E21.267
International ClassificationH01L27/115, H01L21/8242, H01L29/792, H01L21/314, H01L21/8247, H01L21/336, H01L29/788, H01L29/49, H01L21/28, H01L27/108
Cooperative ClassificationH01L29/4933, H01L29/66833, H01L21/3143, H01L29/792, H01L21/28282
European ClassificationH01L29/66M6T6F18, H01L29/49C2B, H01L21/28G, H01L29/792
Legal Events
DateCodeEventDescription
Feb 14, 1997ASAssignment
Owner name: SONY CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAKAMURA, AKIHIRO;REEL/FRAME:008357/0361
Effective date: 19970129
Dec 21, 2005REMIMaintenance fee reminder mailed
Jun 5, 2006LAPSLapse for failure to pay maintenance fees
Aug 1, 2006FPExpired due to failure to pay maintenance fee
Effective date: 20060604