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Publication numberUS20010041447 A1
Publication typeApplication
Application numberUS 08/954,175
Publication dateNov 15, 2001
Filing dateOct 20, 1997
Priority dateOct 20, 1997
Also published asUS6399505
Publication number08954175, 954175, US 2001/0041447 A1, US 2001/041447 A1, US 20010041447 A1, US 20010041447A1, US 2001041447 A1, US 2001041447A1, US-A1-20010041447, US-A1-2001041447, US2001/0041447A1, US2001/041447A1, US20010041447 A1, US20010041447A1, US2001041447 A1, US2001041447A1
InventorsTakeshi Nogami
Original AssigneeTakeshi Nogami
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method and system for copper interconnect formation
US 20010041447 A1
Abstract
A system and method for reducing contamination in a semiconductor device formed on a substrate is disclosed. The method and system include providing a barrier metal layer on the substrate. A first portion of the barrier metal layer is thinner than a second portion of the barrier metal layer. The method and system further include removing the first portion of the barrier metal layer.
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Claims(13)
What is claimed is:
1. A method for reducing contamination in a semiconductor device formed on a substrate comprising the steps of:
providing a barrier metal layer on the substrate, a first portion of the barrier metal layer being thinner than a second portion of the barrier metal layer; and
removing the first portion of the barrier metal layer.
2. The method of
claim 1
wherein the substrate further includes a center, an edge, a front, and a back; the first portion of the barrier metal layer being near the substrate edge and back, the second portion of the barrier metal layer being near the substrate center.
3. The method of
claim 2
further comprising the steps of:
providing a seed layer located near the center of the substrate.
4. The method of
claim 3
wherein the step of removing the portion of the barrier metal layer near the substrate edge and substrate back further comprises the step of:
etching the first portion of the barrier metal layer using an etching gas.
5. The method of
claim 4
wherein the barrier metal layer further comprises tungsten nitride; and the etching gas further comprises NF3.
6. The method of
claim 4
wherein the barrier metal layer further comprises titanium nitride; and the etching gas further comprises chlorine.
7. A system for reducing contamination in a semiconductor device formed on a substrate comprising:
means for providing a barrier metal layer on the substrate, a first portion of the barrier metal layer being thinner than a second portion of the barrier metal layer; and
means for removing the first portion of the barrier metal layer.
8. The system of
claim 7
wherein the substrate further includes a center, an edge, and a back; and the first portion of the barrier metal layer being near the substrate edge and back, the second portion of the barrier metal layer being near the substrate center.
9. The system of
claim 8
further comprising:
means for providing a seed layer located near the substrate center.
10. The system of
claim 9
further comprising:
a base for supporting the substrate at the back of the substrate.
11. The system of
claim 10
wherein the means for removing the first portion of the barrier further comprise:
means for etching the barrier metal layer using an etching gas.
12. The system of
claim 11
wherein the barrier metal layer further comprises tungsten nitride; and the etching gas further comprises NF3.
13. The system of
claim 11
wherein the barrier metal layer further comprises titanium nitride; and the etching gas further comprises chlorine.
Description
FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor processing and more particularly to a method and system for reducing the contamination due to copper interconnect formation.

BACKGROUND OF THE INVENTION

[0002] Copper interconnects can be used formed during semiconductor processing. In forming copper interconnects, for a trench is first provided in the silicon substrate. Next, a barrier metal is typically deposited to prevent the copper to be used in an interconnect or via from migrating. Then, copper plating is performed, filling the trench and providing the interconnect.

[0003] Typically, the barrier metals that are used also work as a seed layer for copper. Such barrier metals are used to allow the growth of the copper on the barrier metal in the trench or the via. If barrier metals which cannot act as a seed layer are used, the copper will not properly grow in the trench or via unless a separate seed layer is provided.

[0004] Although the above process forms copper interconnects, the barrier metal is deposited at the edge and rear of the silicon substrate as well as in the trenches or vias. Because the barrier metal acts as a seed layer for copper, a copper film also develops at the edge and rear of the substrate during copper plating. Because this copper film is thin, it does not adhere well to the silicon substrate and peels during processing. Pieces of the peeled copper film may then contaminate the circuitry formed towards the center of the silicon substrate.

[0005] Accordingly, what is needed is a system and method for providing copper interconnects and vias without introducing copper contamination due to films formed at the edge of the substrate. The present invention addresses such a need.

SUMMARY OF THE INVENTION

[0006] The present invention provides a method and system for reducing contamination in a semiconductor device formed on a substrate. A first portion of the barrier metal layer is thinner than a second portion of the barrier metal layer. The method and system further comprise removing the first portion of the barrier metal layer.

[0007] According to the system and method disclosed herein, the present invention reduce copper contamination, thereby increasing overall system performance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram of a conventional system for providing copper interconnects.

[0009]FIG. 2A is a block diagram of a system for providing copper interconnects in accordance with the method and system just after deposition of a barrier metal layer.

[0010]FIG. 2B is a block diagram of a system for providing copper interconnects in accordance with the method and system during etching.

[0011]FIG. 2C is a block diagram of a system for providing copper interconnects in accordance with the method and system after etching.

DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention relates to an improvement in semiconductor processing. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.

[0013]FIG. 1 is a block diagram of a conventional substrate during formation of copper interconnects and vias. The substrate 12 is typically silicon. The substrate is placed on an apparatus including a base 18. After formation of trenches or via holes, not shown, a layer of barrier metal 14 is deposited onto the substrate 14. The barrier metal layer 14 is used to block the migration of copper outside of the interconnects and vias. Typically, the barrier metal layer 14 is formed through chemical vapor deposition (“CVD”). In some instances a seed layer 16 is also grown on the barrier metal layer 14. After the seed layer 16 is provided, a copper layer, not shown, is deposited. Typically, the copper layer is formed by electroplating copper.

[0014] Although the system shown in FIG. 1 allows formation of copper interconnects and vias, those with ordinary skill in the art will realize that copper deposited during formation of the interconnects and vias will contaminate the structures formed on the substrate 12. The barrier metal layer 14 covers not only the open portion, but also covers the edge and a portion of the back of the substrate 12. Thus, a thin layer of the barrier metal chosen for the barrier metal layer 14 is present at the edge and rear of the substrate 12. Typically, the barrier metal layer 14 is approximately 300 Angstroms near the center of the substrate 12 and approximately 30 Angstroms at the edge and rear of the substrate 12.

[0015] The barrier metal layer 14 can typically act as a seed layer for copper. For example, tungsten-nitride (WNx where x is an integer) or titanium-nitride (TiN) is typically used to form the barrier metal layer 14. This feature of the barrier metal layer 14 is important in aiding the growth of the copper to form the interconnects and vias. Because the barrier metal layer 14 is a seed layer, the copper plating causes a thin layer of copper, not shown, to grow on the thin portion of the barrier metal layer 14, at the edge and back of the substrate 12. The thin copper layer does not adhere well to the substrate 12. As a result, the thin copper layer peels off of the edge and back of the substrate 12, contaminating the circuits formed on the substrate 12.

[0016] The present invention provides for a method and system for removing a portion of the barrier metal layer. The present invention will be described in terms of a particular process for etching a portion of the barrier metal layer. However, one of ordinary skill in the art will readily recognize that this method and system will operate effectively for other types of methods for removing the portion of the barrier metal layer.

[0017] To more particularly illustrate the method and system in accordance with the present invention, refer now to FIG. 2A depicting a block diagram of one embodiment of such a system 100 just after deposition of a barrier metal. The system 100 of the present invention includes a base 118. The substrate 112 is placed on the base 118. Trenches or vias are then formed in the substrate 112. Next, a barrier metal layer 114 is deposited to prevent diffusion of any copper deposited later. In a preferred embodiment, the barrier metal layer 114 is deposited using CVD. Typically, the barrier metal layer 114 is much thicker near the center of the substrate 112 than near the edge. In a preferred embodiment, the barrier metal layer 114 is approximately three hundred Angstroms near the center at approximately thirty Angstroms near the edge of the substrate 114. Generally, the barrier metal layer 114 is on the order of ten times thicker at the center of the substrate 112 than at the edge and back of the substrate 112. After deposition of the barrier metal layer 114, a seed layer 116 is deposited. The seed layer 116 improves adhesion of the copper layer, not shown, which is to be deposited later. FIG. 2B depicts the system 100 after deposition of the seed layer 116.

[0018] In accordance with the method and system, the barrier metal layer 114 is etched after deposition of the seed layer 116. This etch removes the thin portions of the barrier metal layer 114 at the edge and back of the substrate. In a preferred embodiment, if the barrier metal layer 114 is composed of tungsten nitride, the etching gas is preferably NF3. In another embodiment, if the barrier metal layer 114 is composed of titanium nitride, the etching gas used may be chlorine.

[0019] Etching the barrier metal layer 114 removes the portion of the barrier metal layer 114 at the edge and back of the substrate 112. Because of the presence of the seed layer 116, the metal in the central portion of the substrate 112 is not significantly etched. This removes the thinner portion of the barrier metal layer 114. Typically, the thinner portion of the barrier metal layer 114 is at the edge and back of the substrate 112. Thus, the etch removes the portion of the barrier metal layer 114 to which copper would otherwise adhere. Because of the seed layer 116, the thinner portions of the barrier metal layer 114 have been removed while the thicker portion of the barrier metal layer 114 lying beneath the seed layer 116 remains substantially unchanged. Thus, in accordance with the method and system, the thin portion of the barrier metal layer 114 will be removed.

[0020] Refer now to FIG. 2C, depicting one embodiment of the system 100 after etching of the barrier metal layer 114. The thin portions of the barrier metal layer 114 have been removed, leaving only the thicker central portion lying beneath the seed layer 116. Because the portion of the barrier metal layer at the edge and back of the substrate 114 was etched while the portion of the barrier metal layer at the center of the substrate 114 was protected by the seed layer 116, the portion of the barrier metal layer 114 remaining can still prevent diffusion of the copper, not shown, that will be plated later. In addition, because the portion of the barrier metal layer 114 at the edge and back of the substrate 112 has been removed, there is no seed layer for copper to adhere to at these portions of the substrate. As a result, deposition of copper at the edges and back of the substrate is greatly reduced. The contamination due to copper peeling off of the substrate 112 is thereby reduced.

[0021] A method and system has been disclosed for providing copper interconnects with reduced contamination due to copper deposited at the edge or rear of the substrate.

[0022] Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6413436 *Nov 10, 1999Jul 2, 2002Semitool, Inc.Selective treatment of the surface of a microelectronic workpiece
Classifications
U.S. Classification438/706, 257/E21.584
International ClassificationH01L21/768
Cooperative ClassificationH01L21/76843, H01L21/76873
European ClassificationH01L21/768C3B, H01L21/768C3S2
Legal Events
DateCodeEventDescription
Nov 6, 2013FPAYFee payment
Year of fee payment: 12
Nov 20, 2009FPAYFee payment
Year of fee payment: 8
Nov 23, 2005FPAYFee payment
Year of fee payment: 4
Oct 20, 1997ASAssignment
Owner name: ADVANCED MICRO DEVICES, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NOGAMI, TAKESHI;REEL/FRAME:008786/0566
Effective date: 19971016