US20010042776A1 - Method of wire bonding for small clearance - Google Patents

Method of wire bonding for small clearance Download PDF

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Publication number
US20010042776A1
US20010042776A1 US09/577,686 US57768600A US2001042776A1 US 20010042776 A1 US20010042776 A1 US 20010042776A1 US 57768600 A US57768600 A US 57768600A US 2001042776 A1 US2001042776 A1 US 2001042776A1
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Prior art keywords
chip
pad
capillary
bump
small clearance
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US09/577,686
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US6321976B1 (en
Inventor
Randy Lo
Han-Ping Pu
Tony Yuan
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority to US09/577,686 priority Critical patent/US6321976B1/en
Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD. reassignment SILICONWARE PRECISION INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LO, RANDY H.Y., PU, HAN-PING, YUAN, TONY
Publication of US20010042776A1 publication Critical patent/US20010042776A1/en
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004—Wire welding
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding

Definitions

  • the present invention relates to a method of wire bonding for small clearance, and more specifically, to a method of employing a conductive bump over the pad of the chip to prevent the capillary from colliding with the chip during the three-dimensional package wiring process.
  • VLSI very large scale integrated circuit
  • the pad of the chip is soldered to the lead frame by wiring, and when the chips are adhered in three dimensional manner, the capillary may collide with some higher chips to damage the chips and the capillary because the size of the chip is similar while wiring.
  • the steps of wiring comprises: (1) the capillary solders the wire on a pad by a thermal process or super sonic technique; (2) the capillary rises to form a vertical wire; (3) the capillary translates the wire to the lead frame; and (4) another end of the wire is soldered onto the lead frame.
  • the reverse loop D has to add to the stroke of the capillary to enhance the characteristic of the wire. This step is out of question in single chip package wiring. However, in the three dimensional package wiring, the effect of the reverse loop D has to take into consideration, as shown in FIG. 1. The sizes of the upper and lower chips 11 and 12 are almost the same in package application.
  • the capillary 14 may collide with the chip 11 to damage the capillary 14 and the chip 11 resulting in failure of wiring if the distance A from the pad 13 in the chip 12 to the rim of the chip 11 is very small and one of the reverse loop D, the radius C of the capillary, and the thickness E of the chip 11 is too big, or the distance A from the center of the pad in the chip 12 to the rim of the chip 11 is too small.
  • the solution of the prior art is to select smaller capillary 14 .
  • the appropriate capillary can not be found if the distance A between the pad 13 in the chip 12 and the rim of the chip 11 is smaller than 0.2 mm.
  • An object of the present invention is to provide a method of wire bonding for small clearance, which overcomes the disadvantage in the prior arts that the distance A between the center of the pad in the chip 12 and the rim of the chip 11 is too small to perform the wiring process by the conventional wiring equipment.
  • the method of the present invention can prevent the capillary from colliding with the chip during the three-dimensional package wiring process.
  • a conductive bump 15 is first formed over the pad 13 of the chip 12 and then the chip is connected to the lead frame by the conventional wiring method.
  • the height H of the bump 15 is determined by the reverse loop D, the radius C of the capillary 14 , the thickness E of the chip 11 , and the distance A between the pad 13 in the chip 12 and the rim of the chip 11 .
  • FIG. 1 is a schematic diagram illustrating the stub structure by a conventional chip wiring method
  • FIG. 2 is a schematic diagram illustrating the stub structure by a new chip wiring method according to the present invention.
  • the stub structure used in the wiring method for small clearance comprises a body, which at least consists of the chips 11 and 12 .
  • the present invention is characterized as that the pad 13 is covered by a conductive bump 15 , which is made of one conductive material selected from metal, alloy, polymer and the mixture.
  • the present invention increases the space for the reverse loop D of the capillary 14 with respect to the prior art shown in FIG. 1.
  • the constraint to limit the clearance (distance A) between the chips is allowed of more wide range so as to overcome the failure of wiring in three dimensional package for small clearance.
  • the pad 13 of the chip 12 is first covered with the conductive bump 15 , and then the chip is connected to the lead frame by the conventional wiring process.
  • the height H of the bump 15 is determined by the reverse loop D, the radius C of the capillary 14 , the thickness E of the chip 11 , and the distance A between the pad 13 in the chip 12 and the rim of the chip 11 .
  • the present invention provides the stability of the prior art and meets the requirement of the present and future process.
  • the present invention employs the convention technique to overcome the present problem in new process such that the issue that the capillary may collide with the chip is solved in three dimensional package for small clearance.
  • the capillary may not collide with the chip is solved in the three dimensional package for small clearance
  • the present equipment is enough to implement the method of the present invention so as to save the cost

Abstract

A method of wire bonding for small clearance is disclosed. The method employs a conductive bump over the pad of the chip to prevent the capillary from colliding with the chip during the three-dimensional package wiring process The conventional constraint which limits the clearance to greater than 0.2 mm so as to find the appropriate capillary is overcome in this method.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a method of wire bonding for small clearance, and more specifically, to a method of employing a conductive bump over the pad of the chip to prevent the capillary from colliding with the chip during the three-dimensional package wiring process. [0001]
    • BACKGROUND OF THE INVENTION
  • At present, the commercialized electronic products have a trend with light-weight, and thin, short, and small size. Therefore, very large scale integrated circuit (VLSI) have been widely used. As the development of the semiconductor, the total number of transistors in the die greatly increases, and at the same time, the requirement the density of package becomes more and more strictly. The three dimensional package is thus developed to greatly increase the package density to overcome the issue. [0002]
  • However, during packaging, the pad of the chip is soldered to the lead frame by wiring, and when the chips are adhered in three dimensional manner, the capillary may collide with some higher chips to damage the chips and the capillary because the size of the chip is similar while wiring. [0003]
  • In the prior art, the steps of wiring comprises: (1) the capillary solders the wire on a pad by a thermal process or super sonic technique; (2) the capillary rises to form a vertical wire; (3) the capillary translates the wire to the lead frame; and (4) another end of the wire is soldered onto the lead frame. [0004]
  • For the process which needs a long wire, the reverse loop D has to add to the stroke of the capillary to enhance the characteristic of the wire. This step is out of question in single chip package wiring. However, in the three dimensional package wiring, the effect of the reverse loop D has to take into consideration, as shown in FIG. 1. The sizes of the upper and [0005] lower chips 11 and 12 are almost the same in package application. Therefore, when the two chips 11 and 12 are assembled together by soldering process, the capillary 14 may collide with the chip 11 to damage the capillary 14 and the chip 11 resulting in failure of wiring if the distance A from the pad 13 in the chip 12 to the rim of the chip 11 is very small and one of the reverse loop D, the radius C of the capillary, and the thickness E of the chip 11 is too big, or the distance A from the center of the pad in the chip 12 to the rim of the chip 11 is too small. The solution of the prior art is to select smaller capillary 14. However, there is a disadvantage that the appropriate capillary can not be found if the distance A between the pad 13 in the chip 12 and the rim of the chip 11 is smaller than 0.2 mm.
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a method of wire bonding for small clearance, which overcomes the disadvantage in the prior arts that the distance A between the center of the pad in the [0006] chip 12 and the rim of the chip 11 is too small to perform the wiring process by the conventional wiring equipment. The method of the present invention can prevent the capillary from colliding with the chip during the three-dimensional package wiring process. In the present invention, a conductive bump 15 is first formed over the pad 13 of the chip 12 and then the chip is connected to the lead frame by the conventional wiring method. The height H of the bump 15 is determined by the reverse loop D, the radius C of the capillary 14, the thickness E of the chip 11, and the distance A between the pad 13 in the chip 12 and the rim of the chip 11.
  • Other features and advantages of the invention will become apparent from the following description of the invention that refers to the accompanying drawings.[0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram illustrating the stub structure by a conventional chip wiring method; and [0008]
  • FIG. 2 is a schematic diagram illustrating the stub structure by a new chip wiring method according to the present invention.[0009]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • When the distance A is too small, as shown in FIG. 1, it is possible to overcome the issue that the [0010] capillary 14 may collide with the chip 11 by increasing the space for the reverse loop D of the capillary 14. With reference to FIG. 2, the stub structure used in the wiring method for small clearance according to the present invention comprises a body, which at least consists of the chips 11 and 12. The present invention is characterized as that the pad 13 is covered by a conductive bump 15, which is made of one conductive material selected from metal, alloy, polymer and the mixture. Apparently, the present invention increases the space for the reverse loop D of the capillary 14 with respect to the prior art shown in FIG. 1. The constraint to limit the clearance (distance A) between the chips is allowed of more wide range so as to overcome the failure of wiring in three dimensional package for small clearance.
  • In the steps of the method of the present invention, the [0011] pad 13 of the chip 12 is first covered with the conductive bump 15, and then the chip is connected to the lead frame by the conventional wiring process. The height H of the bump 15 is determined by the reverse loop D, the radius C of the capillary 14, the thickness E of the chip 11, and the distance A between the pad 13 in the chip 12 and the rim of the chip 11. The present invention provides the stability of the prior art and meets the requirement of the present and future process.
  • The present invention employs the convention technique to overcome the present problem in new process such that the issue that the capillary may collide with the chip is solved in three dimensional package for small clearance. [0012]
  • The present invention provides the advantages: [0013]
  • (1) the capillary may not collide with the chip is solved in the three dimensional package for small clearance; [0014]
  • (2) the clearance between the chip and the pad is allowed smaller than 0.2 mm in the three dimensional package; [0015]
  • (3) the present equipment is enough to implement the method of the present invention so as to save the cost; and [0016]
  • (4) only one step is added in the manufacturing process to keep the stability of the prior art. [0017]
  • Although only the preferred embodiments of this invention were shown and described in the above description, it is requested that any modification or combination that comes within the spirit of this invention be protected. [0018]

Claims (10)

What is claimed is:
1. A method of wire bonding for small clearance, using a body comprising a plurality of chips, wherein said method is characterized as: a conductive bump with an appropriate height is first formed between a pad and a wire during a wiring process for connecting said pad in one side of said body to a lead frame.
2. The method as claimed in
claim 1
, wherein said conductive bump is made of metal, alloy, polymer, or a mixture.
3. The method as claimed in
claim 2
, wherein said metal is selected from gold, aluminum, or copper.
4. The method as claimed in
claim 1
, wherein said bump is formed by evaporation, sputtering, etching, plating, printing, or stud bonding.
5. The method as claimed in
claim 1
, wherein said bump has a height determined by a type and a radius of said capillary, a reverse loop, a thickness of said chip, and a distance from a center of said pad to a rim of the chip.
6. A stub structure for wire bonding with small clearance, comprising a body with a plurality of chips, wherein said stub structure is characterized as: a conductive bump with an appropriate height is first formed between a pad and a wire during a wiring process for connecting said pad in one side of said body to a lead frame.
7. The stub structure as claimed in
claim 6
, wherein said conductive bump is made of metal, alloy, polymer, or a mixture.
8. The stub structure as claimed in
claim 7
, wherein said metal is selected from gold, aluminum, or copper.
9. The stub structure as claimed in
claim 6
, wherein said bump is formed by evaporation, sputtering, etching, plating, printing, or stud bonding.
10. The stub structure as claimed in
claim 6
, wherein said bump has a height determined by a type and a radius of said capillary, a reverse loop, a thickness of said chip, and a distance from a center of said pad to a rim of the chip.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130125390A1 (en) * 2010-08-10 2013-05-23 Kulicke And Soffa Industries, Inc. Wire loops, methods of forming wire loops, and related processes
US9673178B2 (en) * 2015-10-15 2017-06-06 Powertech Technology Inc. Method of forming package structure with dummy pads for bonding
JP2022047892A (en) * 2020-09-14 2022-03-25 三菱電機株式会社 Semiconductor device and manufacturing method thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6564449B1 (en) * 2000-11-07 2003-05-20 Advanced Semiconductor Engineering, Inc. Method of making wire connection in semiconductor device
US6900549B2 (en) * 2001-01-17 2005-05-31 Micron Technology, Inc. Semiconductor assembly without adhesive fillets
US6768212B2 (en) * 2002-01-24 2004-07-27 Texas Instruments Incorporated Semiconductor packages and methods for manufacturing such semiconductor packages
US6815836B2 (en) * 2003-03-24 2004-11-09 Texas Instruments Incorporated Wire bonding for thin semiconductor package
US8802555B2 (en) * 2011-03-23 2014-08-12 Stats Chippac Ltd. Integrated circuit packaging system with interconnects and method of manufacture thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
US4907734A (en) * 1988-10-28 1990-03-13 International Business Machines Corporation Method of bonding gold or gold alloy wire to lead tin solder
US5086335A (en) * 1990-07-31 1992-02-04 Hewlett-Packard Company Tape automated bonding system which facilitate repair
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5205463A (en) * 1992-06-05 1993-04-27 Kulicke And Soffa Investments, Inc. Method of making constant clearance flat link fine wire interconnections
US5311404A (en) * 1992-06-30 1994-05-10 Hughes Aircraft Company Electrical interconnection substrate with both wire bond and solder contacts
US5558270A (en) * 1995-01-06 1996-09-24 Kulicke And Soffa Investments, Inc Fine pitch capillary/wedge bonding tool
US5842628A (en) * 1995-04-10 1998-12-01 Fujitsu Limited Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method
US6001724A (en) * 1996-01-29 1999-12-14 Micron Technology, Inc. Method for forming bumps on a semiconductor die using applied voltage pulses to an aluminum wire
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
JP3344235B2 (en) * 1996-10-07 2002-11-11 株式会社デンソー Wire bonding method
US6144101A (en) * 1996-12-03 2000-11-07 Micron Technology, Inc. Flip chip down-bond: method and apparatus
US5938952A (en) * 1997-01-22 1999-08-17 Equilasers, Inc. Laser-driven microwelding apparatus and process
US6097087A (en) * 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US6075281A (en) * 1999-03-30 2000-06-13 Vanguard International Semiconductor Corporation Modified lead finger for wire bonding

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130125390A1 (en) * 2010-08-10 2013-05-23 Kulicke And Soffa Industries, Inc. Wire loops, methods of forming wire loops, and related processes
US9455544B2 (en) * 2010-08-10 2016-09-27 Kulicke And Soffa Industries, Inc. Wire loops, methods of forming wire loops, and related processes
US9673178B2 (en) * 2015-10-15 2017-06-06 Powertech Technology Inc. Method of forming package structure with dummy pads for bonding
JP2022047892A (en) * 2020-09-14 2022-03-25 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP7412310B2 (en) 2020-09-14 2024-01-12 三菱電機株式会社 Semiconductor device and its manufacturing method

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