US20010043074A1 - Test carrier with molded interconnect for testing semiconductor components - Google Patents
Test carrier with molded interconnect for testing semiconductor components Download PDFInfo
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- US20010043074A1 US20010043074A1 US09/143,300 US14330098A US2001043074A1 US 20010043074 A1 US20010043074 A1 US 20010043074A1 US 14330098 A US14330098 A US 14330098A US 2001043074 A1 US2001043074 A1 US 2001043074A1
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- interconnect
- contacts
- lead frame
- carrier
- component
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
- G01R1/0483—Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
Definitions
- This invention relates generally to semiconductor manufacture, and more particularly to an improved test carrier for temporarily packaging and testing semiconductor components, such as dice and chip scale packages.
- This invention also relates to a test system incorporating the carrier, and to a method for fabricating the carrier.
- semiconductor components such as bare dice and chip scale packages must be tested prior to shipment by semiconductor manufacturers. Since these components are relatively small and fragile, carriers have been developed for temporarily packaging the components for testing. The carriers permit electrical connections to be made between external contacts on the components, and testing equipment such as burn-in boards.
- the external contacts typically comprise planar or bumped bond pads.
- the external contacts typically comprise solder balls in a dense array, such as a ball grid array, or a fine ball grid array.
- An interconnect on the carrier includes contacts that make the temporary electrical connections with the external contacts on the components.
- the interconnect must provide power, ground and signal paths to the component. As the external contacts on the components become smaller and denser, it becomes more difficult to fabricate the carrier with the required number of electrical paths to the interconnect.
- the carrier must be reused multiple times in a production environment. Accordingly, it is desirable to make the carrier as damage resistant as possible. Incorporating the interconnect into the carrier, while maintaining a compact outline for the carrier is increasingly difficult.
- the fabrication process for the carrier must be capable of producing production quantities at reasonable costs. It would be advantageous to have the capability to fabricate carriers using conventional semiconductor fabrication processes. This would lower initial capital outlays for production equipment, and lower production costs.
- test carrier and a method for fabricating the carrier.
- the test carrier can be used to temporarily package and test semiconductor components, such as bare dice, and chip scale packages.
- the test carrier includes a base for retaining one or more components, and et lead frame molded to the base.
- the lead frame includes lead fingers which form internal signal traces and terminal contacts for the carrier.
- the carrier also includes an interconnect, which is attached to a mounting paddle of the lead frame and molded to the base.
- the interconnect includes contacts for electrically contacting external contacts on the component under test.
- the interconnect contacts are electrically connected to the lead fingers of the lead frame by wire bonding.
- the interconnect contacts can comprise etched pillars with penetrating projections.
- the interconnect contacts can comprise microbumps on a polymer film.
- the interconnect contacts can comprise recesses, or flat pads, covered with conductive layers.
- the carrier also includes a force applying member for biasing the component against the interconnect.
- the force applying mechanism includes a biasing member, such as a compressible elastomeric spring.
- the force applying mechanism also includes a lid, and one or more clips, which attach to the carrier base.
- multiple interconnects can be molded to a board having integrally formed clip members.
- laser machined conductive vias in the interconnect provide electrical paths for external contacts formed directly on the interconnect.
- the method for fabricating the carrier includes the initial step of attaching the interconnect to the lead frame. Following attachment, an elastomeric gasket can be placed on the interconnect and lead frame, to protect the interconnect, and portions of the lead fingers wherein wire bonds will be formed. Alternately, in place of an elastomeric gasket, a polymer layer, such as a thick film resist, can be applied to the interconnect prior to molding. During a molding step, the carrier base is molded to the lead frame and interconnect. Next, the gasket is removed, or the polymer layer is stripped, and the interconnect is wire bonded to the lead fingers. As another alternate wiring bonding can precede molding, and the wire bonds can be encapsulated. Finally, a trim and form step is performed to form exposed portions of the lead fingers into the terminal leads of the carrier.
- an elastomeric gasket can be placed on the interconnect and lead frame, to protect the interconnect, and portions of the lead fingers wherein wire bonds will be formed.
- a polymer layer such as
- a test system constructed in accordance with the invention includes the carrier and test circuitry.
- the test circuitry generates and transmits test signals through the carrier to the component, and evaluates the resultant signals.
- the test system can also include a burn-in board which provides electrical interface between the carrier and test circuitry.
- FIG. 1 is a plan view of a test carrier constructed in accordance with the invention.
- FIG. 1A is a cross sectional view taken along section line 1 A- 1 A of FIG. 1;
- FIG. 2 is a side elevation view of the carrier
- FIG. 3 is an end view of the carrier
- FIG. 4 is a schematic plan view of a lead frame configured for fabricating multiple carriers
- FIG. 5 is an enlarged plan view taken along section line 5 - 5 of FIG. 4 of a portion of the lead frame;
- FIG. 5A is an enlarged plan view partially cut away taken along section line 5 A- 5 A of FIG. 5;
- FIG. 5B is a cross sectional view of the lead frame and interconnect taken along section line 5 B- 5 B of FIG. 5;
- FIG. 6 is an enlarged plan view of an interconnect of the carrier with a component under test superimposed thereon;
- FIG. 6A is an enlarged cross sectional view taken along section line 6 A- 6 A of FIG. 6, illustrating an interconnect contact electrically engaging a component contact;
- FIG. 6B is an enlarged cross sectional view equivalent to FIG. 6A of an alternate embodiment interconnect contact
- FIG. 6C is a plan view of the interconnect contact of FIG. 6B;
- FIG. 6C is enlarged cross sectional view equivalent to FIG. 6A of another alternate embodiment interconnect contact
- FIGS. 7 A- 7 F are schematic cross sectional views illustrating steps in a method for fabricating the carrier in accordance with the invention.
- FIGS. 8 A- 8 E are schematic cross sectional views illustrating steps in a method for fabricating an alternate embodiment carrier
- FIGS. 9 A- 9 D are schematic cross sectional views illustrating steps in a method for fabricating another alternate embodiment carrier
- FIG. 10A is a schematic perspective view of an alternate embodiment carrier.
- FIG. 10B is a cross sectional view taken along section line 10 B- 10 B of FIG. 10A.
- test carrier 10 constructed in accordance with the invention is illustrated.
- the carrier 10 is adapted to temporarily package a semiconductor component 16 (FIG. 1A) for testing and burn-in.
- the carrier 10 includes a base 12 , a lead frame 14 (FIG. 1A) and an interconnect 18 (FIG. 1A). As will be further explained, the lead frame 14 and interconnect 18 are molded to the base 12 .
- the carrier 10 also includes a force applying mechanism comprising a spring 20 (FIG. 1A), a lid 22 and a pair of clips 24 .
- the carrier 10 includes a plurality of terminal leads 26 in electrical communication with the interconnect 18 .
- the terminal leads 26 comprise trimmed and formed portions of the lead frame 14 . Further, the terminal leads 26 are adapted for electrical communication with test circuitry 27 (FIG. 2) of a test system.
- the test circuitry 27 generates test signals, and transmits the test signals to the terminal leads 26 and through the interconnect 18 to the component 16 .
- the test circuitry 27 also analyzes the resultant test signals transmitted from the component 16 . This permits various electrical characteristics of the component 16 to be evaluated.
- the carrier base 12 and terminal leads 26 have a configuration (i.e., size, peripheral outline, external leads) corresponding to that of a conventional semiconductor package.
- the carrier base 12 has the configuration of a small outline j-bend (SOJ) package.
- the carrier base 12 can have the configuration of other conventional packages such as single in line memory module (SIMM), dual in line package (DIP), quad flat pack (QFP), zig zag in line package (ZIP), or leadless chip carrier (LCC).
- SIMMM single in line memory module
- DIP dual in line package
- QFP quad flat pack
- ZIP zig zag in line package
- LCC leadless chip carrier
- he terminal leads 26 are located on opposing sides of the carrier base 12 .
- the terminal leads 26 can be located on more than two sides (e.g., three sides, four sides).
- the carrier base 12 can include solder balls in a ball grid array (BGA) or fine ball grid array (FBGA), or pins in a pin grid array (PGA).
- BGA ball grid array
- FBGA fine ball grid array
- PGA pin grid array
- the carrier base 12 and terminal leads 26 can also have a specialized configuration different than conventional semiconductor packages.
- the carrier base 12 is formed of plastic using a conventional injection molding process. Exemplary plastics include epoxy novolac resin, silicone, phenylsilane and thermoset plastics.
- the carrier base 12 includes channels 28 on either end for receiving the clips 24 .
- the carrier base 12 also includes a recess 30 . With the lid 22 attached to the carrier base 12 the recess 30 forms an enclosed cavity 32 (FIG. 1A) for the component 16 and spring 20 . Also, with the lid 22 attached to the carrier base 12 , the component 16 is pressed by the spring 20 against the interconnect 18 .
- the lid 22 and clips 24 are sized and shaped for mating physical engagement.
- the clips 24 include rectangular openings 34 (FIG. 1) which permit handling by a manual or automated tool.
- the clips 24 comprise a resilient metal or plastic material.
- the spring 20 can comprise a resilient elastomeric material such as silicone, butyl rubber, or fluorosilicone. Suitable elastomeric materials include “PORON” available from a Rogers Corporation subsidiary of Elkgrove Village, ILL. If desired, the elastomeric spring 20 can be secured to the lid 22 using an adhesive such as silicone. Rather than being formed of elastomeric materials, the spring 20 can comprise a resilient metal such as a belleville washer, or spring segment. Alternately, the spring 20 can comprise a compressible gas or liquid filled bladder. This type of bladder is available from Paratech of Frankfort, IL under the trademark “MAXI FORCE AIR BAG”.
- Assembly of the carrier 10 , with the component 16 therein, can be accomplished by attaching the component 16 to the lid 22 and spring 20 .
- the lid 22 and spring 20 can include a vacuum conduit 31 to enable attachment of the component 16 using a vacuum tool (not shown).
- the component 16 can then be aligned with the interconnect 18 and placed in contact therewith.
- Optical alignment techniques can be used during assembly of the carrier 10 .
- the lead frame 14 is shown prior to formation of the carrier base 12 .
- the lead frame 14 initially comprises a strip of material which includes multiple interconnect mounting sites 36 (FIG. 4).
- the lead frame 14 includes ten interconnect mounting sites 36 .
- this number is merely exemplary, and a greater or lesser number of interconnect mounting sites 36 can be employed.
- Each interconnect mounting site 36 can be used to mount an interconnect 18 to form a single carrier base 12 .
- the lead frame 14 can be cut or sheared into a plurality of separate bases 12 .
- Each carrier base 12 includes an integrally molded interconnect 18 substantially as shown in FIG. 1A.
- the lead frame 14 includes parallel spaced side rails 42 , 44 having multiple through openings 46 , 48 .
- the side rails 42 , 44 and openings 46 , 48 permit the lead frame 14 to be handled by automated transfer mechanisms associated with chip bonders, wire bonders, molds, trim and form machinery, and marking machinery.
- the lead frame 14 also include elongated openings 50 to facilitate singulation of the lead frame 14 into separate carriers 10 .
- the lead frame 14 can be formed of metal using a stamping process, or a chemical milling process. Suitable metals for the lead frame 14 include nickel-iron alloys (e.g., 42% Ni-58% Fe), clad materials (e.g., copper clad stainless steel), or copper alloys.
- each interconnect mounting site 36 includes a down set mounting paddle 38 .
- each interconnect mounting site 36 includes a pattern of lead fingers 40 .
- wires 80 (FIG. 1A) will be wire bonded to the lead fingers 40 and to bonding pads 52 on the interconnect 18 .
- the lead fingers 40 will form the internal signal traces for the carrier 10 .
- terminal portions of the lead fingers 40 will be trimmed and formed to form the terminal leads 26 (FIG. 1) of the carrier 10 .
- the lead fingers 40 can overlap the interconnect 18 to provide increased structural rigidity for supporting the interconnect 18 in the molded base 12 .
- the mounting paddle 38 can include cut outs 39 to accommodate formation of the overlapping lead fingers 40 during stamping or etching of the lead frame 14 .
- the mounting paddle 38 includes a planar surface configured to support the interconnect 18 .
- a backside of the interconnect 18 can be adhesively bonded to the mounting paddle 38 .
- the mounting paddle 38 has a peripheral shape which corresponds to a peripheral shape of the interconnect 18 .
- the mounting paddle 38 has a generally rectangular peripheral shape.
- the mounting paddle 38 can also be configured in other peripheral shapes, such as square.
- a peripheral size of the mounting paddle 38 can be slightly larger than a peripheral size of the interconnect 18 .
- the interconnect 18 can be attached to the mounting paddle 38 using an adhesive layer 54 .
- the adhesive layer 54 can comprise an epoxy, acrylic, silicone or polyimide material. Alternately, the adhesive layer 54 can comprise a polymer tape, such as “KAPTON” tape manufactured by DuPont.
- a manual or automated process can be employed for attaching the interconnect 18 to the mounting paddle 38 .
- a conventional chip bonder used in the production of conventional semiconductor packages for bonding dice to lead frames can be utilized.
- the mounting paddle 38 includes downset segments 56 which connect the mounting paddle to the siderails 42 , 44 (FIG. 5) of the lead frame 14 .
- a downset D of the mounting paddle 38 provides an offset for the mounting paddle 38 relative to the lead fingers 40 . This facilitates molding of the interconnect 18 into the plastic base 12 , and embeds the interconnect 18 within the molded plastic material of the base 12 .
- the downset mounting paddle 38 forms an exposed bottom surface of the base 12 . During a test procedure using the package 10 , the exposed surface of the mounting paddle 38 improves heat transfer from the interconnect 18 .
- the interconnect 18 includes patterns of interconnect contacts 58 which are configured to electrically connect to contacts 60 (FIG. 6A) on the component 16 .
- the component contacts 60 can comprise thin film bond pads, test pads or fuse pads on a bare die.
- the component contacts 60 are embedded in a passivation layer 88 .
- the interconnect contacts 58 can be formed integrally with a substrate 62 of the interconnect 18 .
- the substrate 62 comprises silicon, such that a coefficient of thermal expansion (CTE) of the interconnect 18 matches that of components 16 formed of silicon.
- CTE coefficient of thermal expansion
- germanium, a glass material, or a ceramic material can be used as the substrate material.
- the interconnect contacts 58 include penetrating projections 64 adapted to penetrate the component contacts 58 to a limited penetration depth.
- the interconnect contacts 58 include conductive layers 66 adapted to electrically contact the component contacts 58 .
- the conductive layers 66 are in electrical communication with patterns of conductors 68 formed on a surface of the substrate 62 .
- the conductors 68 include, or are in electrical communication with, the bond pads 52 .
- An insulating layer 70 is formed on the substrate 62 to electrically insulate the conductors 68 and conductive layers 66 from a bulk of the substrate 62 . Further details of the interconnect 18 , including methods of fabrication, are disclosed in U.S. Pat. No.
- interconnect 18 A having interconnect contacts 58 A is illustrated.
- the interconnect contacts 58 A are adapted to form electrical connections with bumped component contacts 60 A.
- the bumped component contacts 60 A can comprise solder balls on a bumped die or chip scale package.
- the interconnect contacts 58 A comprise recesses 72 formed in an interconnect substrate 62 A.
- the recesses 72 are sized and shaped to retain the bumped component contacts 60 A.
- the interconnect contacts 58 A also include conductive layers 66 A covering the recesses 72 , and penetrating projections 64 A formed within the recesses 72 .
- the conductive layers 66 A are in electrical communication with conductors (not shown) equivalent to the conductors 68 (FIG. 6) previously described.
- the penetrating projections 64 A are configured to penetrate the bumped component contacts 60 A. Insulating layers 18 A insulate the conductive layers 66 A.
- the interconnect contacts 58 A also include conductive vias 74 in electrical communication with the conductive layers 66 A.
- the conductive vias 74 can include bumped terminal contacts 26 A, such as solder balls.
- the bumped terminal contacts 26 A form the terminal contacts for the carrier.
- One method for forming the conductive vias 74 comprises laser machining openings in the substrate 62 A, etching the openings (e.g., KOH or TMAH wet etch), insulating the openings with insulating layer 70 A, and then filling the openings with a conductive material (e.g., metal or conductive polymer).
- the terminal contacts 26 A can be attached to the conductive vias 74 by soldering, brazing, or welding, pre-formed metal balls to the conductive vias 74 .
- a ball bumper apparatus can be used to attach pre-formed metal balls to the conductive vias 74 to form the bumped terminal contacts 26 A.
- interconnect 18 A Further details of the interconnect 18 A, interconnect contacts 58 A, and conductive vias 74 , including methods of fabrication, are described in U.S. patent application Ser. No. 08/993,965 filed Dec. 18, 1997, entitled “Semiconductor Interconnect Having Laser Machined Contacts”, which is incorporated herein by reference.
- a method for fabricating the interconnect contacts 58 A is also described in U.S. patent application Ser. No. 08/829,193, filed Mar. 31, 1997 entitled “Interconnect Having Recessed Contact Members For Testing Semiconductor Dice And Packages With Contact Bumps”, which is incorporated herein by reference.
- an alternate embodiment interconnect 18 B includes interconnect contacts 58 B.
- the interconnect contacts 58 B comprise metal microbumps formed on polymer tape 76 similar to multi layered TAB tape.
- a compliant adhesive layer 78 attaches the polymer tape 76 to a substrate 62 B of the interconnect 18 B.
- conductors 68 B equivalent to conductors 68 can comprise metal foil laminated to the polymer tape 76 . Further details of the interconnect 10 B, and interconnect contacts 58 B, including methods of fabrication, are described in U.S. Pat. No. 5,678,301 entitled “Method For Forming An Interconnect For Testing Unpackaged Semiconductor Dice”.
- the interconnect 18 can be provided with contacts 58 , conductors 68 and bonding pads 52 , substantially as shown in FIG. 6.
- the lead frame 14 with lead fingers 40 and mounting paddle 38 can be provided substantially as shown in FIG. 5.
- the interconnect 18 can be attached to the mounting paddle 38 of the lead frame 14 by forming the adhesive layer 54 between the backside of the interconnect 18 , and the surface of the mounting paddle 38 .
- the adhesive layer 54 can comprise a deposited elastomer, as previously described, or an adhesive tape.
- the attaching step can be performed manually, or a conventional chip attach apparatus can be used.
- additional adhesive layers 54 A can be used to attach the lead fingers 40 on the lead frame 14 to a face of the interconnect 18 .
- a gasket 84 can be placed over the interconnect 18 and portions of the lead fingers 40 .
- the gasket 84 will protect the surface of the interconnect 18 , and the lead fingers 40 , during a subsequent encapsulation step.
- the inner dotted rectangle represents a peripheral outline of the gasket 84 .
- the gasket 84 comprises an elastomeric material, such as silicone, that can be easily removed from the interconnect 18 following the molding step.
- the gasket 84 can comprise a deposited and cured polymer layer, such as a thick film resist.
- the gasket 84 can comprise a removable plate configured to protect the interconnect 18 and portions of the lead fingers 40 .
- an injection mold 82 can be used to mold the carrier base 12 to the lead frame 14 .
- a conventional molding apparatus adapted to form plastic semiconductor packages can be used to perform the molding step.
- the carrier base 12 forms on either side of the lead fingers 40 in a shape which is determined by the mold 82 .
- the carrier base 12 can include all of the features as shown in FIGS. 1 - 3 including a size and outline corresponding to a conventional semiconductor package.
- the molding step molds the interconnect 18 into the carrier base 12 . Only the surface of the interconnect 18 , which is protected by the gasket 84 , remains unencapsulated by the molded base 12 .
- the lead frame 14 can be removed from the mold 82 .
- the gasket 84 can then be removed from the interconnect 18 . Removal of the gasket 84 can be accomplished using a suitable tool. If the gasket 84 comprises a deposited and cured material, removal can be with a wet etchant that will strip the gasket 84 without harming the interconnect 18 .
- the wires 80 can be wire bonded to the bonding pads 52 (FIG. 6) on the interconnect 18 , and to the lead fingers 40 on the lead frame 14 .
- a conventional wire bonder can be used to perform the wire bonding step. Prior to the wire bonding step it may be necessary to clean the surface of the interconnect 18 with a cleaning agent that will remove contaminants. It may also be necessary to remove any mold flash that could affect the wire bonds.
- a trim and form step can be performed to shape the exposed portions of the lead fingers 40 into the terminal leads 26 (FIG. 1) for the carrier 10 .
- the lead frame 14 can be cut into a plurality of separate carriers 10 .
- conventional equipment used to form conventional plastic semiconductor packages, can be employed.
- FIGS. 8 A- 8 E steps in a method for fabricating an alternate embodiment carrier 10 A (FIG. 8E) are illustrated. Initially as shown in FIG. 8A, the interconnect 18 can be attached to the mounting paddle 38 of the lead frame 14 using the adhesive layer 54 .
- the wires 80 can be wire bonded to the bonding pads 52 (FIG. 6) on the interconnect 18 and to the lead fingers 40 on the lead frame 14 .
- a polymer layer 86 can be formed on the face of the interconnect 18 .
- the polymer layer 86 will protect the interconnect 18 during a subsequent molding step.
- One suitable polymer for forming the polymer layer 86 comprises a thick film resist sold by Shell Chemical under the trademark “EPON RESIN SU-8”.
- the resist also includes an organic solvent (e.g., gamma-butyloracton), and a photoinitiator.
- the resist can be deposited to a thickness of from about 3-50 mils.
- a conventional resist coating apparatus such as a spin coater, or a meniscus coater, along with a mask or stencil, can be used to deposit the resist in viscous form onto the interconnect 18 .
- the deposited resist can then be hardened by heating to about 95° C. for about 15 minutes or longer.
- a plastic base 12 A can be molded to the lead frame 14 and the interconnect 18 , substantially as previously described for base 12 in FIG. 7C.
- the polymer layer 86 protects the interconnect 18 , particularly the interconnect contacts 58 (FIG. 6).
- the wires 80 can be encapsulated within the plastic base 12 A.
- the polymer layer 86 can be stripped to complete the carrier 10 A.
- a suitable wet etchant for stripping the previously described resist formulation is a solution of PGMEA (propyleneglycol-monomethyletheracetate).
- FIGS. 9 A- 9 D steps in a method for fabricating an alternate embodiment carrier 10 B (FIG. 9D) are illustrated.
- an interconnect 18 A fabricated as previously shown and described in FIG. 6B is provided.
- the interconnect 18 A includes recessed interconnect contacts 58 A and conductive vias 74 also as previously described.
- lead frame 14 A having lead fingers 40 A is provided.
- the lead frame 14 A has a lead on chip configuration in which the lead fingers 40 A rather than a mounting paddle support the interconnect 18 A.
- the interconnect 18 A can be attached to the lead fingers 40 A by forming an adhesive layer 54 A therebetween.
- a polymer layer 86 can be formed as previously described to protect the interconnect 18 A and interconnect contacts 58 A.
- a plastic body 12 B can be formed using a molding process as previously described. Again the interconnect 18 A is molded into the body 12 B, but in this embodiment the back side of the interconnect 18 A is exposed.
- the terminal contacts 26 A such as solder or conductive polymer balls, can be formed on the conductive vias 74 .
- the terminal contacts 26 A can be attached by soldering, brazing or welding preformed balls, or by attaching pre-formed balls using a ball bumper apparatus.
- the terminal contacts 26 A can be formed in a dense array on the interconnect 18 A, such as a ball grid array (BGA), or a fine ball grid array (FBGA).
- the lead fingers 40 A provide a structural function, but do not necessarily provide an electrical function. Electrical communication from the outside can be through the terminal contacts 26 A and conductive vias 74 to the contacts 58 A. However, if desired, the lead fingers 40 A can be electrically connected to select contacts 58 A, such as to provide power or ground connections. In this case an electrically conductive polymer, such as a Z-axis epoxy can be used to electrically connect the lead fingers 40 A to conductors in electrical communication with the contacts 58 A.
- the polymer layer 86 can be stripped, as previously described to complete the carrier 10 B.
- the carrier 10 C comprises a board 90 containing a plurality of interconnects 18 C.
- the interconnects 18 C are molded, or laminated, to the board 90 and include interconnect contacts 58 A formed as previously described.
- the interconnect contacts 58 A are in electrical communication with an electrical connector 94 , such as an edge connector, formed on the board 90 .
- Surface conductors (not shown) on the board 90 , or internal conductors (not shown) within the board 90 electrically connect the interconnect contacts 58 A to the electrical connector 94 on the board 90 .
- wire bonds as previously described, can be used to electrically connect the interconnect contacts to the electrical connector 94 , or to conductors in electrical communication with the electrical connector 94 .
- gaskets, or deposited polymer layers can be used to protect the interconnects 18 C during molding or lamination of the board.
- the board 90 comprises a glass filled resin such as an epoxy glass (FR-4), a polyimide glass or a cyanate-glass material.
- FR-4 epoxy glass
- polyimide glass polyimide glass
- cyanate-glass material a glass filled resin
- these materials can be laminated, cured, and then metallized using deposition and photolithography processes. Also, required features can be punched or machined using processes employed in the fabrication of printed circuit boards (PCB), and other electronic devices.
- PCB printed circuit boards
- the board 90 can comprise an electronics grade plastic, such as polyetherimide (PES), polyethersulfone (PES), polyether-ether ketone (PEEK), polyphenylene sulfide (PPS), or a liquid crystal polymer (LCP). With these plastics the board 90 can be shaped and metallized using a molding process such as 3-D injection molding.
- PES polyetherimide
- PES polyethersulfone
- PEEK polyether-ether ketone
- PPS polyphenylene sulfide
- LCP liquid crystal polymer
- the board 90 can comprise ceramic. With ceramic, a ceramic lamination and metallization process can be used to construct the board 90 . As another alternative, the board 90 can comprise silicon, or other semiconducting material. With silicon, etching, micromachining, and metallization processes used for semiconductor circuit fabrication can be uses to construct the board 90 .
- a lid 22 C and a spring 20 C are associated with each interconnect 18 C.
- the lids 22 C and springs 20 C can be formed substantially as previously described for lid 22 (FIG. 1A) and spring 20 (FIG. 1A).
- a vacuum passage 96 can be formed through the lid 22 C and the spring 20 C for retaining a component 16 A for assembly on the board 90 .
- the board 90 also includes a plurality of clip members 92 associated with each interconnect 18 C.
- the clip members 92 comprise resilient metal or plastic members that can either be molded integrally with the board, or attached with suitable fasteners. With the component 16 A placed on the interconnect 18 C, the clip members 92 hold the component 16 A in place for testing.
- the component 16 A can be assembled to the spring 20 C, and aligned with the interconnect 18 C using optical alignment techniques.
- U.S. Pat. No. 5,634,267 entitled “Method And Apparatus For Manufacturing Known Good Semiconductor Die”, which is incorporated herein by reference, describes a method of optical alignment.
Abstract
Description
- This invention relates generally to semiconductor manufacture, and more particularly to an improved test carrier for temporarily packaging and testing semiconductor components, such as dice and chip scale packages. This invention also relates to a test system incorporating the carrier, and to a method for fabricating the carrier.
- Semiconductor components, such as bare dice and chip scale packages must be tested prior to shipment by semiconductor manufacturers. Since these components are relatively small and fragile, carriers have been developed for temporarily packaging the components for testing. The carriers permit electrical connections to be made between external contacts on the components, and testing equipment such as burn-in boards. On bare dice, the external contacts typically comprise planar or bumped bond pads. On chip scale packages, the external contacts typically comprise solder balls in a dense array, such as a ball grid array, or a fine ball grid array.
- An interconnect on the carrier includes contacts that make the temporary electrical connections with the external contacts on the components. The interconnect must provide power, ground and signal paths to the component. As the external contacts on the components become smaller and denser, it becomes more difficult to fabricate the carrier with the required number of electrical paths to the interconnect.
- Also, the carrier must be reused multiple times in a production environment. Accordingly, it is desirable to make the carrier as damage resistant as possible. Incorporating the interconnect into the carrier, while maintaining a compact outline for the carrier is increasingly difficult. In addition, the fabrication process for the carrier must be capable of producing production quantities at reasonable costs. It would be advantageous to have the capability to fabricate carriers using conventional semiconductor fabrication processes. This would lower initial capital outlays for production equipment, and lower production costs.
- In view of the foregoing, improved carriers for testing semiconductor components including unpackaged dice, and chip scale packages are needed. Also needed are improved fabrication processes for carriers. In particular, carriers which can be constructed at low costs, using standard fabrication equipment, are needed.
- In accordance with the present invention, an improved test carrier, and a method for fabricating the carrier, are provided. The test carrier can be used to temporarily package and test semiconductor components, such as bare dice, and chip scale packages.
- The test carrier includes a base for retaining one or more components, and et lead frame molded to the base. The lead frame includes lead fingers which form internal signal traces and terminal contacts for the carrier. The carrier also includes an interconnect, which is attached to a mounting paddle of the lead frame and molded to the base.
- The interconnect includes contacts for electrically contacting external contacts on the component under test. The interconnect contacts are electrically connected to the lead fingers of the lead frame by wire bonding. For components with planar external contacts, such as bond pads on bare dice, the interconnect contacts can comprise etched pillars with penetrating projections. Alternately, for planar external contacts, the interconnect contacts can comprise microbumps on a polymer film. For components with bumped contacts, such as chip scale packages having solder balls, the interconnect contacts can comprise recesses, or flat pads, covered with conductive layers.
- The carrier also includes a force applying member for biasing the component against the interconnect. The force applying mechanism includes a biasing member, such as a compressible elastomeric spring. The force applying mechanism also includes a lid, and one or more clips, which attach to the carrier base.
- In an alternate embodiment, multiple interconnects can be molded to a board having integrally formed clip members. In another alternate embodiment laser machined conductive vias in the interconnect provide electrical paths for external contacts formed directly on the interconnect.
- The method for fabricating the carrier includes the initial step of attaching the interconnect to the lead frame. Following attachment, an elastomeric gasket can be placed on the interconnect and lead frame, to protect the interconnect, and portions of the lead fingers wherein wire bonds will be formed. Alternately, in place of an elastomeric gasket, a polymer layer, such as a thick film resist, can be applied to the interconnect prior to molding. During a molding step, the carrier base is molded to the lead frame and interconnect. Next, the gasket is removed, or the polymer layer is stripped, and the interconnect is wire bonded to the lead fingers. As another alternate wiring bonding can precede molding, and the wire bonds can be encapsulated. Finally, a trim and form step is performed to form exposed portions of the lead fingers into the terminal leads of the carrier.
- A test system constructed in accordance with the invention includes the carrier and test circuitry. The test circuitry generates and transmits test signals through the carrier to the component, and evaluates the resultant signals. The test system can also include a burn-in board which provides electrical interface between the carrier and test circuitry.
- FIG. 1 is a plan view of a test carrier constructed in accordance with the invention;
- FIG. 1A is a cross sectional view taken along section line1A-1A of FIG. 1;
- FIG. 2 is a side elevation view of the carrier;
- FIG. 3 is an end view of the carrier;
- FIG. 4 is a schematic plan view of a lead frame configured for fabricating multiple carriers;
- FIG. 5 is an enlarged plan view taken along section line5-5 of FIG. 4 of a portion of the lead frame;
- FIG. 5A is an enlarged plan view partially cut away taken along
section line 5A-5A of FIG. 5; - FIG. 5B is a cross sectional view of the lead frame and interconnect taken along
section line 5B-5B of FIG. 5; - FIG. 6 is an enlarged plan view of an interconnect of the carrier with a component under test superimposed thereon;
- FIG. 6A is an enlarged cross sectional view taken along
section line 6A-6A of FIG. 6, illustrating an interconnect contact electrically engaging a component contact; - FIG. 6B is an enlarged cross sectional view equivalent to FIG. 6A of an alternate embodiment interconnect contact;
- FIG. 6C is a plan view of the interconnect contact of FIG. 6B;
- FIG. 6C is enlarged cross sectional view equivalent to FIG. 6A of another alternate embodiment interconnect contact;
- FIGS.7A-7F are schematic cross sectional views illustrating steps in a method for fabricating the carrier in accordance with the invention;
- FIGS.8A-8E are schematic cross sectional views illustrating steps in a method for fabricating an alternate embodiment carrier;
- FIGS.9A-9D are schematic cross sectional views illustrating steps in a method for fabricating another alternate embodiment carrier;
- FIG. 10A is a schematic perspective view of an alternate embodiment carrier; and
- FIG. 10B is a cross sectional view taken along
section line 10B-10B of FIG. 10A. - Referring to FIGS.1-3, a
test carrier 10 constructed in accordance with the invention is illustrated. Thecarrier 10 is adapted to temporarily package a semiconductor component 16 (FIG. 1A) for testing and burn-in. - The
carrier 10 includes abase 12, a lead frame 14 (FIG. 1A) and an interconnect 18 (FIG. 1A). As will be further explained, thelead frame 14 andinterconnect 18 are molded to thebase 12. Thecarrier 10 also includes a force applying mechanism comprising a spring 20 (FIG. 1A), alid 22 and a pair ofclips 24. In addition, thecarrier 10 includes a plurality of terminal leads 26 in electrical communication with theinterconnect 18. - As will be further explained, the terminal leads26 comprise trimmed and formed portions of the
lead frame 14. Further, the terminal leads 26 are adapted for electrical communication with test circuitry 27 (FIG. 2) of a test system. Thetest circuitry 27 generates test signals, and transmits the test signals to the terminal leads 26 and through theinterconnect 18 to thecomponent 16. Thetest circuitry 27 also analyzes the resultant test signals transmitted from thecomponent 16. This permits various electrical characteristics of thecomponent 16 to be evaluated. - The
carrier base 12 and terminal leads 26 have a configuration (i.e., size, peripheral outline, external leads) corresponding to that of a conventional semiconductor package. In the illustrative embodiment, thecarrier base 12 has the configuration of a small outline j-bend (SOJ) package. Alternately, thecarrier base 12 can have the configuration of other conventional packages such as single in line memory module (SIMM), dual in line package (DIP), quad flat pack (QFP), zig zag in line package (ZIP), or leadless chip carrier (LCC). This permits thecarrier 10 to be utilized with conventional equipment such as burn-in boards, carrier trays, and handling equipment associated with conventional semiconductor packages. In the illustrative embodiment in the SOJ configuration, he terminal leads 26 are located on opposing sides of thecarrier base 12. However, for other configurations the terminal leads 26 can be located on more than two sides (e.g., three sides, four sides). - Alternately, rather than having terminal leads26 formed as dual in line pins, other configurations for the
leads 26 can be provided. For example, thecarrier base 12 can include solder balls in a ball grid array (BGA) or fine ball grid array (FBGA), or pins in a pin grid array (PGA). Thecarrier base 12 and terminal leads 26 can also have a specialized configuration different than conventional semiconductor packages. - The
carrier base 12 is formed of plastic using a conventional injection molding process. Exemplary plastics include epoxy novolac resin, silicone, phenylsilane and thermoset plastics. Thecarrier base 12 includeschannels 28 on either end for receiving theclips 24. Thecarrier base 12 also includes arecess 30. With thelid 22 attached to thecarrier base 12 therecess 30 forms an enclosed cavity 32 (FIG. 1A) for thecomponent 16 andspring 20. Also, with thelid 22 attached to thecarrier base 12, thecomponent 16 is pressed by thespring 20 against theinterconnect 18. - The
lid 22 and clips 24 are sized and shaped for mating physical engagement. In addition, theclips 24 include rectangular openings 34 (FIG. 1) which permit handling by a manual or automated tool. Preferably theclips 24 comprise a resilient metal or plastic material. - The
spring 20 can comprise a resilient elastomeric material such as silicone, butyl rubber, or fluorosilicone. Suitable elastomeric materials include “PORON” available from a Rogers Corporation subsidiary of Elkgrove Village, ILL. If desired, theelastomeric spring 20 can be secured to thelid 22 using an adhesive such as silicone. Rather than being formed of elastomeric materials, thespring 20 can comprise a resilient metal such as a belleville washer, or spring segment. Alternately, thespring 20 can comprise a compressible gas or liquid filled bladder. This type of bladder is available from Paratech of Frankfort, IL under the trademark “MAXI FORCE AIR BAG”. - Assembly of the
carrier 10, with thecomponent 16 therein, can be accomplished by attaching thecomponent 16 to thelid 22 andspring 20. Thelid 22 andspring 20 can include avacuum conduit 31 to enable attachment of thecomponent 16 using a vacuum tool (not shown). Thecomponent 16 can then be aligned with theinterconnect 18 and placed in contact therewith. Optical alignment techniques can be used during assembly of thecarrier 10. U.S. Pat. No. 5,541,525 entitled “Carrier For Testing An Unpackaged Semiconductor Die”, which is incorporated herein by reference, describes a method for assembling thecarrier 10 using optical alignment. - Referring to FIGS. 4 and 5, the
lead frame 14 is shown prior to formation of thecarrier base 12. Thelead frame 14 initially comprises a strip of material which includes multiple interconnect mounting sites 36 (FIG. 4). In an illustrative embodiment thelead frame 14 includes teninterconnect mounting sites 36. However, this number is merely exemplary, and a greater or lesser number ofinterconnect mounting sites 36 can be employed. Eachinterconnect mounting site 36 can be used to mount aninterconnect 18 to form asingle carrier base 12. Following a molding step in which the carrier bases 12 are molded to theinterconnects 18, thelead frame 14 can be cut or sheared into a plurality ofseparate bases 12. Eachcarrier base 12 includes an integrally moldedinterconnect 18 substantially as shown in FIG. 1A. - As shown in FIG. 5, the
lead frame 14 includes parallel spaced side rails 42, 44 having multiple throughopenings openings lead frame 14 to be handled by automated transfer mechanisms associated with chip bonders, wire bonders, molds, trim and form machinery, and marking machinery. Thelead frame 14 also includeelongated openings 50 to facilitate singulation of thelead frame 14 intoseparate carriers 10. Thelead frame 14 can be formed of metal using a stamping process, or a chemical milling process. Suitable metals for thelead frame 14 include nickel-iron alloys (e.g., 42% Ni-58% Fe), clad materials (e.g., copper clad stainless steel), or copper alloys. - As also shown in FIG. 5, each
interconnect mounting site 36 includes a downset mounting paddle 38. In addition, eachinterconnect mounting site 36 includes a pattern oflead fingers 40. Following the molding step, wires 80 (FIG. 1A) will be wire bonded to thelead fingers 40 and tobonding pads 52 on theinterconnect 18. Thelead fingers 40 will form the internal signal traces for thecarrier 10. Also, terminal portions of thelead fingers 40 will be trimmed and formed to form the terminal leads 26 (FIG. 1) of thecarrier 10. - Some of the
lead fingers 40 can overlap theinterconnect 18 to provide increased structural rigidity for supporting theinterconnect 18 in the moldedbase 12. As shown in FIG. 5A, the mountingpaddle 38 can include cutouts 39 to accommodate formation of the overlappinglead fingers 40 during stamping or etching of thelead frame 14. - As shown in FIG. 5B, the mounting
paddle 38 includes a planar surface configured to support theinterconnect 18. During attachment of theinterconnect 18 to thelead frame 14, a backside of theinterconnect 18 can be adhesively bonded to the mountingpaddle 38. Accordingly, the mountingpaddle 38 has a peripheral shape which corresponds to a peripheral shape of theinterconnect 18. In the illustrative embodiment the mountingpaddle 38 has a generally rectangular peripheral shape. However, the mountingpaddle 38 can also be configured in other peripheral shapes, such as square. A peripheral size of the mountingpaddle 38 can be slightly larger than a peripheral size of theinterconnect 18. - The
interconnect 18 can be attached to the mountingpaddle 38 using anadhesive layer 54. Theadhesive layer 54 can comprise an epoxy, acrylic, silicone or polyimide material. Alternately, theadhesive layer 54 can comprise a polymer tape, such as “KAPTON” tape manufactured by DuPont. For attaching theinterconnect 18 to the mounting paddle 38 a manual or automated process can be employed. For an automated process, a conventional chip bonder used in the production of conventional semiconductor packages for bonding dice to lead frames can be utilized. - Still referring to FIG. 5B, the mounting
paddle 38 includesdownset segments 56 which connect the mounting paddle to thesiderails 42, 44 (FIG. 5) of thelead frame 14. A downset D of the mountingpaddle 38 provides an offset for the mountingpaddle 38 relative to thelead fingers 40. This facilitates molding of theinterconnect 18 into theplastic base 12, and embeds theinterconnect 18 within the molded plastic material of thebase 12. In addition, as shown in FIG. 1A, thedownset mounting paddle 38 forms an exposed bottom surface of thebase 12. During a test procedure using thepackage 10, the exposed surface of the mountingpaddle 38 improves heat transfer from theinterconnect 18. - Referring to FIGS. 6 and 6A, the
interconnect 18 is illustrated separately. Theinterconnect 18 includes patterns ofinterconnect contacts 58 which are configured to electrically connect to contacts 60 (FIG. 6A) on thecomponent 16. By way of example, thecomponent contacts 60 can comprise thin film bond pads, test pads or fuse pads on a bare die. In this case, thecomponent contacts 60 are embedded in apassivation layer 88. - The
interconnect contacts 58 can be formed integrally with asubstrate 62 of theinterconnect 18. Preferably, thesubstrate 62 comprises silicon, such that a coefficient of thermal expansion (CTE) of theinterconnect 18 matches that ofcomponents 16 formed of silicon. Alternately, germanium, a glass material, or a ceramic material, can be used as the substrate material. - The
interconnect contacts 58 include penetratingprojections 64 adapted to penetrate thecomponent contacts 58 to a limited penetration depth. In addition, theinterconnect contacts 58 includeconductive layers 66 adapted to electrically contact thecomponent contacts 58. Theconductive layers 66 are in electrical communication with patterns ofconductors 68 formed on a surface of thesubstrate 62. Theconductors 68 include, or are in electrical communication with, thebond pads 52. An insulatinglayer 70 is formed on thesubstrate 62 to electrically insulate theconductors 68 andconductive layers 66 from a bulk of thesubstrate 62. Further details of theinterconnect 18, including methods of fabrication, are disclosed in U.S. Pat. No. 5,483,741, entitled “Method For Fabricating A Self Limiting Silicon Based Interconnect For Testing Bare Semicorductor Dice”, and U.S. Pat. No. 5,686,317, entitled “Method For Fabricating An Interconnect Having A Penetration Limited Contact Structure For Establishing A Temporary Electrical Connection With A Semiconductor Die”, both of which are incorporated herein by reference. - Referring to FIGS. 6B and 6C, an
alternate embodiment interconnect 18A havinginterconnect contacts 58A is illustrated. Theinterconnect contacts 58A are adapted to form electrical connections with bumpedcomponent contacts 60A. For example, the bumpedcomponent contacts 60A can comprise solder balls on a bumped die or chip scale package. - The
interconnect contacts 58A comprise recesses 72 formed in aninterconnect substrate 62A. Therecesses 72 are sized and shaped to retain the bumpedcomponent contacts 60A. Theinterconnect contacts 58A also includeconductive layers 66A covering therecesses 72, and penetratingprojections 64A formed within therecesses 72. Theconductive layers 66A are in electrical communication with conductors (not shown) equivalent to the conductors 68 (FIG. 6) previously described. The penetratingprojections 64A are configured to penetrate the bumpedcomponent contacts 60A. Insulatinglayers 18A insulate theconductive layers 66A. - The
interconnect contacts 58A also includeconductive vias 74 in electrical communication with theconductive layers 66A. Theconductive vias 74 can include bumpedterminal contacts 26A, such as solder balls. As will be further explained, in analternate embodiment carrier 10B (FIG. 9D), the bumpedterminal contacts 26A form the terminal contacts for the carrier. - One method for forming the
conductive vias 74 comprises laser machining openings in thesubstrate 62A, etching the openings (e.g., KOH or TMAH wet etch), insulating the openings with insulatinglayer 70A, and then filling the openings with a conductive material (e.g., metal or conductive polymer). Theterminal contacts 26A can be attached to theconductive vias 74 by soldering, brazing, or welding, pre-formed metal balls to theconductive vias 74. Alternately, a ball bumper apparatus can be used to attach pre-formed metal balls to theconductive vias 74 to form the bumpedterminal contacts 26A. - Further details of the
interconnect 18A,interconnect contacts 58A, andconductive vias 74, including methods of fabrication, are described in U.S. patent application Ser. No. 08/993,965 filed Dec. 18, 1997, entitled “Semiconductor Interconnect Having Laser Machined Contacts”, which is incorporated herein by reference. A method for fabricating theinterconnect contacts 58A is also described in U.S. patent application Ser. No. 08/829,193, filed Mar. 31, 1997 entitled “Interconnect Having Recessed Contact Members For Testing Semiconductor Dice And Packages With Contact Bumps”, which is incorporated herein by reference. - Referring to FIG. 6D, an
alternate embodiment interconnect 18B includesinterconnect contacts 58B. Theinterconnect contacts 58B comprise metal microbumps formed onpolymer tape 76 similar to multi layered TAB tape. In this embodiment a compliantadhesive layer 78 attaches thepolymer tape 76 to asubstrate 62B of theinterconnect 18B. In addition,conductors 68B equivalent to conductors 68 (FIG. 6) can comprise metal foil laminated to thepolymer tape 76. Further details of theinterconnect 10B, andinterconnect contacts 58B, including methods of fabrication, are described in U.S. Pat. No. 5,678,301 entitled “Method For Forming An Interconnect For Testing Unpackaged Semiconductor Dice”. - Referring to FIGS.7A-7F, steps in a method for fabricating the
carrier 10 are illustrated. Initially, theinterconnect 18 can be provided withcontacts 58,conductors 68 andbonding pads 52, substantially as shown in FIG. 6. In addition, thelead frame 14 withlead fingers 40 and mountingpaddle 38 can be provided substantially as shown in FIG. 5. - Next, as shown in FIG. 7A, the
interconnect 18 can be attached to the mountingpaddle 38 of thelead frame 14 by forming theadhesive layer 54 between the backside of theinterconnect 18, and the surface of the mountingpaddle 38. Theadhesive layer 54 can comprise a deposited elastomer, as previously described, or an adhesive tape. The attaching step can be performed manually, or a conventional chip attach apparatus can be used. Also, additionaladhesive layers 54A can be used to attach thelead fingers 40 on thelead frame 14 to a face of theinterconnect 18. - Next, as shown in FIG. 7B, a
gasket 84 can be placed over theinterconnect 18 and portions of thelead fingers 40. Thegasket 84 will protect the surface of theinterconnect 18, and thelead fingers 40, during a subsequent encapsulation step. In FIG. 5, the inner dotted rectangle represents a peripheral outline of thegasket 84. In the embodiment of FIG. 7B, thegasket 84 comprises an elastomeric material, such as silicone, that can be easily removed from theinterconnect 18 following the molding step. Alternately, as will be further explained, thegasket 84 can comprise a deposited and cured polymer layer, such as a thick film resist. Still further, thegasket 84 can comprise a removable plate configured to protect theinterconnect 18 and portions of thelead fingers 40. - Next, as shown in FIG. 7C, an
injection mold 82 can be used to mold thecarrier base 12 to thelead frame 14. A conventional molding apparatus adapted to form plastic semiconductor packages can be used to perform the molding step. Thecarrier base 12 forms on either side of thelead fingers 40 in a shape which is determined by themold 82. Thecarrier base 12 can include all of the features as shown in FIGS. 1-3 including a size and outline corresponding to a conventional semiconductor package. - In addition to forming the
carrier base 12, the molding step molds theinterconnect 18 into thecarrier base 12. Only the surface of theinterconnect 18, which is protected by thegasket 84, remains unencapsulated by the moldedbase 12. - Next as shown in FIG. 7D, the
lead frame 14 can be removed from themold 82. As shown in FIG. 7E, thegasket 84 can then be removed from theinterconnect 18. Removal of thegasket 84 can be accomplished using a suitable tool. If thegasket 84 comprises a deposited and cured material, removal can be with a wet etchant that will strip thegasket 84 without harming theinterconnect 18. - Next, as shown in FIG. 7F, the
wires 80 can be wire bonded to the bonding pads 52 (FIG. 6) on theinterconnect 18, and to thelead fingers 40 on thelead frame 14. A conventional wire bonder can be used to perform the wire bonding step. Prior to the wire bonding step it may be necessary to clean the surface of theinterconnect 18 with a cleaning agent that will remove contaminants. It may also be necessary to remove any mold flash that could affect the wire bonds. - Following wire bonding, a trim and form step can be performed to shape the exposed portions of the
lead fingers 40 into the terminal leads 26 (FIG. 1) for thecarrier 10. In addition, thelead frame 14 can be cut into a plurality ofseparate carriers 10. In each of the illustrative steps, conventional equipment, used to form conventional plastic semiconductor packages, can be employed. - Referring to FIGS.8A-8E, steps in a method for fabricating an alternate embodiment carrier 10A (FIG. 8E) are illustrated. Initially as shown in FIG. 8A, the
interconnect 18 can be attached to the mountingpaddle 38 of thelead frame 14 using theadhesive layer 54. - Next, as shown in FIG. 8B, the
wires 80 can be wire bonded to the bonding pads 52 (FIG. 6) on theinterconnect 18 and to thelead fingers 40 on thelead frame 14. - Next, as shown in FIG. 8C, a
polymer layer 86 can be formed on the face of theinterconnect 18. As with the gasket 84 (FIG. 7B), thepolymer layer 86 will protect theinterconnect 18 during a subsequent molding step. One suitable polymer for forming thepolymer layer 86 comprises a thick film resist sold by Shell Chemical under the trademark “EPON RESIN SU-8”. The resist also includes an organic solvent (e.g., gamma-butyloracton), and a photoinitiator. The resist can be deposited to a thickness of from about 3-50 mils. A conventional resist coating apparatus, such as a spin coater, or a meniscus coater, along with a mask or stencil, can be used to deposit the resist in viscous form onto theinterconnect 18. The deposited resist can then be hardened by heating to about 95° C. for about 15 minutes or longer. - Next, as shown in FIG. 8D, a
plastic base 12A can be molded to thelead frame 14 and theinterconnect 18, substantially as previously described forbase 12 in FIG. 7C. During the molding step, thepolymer layer 86 protects theinterconnect 18, particularly the interconnect contacts 58 (FIG. 6). However, in this embodiment thewires 80 can be encapsulated within theplastic base 12A. - Next, as shown in FIG. 8E, the
polymer layer 86 can be stripped to complete the carrier 10A. A suitable wet etchant for stripping the previously described resist formulation is a solution of PGMEA (propyleneglycol-monomethyletheracetate). - Referring to FIGS.9A-9D, steps in a method for fabricating an
alternate embodiment carrier 10B (FIG. 9D) are illustrated. Initially, aninterconnect 18A fabricated as previously shown and described in FIG. 6B is provided. Theinterconnect 18A includes recessedinterconnect contacts 58A andconductive vias 74 also as previously described. In addition,lead frame 14A havinglead fingers 40A is provided. Preferably thelead frame 14A has a lead on chip configuration in which thelead fingers 40A rather than a mounting paddle support theinterconnect 18A. - As shown in FIG. 9A, the
interconnect 18A can be attached to thelead fingers 40A by forming anadhesive layer 54A therebetween. - Next, as shown in FIG. 9B, a
polymer layer 86 can be formed as previously described to protect theinterconnect 18A andinterconnect contacts 58A. - Next, as shown in FIG. 9C, a
plastic body 12B can be formed using a molding process as previously described. Again theinterconnect 18A is molded into thebody 12B, but in this embodiment the back side of theinterconnect 18A is exposed. Following encapsulation, theterminal contacts 26A such as solder or conductive polymer balls, can be formed on theconductive vias 74. Theterminal contacts 26A can be attached by soldering, brazing or welding preformed balls, or by attaching pre-formed balls using a ball bumper apparatus. Advantageously, theterminal contacts 26A can be formed in a dense array on theinterconnect 18A, such as a ball grid array (BGA), or a fine ball grid array (FBGA). - Also in this embodiment, the
lead fingers 40A provide a structural function, but do not necessarily provide an electrical function. Electrical communication from the outside can be through theterminal contacts 26A andconductive vias 74 to thecontacts 58A. However, if desired, thelead fingers 40A can be electrically connected to selectcontacts 58A, such as to provide power or ground connections. In this case an electrically conductive polymer, such as a Z-axis epoxy can be used to electrically connect thelead fingers 40A to conductors in electrical communication with thecontacts 58A. - Next, as shown in FIG. 9D the
polymer layer 86 can be stripped, as previously described to complete thecarrier 10B. - Referring to FIGS. 10A and 10B, an
alternate embodiment carrier 10C is illustrated. Thecarrier 10C comprises aboard 90 containing a plurality ofinterconnects 18C. Theinterconnects 18C are molded, or laminated, to theboard 90 and includeinterconnect contacts 58A formed as previously described. Theinterconnect contacts 58A are in electrical communication with anelectrical connector 94, such as an edge connector, formed on theboard 90. Surface conductors (not shown) on theboard 90, or internal conductors (not shown) within theboard 90 electrically connect theinterconnect contacts 58A to theelectrical connector 94 on theboard 90. In addition, wire bonds as previously described, can be used to electrically connect the interconnect contacts to theelectrical connector 94, or to conductors in electrical communication with theelectrical connector 94. Also gaskets, or deposited polymer layers, can be used to protect theinterconnects 18C during molding or lamination of the board. - In the illustrative embodiment, the
board 90 comprises a glass filled resin such as an epoxy glass (FR-4), a polyimide glass or a cyanate-glass material. In addition to being electrically insulating and structurally rigid, these materials can be laminated, cured, and then metallized using deposition and photolithography processes. Also, required features can be punched or machined using processes employed in the fabrication of printed circuit boards (PCB), and other electronic devices. - Alternately, rather than the above materials, the
board 90 can comprise an electronics grade plastic, such as polyetherimide (PES), polyethersulfone (PES), polyether-ether ketone (PEEK), polyphenylene sulfide (PPS), or a liquid crystal polymer (LCP). With these plastics theboard 90 can be shaped and metallized using a molding process such as 3-D injection molding. - Alternately, the
board 90 can comprise ceramic. With ceramic, a ceramic lamination and metallization process can be used to construct theboard 90. As another alternative, theboard 90 can comprise silicon, or other semiconducting material. With silicon, etching, micromachining, and metallization processes used for semiconductor circuit fabrication can be uses to construct theboard 90. - As shown in FIG. 10B, a
lid 22C and a spring 20C, are associated with eachinterconnect 18C. Thelids 22C and springs 20C can be formed substantially as previously described for lid 22 (FIG. 1A) and spring 20 (FIG. 1A). In addition, avacuum passage 96 can be formed through thelid 22C and the spring 20C for retaining acomponent 16A for assembly on theboard 90. - As shown in FIG. 10B, the
board 90 also includes a plurality ofclip members 92 associated with eachinterconnect 18C. Theclip members 92 comprise resilient metal or plastic members that can either be molded integrally with the board, or attached with suitable fasteners. With thecomponent 16A placed on theinterconnect 18C, theclip members 92 hold thecomponent 16A in place for testing. - The
component 16A can be assembled to the spring 20C, and aligned with theinterconnect 18C using optical alignment techniques. U.S. Pat. No. 5,634,267, entitled “Method And Apparatus For Manufacturing Known Good Semiconductor Die”, which is incorporated herein by reference, describes a method of optical alignment. - Thus the invention provides an improved semiconductor carrier and method of fabrication. Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention, as defined by the following claims.
Claims (45)
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US10/351,767 US6642730B1 (en) | 1998-08-28 | 2003-01-27 | Test carrier with molded interconnect for testing semiconductor components |
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Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6353326B2 (en) | 1998-08-28 | 2002-03-05 | Micron Technology, Inc. | Test carrier with molded interconnect for testing semiconductor components |
TW530159B (en) * | 1999-07-16 | 2003-05-01 | Advantest Corp | Insert for electric devices testing apparatus |
GB2355112A (en) * | 1999-10-08 | 2001-04-11 | Nokia Mobile Phones Ltd | Controlling bondwire inductance by using chip as positional reference |
US6563215B1 (en) | 2000-01-10 | 2003-05-13 | Micron Technology, Inc. | Silicon carbide interconnect for semiconductor components and method of fabrication |
US7033920B1 (en) | 2000-01-10 | 2006-04-25 | Micron Technology, Inc. | Method for fabricating a silicon carbide interconnect for semiconductor components |
US6975030B1 (en) | 2000-01-10 | 2005-12-13 | Micron Technology, Inc. | Silicon carbide contact for semiconductor components |
US20030160362A1 (en) * | 2002-02-22 | 2003-08-28 | Lighthouse Industries, Inc. | Method of injection molding an article having an array of openings |
US20040245590A1 (en) * | 2003-06-05 | 2004-12-09 | Jackson Hsieh | Image sensor package |
US20040245589A1 (en) * | 2003-06-05 | 2004-12-09 | Jackson Hsieh | Substrate structure for a photosensitive chip package |
US6979784B1 (en) * | 2003-10-17 | 2005-12-27 | Advanced Micro Devices, Inc. | Component power interface board |
US7100814B2 (en) * | 2004-02-18 | 2006-09-05 | Cardiac Pacemakers, Inc. | Method for preparing integrated circuit modules for attachment to printed circuit substrates |
US7833840B2 (en) * | 2006-08-03 | 2010-11-16 | Stats Chippac Ltd. | Integrated circuit package system with down-set die pad and method of manufacture thereof |
US8300423B1 (en) * | 2010-05-25 | 2012-10-30 | Amkor Technology, Inc. | Stackable treated via package and method |
US8482134B1 (en) | 2010-11-01 | 2013-07-09 | Amkor Technology, Inc. | Stackable package and method |
US8633598B1 (en) | 2011-09-20 | 2014-01-21 | Amkor Technology, Inc. | Underfill contacting stacking balls package fabrication method and structure |
US9029962B1 (en) | 2011-10-12 | 2015-05-12 | Amkor Technology, Inc. | Molded cavity substrate MEMS package fabrication method and structure |
Family Cites Families (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8412674D0 (en) | 1984-05-18 | 1984-06-27 | British Telecomm | Integrated circuit chip carrier |
KR960015106B1 (en) | 1986-11-25 | 1996-10-28 | 가부시기가이샤 히다찌세이사꾸쇼 | Surface package type semiconductor package |
US4815595A (en) | 1986-12-03 | 1989-03-28 | Sgs-Thomson Microelectronics, Inc. | Uniform leadframe carrier |
US5440240A (en) | 1991-06-04 | 1995-08-08 | Micron Technology, Inc. | Z-axis interconnect for discrete die burn-in for nonpackaged die |
US5634267A (en) | 1991-06-04 | 1997-06-03 | Micron Technology, Inc. | Method and apparatus for manufacturing known good semiconductor die |
US5408190A (en) | 1991-06-04 | 1995-04-18 | Micron Technology, Inc. | Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die |
US5073117A (en) | 1989-03-30 | 1991-12-17 | Texas Instruments Incorporated | Flip-chip test socket adaptor and method |
US5006792A (en) | 1989-03-30 | 1991-04-09 | Texas Instruments Incorporated | Flip-chip test socket adaptor and method |
US5344600A (en) | 1989-06-07 | 1994-09-06 | Motorola, Inc. | Method for encapsulating semiconductor devices with package bodies |
US5012386A (en) * | 1989-10-27 | 1991-04-30 | Motorola, Inc. | High performance overmolded electronic package |
US5167326A (en) | 1990-03-19 | 1992-12-01 | R. H. Murphy Co., Inc. | Carriers for integrated circuits and the like |
US5123850A (en) | 1990-04-06 | 1992-06-23 | Texas Instruments Incorporated | Non-destructive burn-in test socket for integrated circuit die |
US5070297A (en) * | 1990-06-04 | 1991-12-03 | Texas Instruments Incorporated | Full wafer integrated circuit testing device |
US5293072A (en) * | 1990-06-25 | 1994-03-08 | Fujitsu Limited | Semiconductor device having spherical terminals attached to the lead frame embedded within the package body |
US5046239A (en) | 1990-07-10 | 1991-09-10 | The United States Of America As Represented By The Secretary Of The Army | Method of making a flexible membrane circuit tester |
US5399903A (en) * | 1990-08-15 | 1995-03-21 | Lsi Logic Corporation | Semiconductor device having an universal die size inner lead layout |
US5088190A (en) | 1990-08-30 | 1992-02-18 | Texas Instruments Incorporated | Method of forming an apparatus for burn in testing of integrated circuit chip |
US5155067A (en) * | 1991-03-26 | 1992-10-13 | Micron Technology, Inc. | Packaging for a semiconductor die |
US6340894B1 (en) | 1991-06-04 | 2002-01-22 | Micron Technology, Inc. | Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect |
US5815000A (en) | 1991-06-04 | 1998-09-29 | Micron Technology, Inc. | Method for testing semiconductor dice with conventionally sized temporary packages |
US5495179A (en) | 1991-06-04 | 1996-02-27 | Micron Technology, Inc. | Carrier having interchangeable substrate used for testing of semiconductor dies |
US5691649A (en) | 1991-06-04 | 1997-11-25 | Micron Technology, Inc. | Carrier having slide connectors for testing unpackaged semiconductor dice |
US5367253A (en) | 1991-06-04 | 1994-11-22 | Micron Semiconductor, Inc. | Clamped carrier for testing of semiconductor dies |
US5519332A (en) | 1991-06-04 | 1996-05-21 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US5686317A (en) | 1991-06-04 | 1997-11-11 | Micron Technology, Inc. | Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die |
US5541525A (en) | 1991-06-04 | 1996-07-30 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US6094058A (en) | 1991-06-04 | 2000-07-25 | Micron Technology, Inc. | Temporary semiconductor package having dense array external contacts |
US5302891A (en) | 1991-06-04 | 1994-04-12 | Micron Technology, Inc. | Discrete die burn-in for non-packaged die |
US5578934A (en) | 1991-06-04 | 1996-11-26 | Micron Technology, Inc. | Method and apparatus for testing unpackaged semiconductor dice |
EP0689241A2 (en) | 1991-10-17 | 1995-12-27 | Fujitsu Limited | Carrier for carrying semiconductor device |
US5483174A (en) | 1992-06-10 | 1996-01-09 | Micron Technology, Inc. | Temporary connection of semiconductor die using optical alignment techniques |
US5283717A (en) * | 1992-12-04 | 1994-02-01 | Sgs-Thomson Microelectronics, Inc. | Circuit assembly having interposer lead frame |
KR960011257B1 (en) * | 1993-05-14 | 1996-08-21 | 삼성전자 주식회사 | Burn in socket and testing method using the same |
US5528463A (en) | 1993-07-16 | 1996-06-18 | Dallas Semiconductor Corp. | Low profile sockets and modules for surface mountable applications |
KR960008514B1 (en) | 1993-07-23 | 1996-06-26 | 삼성전자 주식회사 | Test socket and manufacturing method of known good die using that |
US5360348A (en) | 1993-08-16 | 1994-11-01 | Johnstech International Corporation | Integrated circuit device test socket |
US5633122A (en) | 1993-08-16 | 1997-05-27 | Micron Technology, Inc. | Test fixture and method for producing a test fixture for testing unpackaged semiconductor die |
US5572140A (en) | 1993-08-25 | 1996-11-05 | Sunright Limited | Reusable carrier for burn-in/testing on non packaged die |
US5543725A (en) | 1993-08-25 | 1996-08-06 | Sunright Limited | Reusable carrier for burn-in/testing on non packaged die |
US5483741A (en) | 1993-09-03 | 1996-01-16 | Micron Technology, Inc. | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice |
US5441684A (en) * | 1993-09-24 | 1995-08-15 | Vlsi Technology, Inc. | Method of forming molded plastic packages with integrated heat sinks |
KR0140034B1 (en) * | 1993-12-16 | 1998-07-15 | 모리시다 요이치 | Semiconductor wafer case, connection method and apparatus, and inspection method for semiconductor integrated circuit, probe card, and its manufacturing method |
KR970005706B1 (en) * | 1994-01-24 | 1997-04-19 | 금성일렉트론 주식회사 | Ccd and the manufacturing method |
US5563446A (en) * | 1994-01-25 | 1996-10-08 | Lsi Logic Corporation | Surface mount peripheral leaded and ball grid array package |
JPH07249723A (en) | 1994-03-11 | 1995-09-26 | Fujitsu Miyagi Electron:Kk | Method and structure for mounting semiconductor device and lead frame |
US5400220A (en) * | 1994-05-18 | 1995-03-21 | Dell Usa, L.P. | Mechanical printed circuit board and ball grid array interconnect apparatus |
US5451165A (en) | 1994-07-27 | 1995-09-19 | Minnesota Mining And Manufacturing Company | Temporary package for bare die test and burn-in |
US6577148B1 (en) * | 1994-08-31 | 2003-06-10 | Motorola, Inc. | Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer |
US5721496A (en) | 1996-01-23 | 1998-02-24 | Micron Technology, Inc. | Method and apparatus for leak checking unpackaged semiconductor dice |
US5739050A (en) | 1996-01-26 | 1998-04-14 | Micron Technology, Inc. | Method and apparatus for assembling a semiconductor package for testing |
US5742169A (en) | 1996-02-20 | 1998-04-21 | Micron Technology, Inc. | Apparatus for testing interconnects for semiconductor dice |
US5852870A (en) * | 1996-04-24 | 1998-12-29 | Amkor Technology, Inc. | Method of making grid array assembly |
US5982185A (en) | 1996-07-01 | 1999-11-09 | Micron Technology, Inc. | Direct connect carrier for testing semiconductor dice and method of fabrication |
US5929647A (en) | 1996-07-02 | 1999-07-27 | Micron Technology, Inc. | Method and apparatus for testing semiconductor dice |
US6255833B1 (en) | 1997-03-04 | 2001-07-03 | Micron Technology, Inc. | Method for testing semiconductor dice and chip scale packages |
US6258609B1 (en) | 1996-09-30 | 2001-07-10 | Micron Technology, Inc. | Method and system for making known good semiconductor dice |
US5783461A (en) | 1996-10-03 | 1998-07-21 | Micron Technology, Inc. | Temporary semiconductor package having hard-metal, dense-array ball contacts and method of fabrication |
US5834945A (en) | 1996-12-31 | 1998-11-10 | Micron Technology, Inc. | High speed temporary package and interconnect for testing semiconductor dice and method of fabrication |
US6072323A (en) | 1997-03-03 | 2000-06-06 | Micron Technology, Inc. | Temporary package, and method system for testing semiconductor dice having backside electrodes |
US6025731A (en) | 1997-03-21 | 2000-02-15 | Micron Technology, Inc. | Hybrid interconnect and system for testing semiconductor dice |
US6016060A (en) | 1997-03-25 | 2000-01-18 | Micron Technology, Inc. | Method, apparatus and system for testing bumped semiconductor components |
US5962921A (en) | 1997-03-31 | 1999-10-05 | Micron Technology, Inc. | Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps |
USD394844S (en) | 1997-04-25 | 1998-06-02 | Micron Technology, Inc. | Temporary package for semiconductor dice |
US6025728A (en) | 1997-04-25 | 2000-02-15 | Micron Technology, Inc. | Semiconductor package with wire bond protective member |
US5931685A (en) | 1997-06-02 | 1999-08-03 | Micron Technology, Inc. | Interconnect for making temporary electrical connections with bumped semiconductor components |
US6040702A (en) | 1997-07-03 | 2000-03-21 | Micron Technology, Inc. | Carrier and system for testing bumped semiconductor components |
US6072326A (en) | 1997-08-22 | 2000-06-06 | Micron Technology, Inc. | System for testing semiconductor components |
US6018249A (en) | 1997-12-11 | 2000-01-25 | Micron Technolgoy, Inc. | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US6107109A (en) | 1997-12-18 | 2000-08-22 | Micron Technology, Inc. | Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate |
US6075283A (en) | 1998-07-06 | 2000-06-13 | Micron Technology, Inc. | Downset lead frame for semiconductor packages |
US6369600B2 (en) | 1998-07-06 | 2002-04-09 | Micron Technology, Inc. | Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure |
US6353326B2 (en) | 1998-08-28 | 2002-03-05 | Micron Technology, Inc. | Test carrier with molded interconnect for testing semiconductor components |
US6242935B1 (en) | 1999-01-21 | 2001-06-05 | Micron Technology, Inc. | Interconnect for testing semiconductor components and method of fabrication |
US6175241B1 (en) | 1999-02-19 | 2001-01-16 | Micron Technology, Inc. | Test carrier with decoupling capacitors for testing semiconductor components |
US6222280B1 (en) | 1999-03-22 | 2001-04-24 | Micron Technology, Inc. | Test interconnect for semiconductor components having bumped and planar contacts |
US6263566B1 (en) | 1999-05-03 | 2001-07-24 | Micron Technology, Inc. | Flexible semiconductor interconnect fabricated by backslide thinning |
US6229202B1 (en) | 2000-01-10 | 2001-05-08 | Micron Technology, Inc. | Semiconductor package having downset leadframe for reducing package bow |
-
1998
- 1998-08-28 US US09/143,300 patent/US6353326B2/en not_active Expired - Fee Related
-
2000
- 2000-10-02 US US09/677,555 patent/US6544461B1/en not_active Expired - Fee Related
-
2003
- 2003-01-27 US US10/351,767 patent/US6642730B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US6544461B1 (en) | 2003-04-08 |
US6353326B2 (en) | 2002-03-05 |
US6642730B1 (en) | 2003-11-04 |
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