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Publication numberUS20010044203 A1
Publication typeApplication
Application numberUS 09/443,376
Publication dateNov 22, 2001
Filing dateNov 19, 1999
Priority dateSep 18, 1998
Also published asUS5994778, US6335273
Publication number09443376, 443376, US 2001/0044203 A1, US 2001/044203 A1, US 20010044203 A1, US 20010044203A1, US 2001044203 A1, US 2001044203A1, US-A1-20010044203, US-A1-2001044203, US2001/0044203A1, US2001/044203A1, US20010044203 A1, US20010044203A1, US2001044203 A1, US2001044203A1
InventorsRichard J. Huang, Guarionex Morales, Simon Chan
Original AssigneeRichard J. Huang, Guarionex Morales, Simon Chan
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Surface treatment of low-k siof to prevent metal interaction
US 20010044203 A1
Abstract
A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
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Claims(23)
We claim:
1. A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of:
obtaining a layer of SiOF; and
depleting the fluorine from a surface of the SiOF layer.
2. A method as defined in
claim 1
, wherein said depleting step comprises the step of treating the surface of said layer of SiOF with a plasma containing hydrogen to yield a treated surface.
3. A method as defined in
claim 1
, further comprising the step of passivating the treated surface.
4. A method as defined in
claim 3
, wherein said passivating step comprises the step of applying substantially pure nitrogen plasma to the treated surface.
5. A method as defined in
claim 4
, wherein said nitrogen plasma is applied at a lower plasma bias power and a higher pressure than said hydrogen-containing plasma used in said treating step.
6. A method as defined in
claim 2
, wherein said treating step is carried out in a CVD-TiN deposition chamber.
7. A method as defined in
claim 6
, wherein said treating step is carried out at a higher temperature than a temperature for CVD-TiN.
8. A method as defined in
claim 1
, further comprising the step of depositing a TiN layer on said treated surface.
9. A method as defined in
claim 8
, further comprising the step of depositing a tungsten layer over said TiN layer.
10. A method as defined in
claim 6
, further comprising the step of depositing a TiN layer on said treated surface.
11. A method as defined in
claim 1
, wherein said depleting step forms a depletion layer that is greater than or equal to 30 Angstroms in thickness.
12. A method as defined in
claim 3
, wherein said passivating step comprises the step of forming a passivation layer that is less than or equal to 25 Angstroms in thickness.
13. A method as defined in
claim 3
, wherein said depleting step forms a depletion layer that is greater than or equal to 30 Angstroms in thickness, and wherein said passivating step comprises the step of forming a passivation layer that is less than or equal to 25 Angstroms in thickness.
14. A method for using low dielectric SiOF in a process to manufacture semiconductor integrated circuit chips, comprising the steps of:
obtaining a layer of SiOF;
treating in a CVD-TiN deposition chamber a surface of said layer of SiOF with a plasma containing hydrogen to deplete fluorine from said surface;
passivating said treated surface with substantially pure N2 plasma; and
depositing a layer of TiN.
15. A method as defined in
claim 14
, wherein said treating step is carried out at a higher temperature than a temperature for CVD-TiN.
16. A semiconductor chip comprising:
an integrated circuit with at least a first and second layers, and with a dielectric layer of SiOF disposed between said two layers, wherein said SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
17. A semiconductor chip as defined in
claim 16
, wherein said first and second layers are metallic layers.
18. A semiconductor chip as defined in
claim 16
, wherein said first region includes a second region, extending from said edge to a depth which is less than said depth of said first region, said second region being passivated.
19. A semiconductor chip as defined in
claim 16
, wherein said second region is passivated with nitrogen.
20. A semiconductor chip as defined in
claim 17
, wherein said second layer is adjacent to said fluorine depleted region and is comprised of TiN.
21. A semiconductor chip as defined in
claim 16
, wherein said predetermined depth of said first region is greater than or equal to 30 Angstroms.
22. A semiconductor chip as defined in
claim 18
, wherein said predetermined depth of said first region is greater than or equal to 30 Angstroms and said depth of said second region is less than or equal to 25 Angstroms.
23. A semiconductor chip as defined in
claim 18
, wherein said depth of said second region is less than or equal to 25 Angstroms.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to the field of semiconductor chip processing, and more particularly, to the processing for an interlayer dielectric.

[0003] 2. Description of the Related Art

[0004] Fluorinated SiO2 (typically PECVD or HDP) can be used to lower the dielectric constant of SiO2 from, for example, 4.0 to 3.6-3.8. The lowering of the dielectric constant is advantageous for a number of reasons, including to reduce the capacitance of the semiconductor device and thereby increase its performance.

[0005] However, fluorine in SiO2 will react with PVD barrier metals (Ti, TiN, Ta, TaN, Al, Cu, etc.) which are subsequently deposited on the surface of the fluorinated SiO2. This reaction between fluorine and the barrier metals will cause delamination on flat SiOF surfaces, as well as inside via holes.

SUMMARY OF THE INVENTION

[0006] Briefly, the present invention comprises, in one aspect, a method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF; and depleting the fluorine from a surface of the SiOF layer.

[0007] In a further aspect of this inventive method, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen to yield a treated surface.

[0008] In a yet further aspect of the present invention, the method comprises the step of passivating the treated surface.

[0009] In a further aspect of the present invention, the passivating step comprises the step of applying substantially pure nitrogen plasma to the treated surface.

[0010] In a yet further aspect of the present invention, the nitrogen plasma is applied at a lower plasma bias power and a higher pressure than the hydrogen-containing plasma used in the treating step.

[0011] In a further aspect of the present invention, the treating step is carried out in a CVD deposition chamber.

[0012] In a yet further aspect of the present invention, the depleting step forms a depletion layer that is greater than or equal to 30 Angstroms in thickness.

[0013] In a further aspect of the present invention, the passivating step comprises the step of forming a passivation layer that is less than or equal to 25 Angstroms in thickness.

[0014] In a further embodiment of the present invention, a method is provided for using low dielectric SiOF in a process to manufacture semiconductor integrated circuit chips, comprising the steps of: obtaining a layer of SiOF; treating in a CVD-TiN deposition chamber a surface of the layer of SiOF with a plasma containing hydrogen to deplete fluorine from the surface; passivating the treated surface with substantially pure N2 plasma; and depositing a layer of TiN.

[0015] In a yet further embodiment of the present invention, a semiconductor chip is provided comprising: an integrated circuit with at least a first and second layers, and with a dielectric layer of SiOF disposed between said two layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

[0016] In a further aspect of this inventive embodiment, the predetermined depth of the first region is greater than or equal to 30 Angstroms.

[0017] In yet a further aspect of the present invention, the depth of the second region is less than or equal to 25 Angstroms.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a process flow diagram for a method in accordance with the present invention.

[0019]FIG. 2 is a cross-section of a select group of layers on a semiconductor chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0020] The present invention will be described in its context of use with an interlayer dielectric layer in a conducting layer stack on a semiconductor chip. However, the invention has broad application in any situation where SiOF is utilized as a layer.

[0021] Referring now to the drawings, FIG. 1 is a process flow diagram for a method in accordance with the present invention. FIG. 2 illustrates a semiconductor chip 10 in accordance with present invention comprising a bulk substrate and various process layers, designated generally by the numeral 12. A further layer 14 of same type is then deposited. By of example, this further layer 14 might be a conducting layer such as a metallic layer. For purposes of describing the present invention, an SiOF layer 16 is shown as being deposited on this layer 14. The SiOF layer 16 may be formed, by way of example, but not by way of limitation, by introducing a fluorine species during an SiO2 PECVD or HDP. Typically, after this SiOF deposition step, vias are etched through the SiOF layer 16. This via etch step is followed by a resist strip step and a solvent clean step, in the well known manner.

[0022] The present invention then requires application of a process to deplete the fluorine form the top surface of the SiOF layer 16 to yield a depleted layer 18 having a desired thickness. In a preferred embodiment this thickness of the depleted layer 18 is equal to or greater than 30 Angstroms.

[0023] In a preferred embodiment, the step used to form the depletion layer 16 is accomplished by treating the surface of the SiOF layer 16 with a plasma containing hydrogen. For example, the plasma may be pure hydrogen, or it may be a diluted H2 plasma, for example an H2/N2 plasma. The purpose of diluting the hydrogen plasma is to make the hydrogen less volatile.

[0024] The hydrogen in the plasma will bond with the fluorine atoms to form HF, which, because of its high vapor pressure and low boiling point, will be vaporized and evacuated from the system.

[0025] In a preferred embodiment, the hydrogen plasma treatment is performed in a CVD deposition chamber, such as, for example, an Applied Material CVD deposition chamber. The CVD chamber may be the same chamber used to be used to deposit a subsequent conducting layer, such as TiN. Preferably the CVD chamber for the plasma treatment should have a slightly elevated temperature (5-50° C. higher) relative to the temperature used to deposit the subsequent conducting layer. For example, if a temperature falling in the range of 375° C. to 450° C. is to be used to deposit a subsequent conducting layer 22, then a slightly elevated temperature that is 5° C. to 50° C. higher than the conducting layer CVD deposition temperature is used during the hydrogen plasma treatment step. The purpose of the use of this elevated temperature is to lower the potential that heating during the subsequent conducting layer deposition step will drive the fluorine atoms from the bulk SiOF layer 16 into the fluorine-depleted layer 18.

[0026] The other parameters for the hydrogen plasma treatment step will be determined empirically. Typically, the pressure in the CVD chamber will be in the millitorr to torr range, the energy parameter will be in the several hundred watt range, and plasma treatment time will range from 20 seconds to several minutes. Optimized parameters will be determined based on the desired thickness of the depletion layer 18.

[0027] In a preferred embodiment, the depleted layer 18 is then passivated to form a passivation layer 20 which is less than the thickness of layer 18. One purpose of the passivation is to bond non-volatile atoms into the depleted layer 18 to lessen the potential for fluorine atoms from the bulk SiOF layer 16 diffusing up into the depleted layer 18 and thereafter reacting with the conducting layer atoms of the subsequently deposited layer 22. This passivation step may be carried out by switching to a pure N2 plasma in the CVD chamber to form SiON to a thickness that is less than the thickness of the depletion layer 18. For example, the passivation layer 20 could have a thickness of 25 Angstroms or less, for example. Typically, a higher source power will be used in the CVD chamber, for example, 300-400 watts, to cause the nitrogen to bond with the SiO surface to yield an SiON dielectric barrier. This passivated dielectric barrier layer lessens the potential that fluorine atoms will diffuse up to the surface of layer 16 and react with, for example, a Ti or TiN barrier metal.

[0028] Note that less bias power (the bias power is different than the plasma power) and a higher pressure condition should be used to treat sidewalls and vias in the SiOF layer 16. For example, a bias power of less than 100 watts could be utilized. One purpose for the lower bias power is to make the plasma less directional so that it will affect the sidewalls.

[0029] The exact thickness of the passivation layer 20 may be optimized empirically. Note that a SIMS analysis may be performed to measure the thickness of the depletion layer 18 and the thickness of the passivation layer 20. Ultimately, optimization is achieved when the depletion and passivation layer thickness are such that it can be assumed that the subsequent layer 22 will not peel off during the remaining process steps for the semiconductor chip.

[0030] A typical device realized using the present invention method might have bulk SiOF layer 16 of 8,000 Angstroms to 15,000 Angstroms, with a depletion layer 18 of 50 Angstroms, and a passivation layer 20 of 25 Angstroms.

[0031] Next, a conducting layer 22 is deposited. By way of example, an in-situ deposition of optimized CVD-TiN may accomplished in the previously mentioned CVD chanber using a nitrogen-rich initial layer. This deposition would then be followed by a standard blanket tungsten deposition to form a layer 24. Note that the present invention is not limited to TiN and Ta. A variety of metals are available to form these conducting layers, including Ti, TiN, Ta, Al, and Cu, for example.

[0032] It should be noted that although the present invention is particularly advantageous when used to form an SiOF inter-metal dielectric layer, it has application in any situation where the fluorine atoms in an SiOF layer are causing interaction and/or adhesion problems with other layers.

[0033] The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiment was chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, and their equivalents.

Referenced by
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US6846745 *Jan 28, 2002Jan 25, 2005Novellus Systems, Inc.High-density plasma process for filling high aspect ratio structures
US7067440Jul 13, 2004Jun 27, 2006Novellus Systems, Inc.Gap fill for high aspect ratio structures
US7122485Dec 9, 2002Oct 17, 2006Novellus Systems, Inc.Deposition profile modification through process chemistry
US7163896Dec 10, 2003Jan 16, 2007Novellus Systems, Inc.Biased H2 etch process in deposition-etch-deposition gap fill
US7176039Sep 21, 2004Feb 13, 2007Novellus Systems, Inc.Dynamic modification of gap fill process characteristics
US7211525Mar 16, 2005May 1, 2007Novellus Systems, Inc.Hydrogen treatment enhanced gap fill
US7217658Sep 7, 2004May 15, 2007Novellus Systems, Inc.Process modulation to prevent structure erosion during gap fill
US7344996Jun 22, 2005Mar 18, 2008Novellus Systems, Inc.Helium-based etch process in deposition-etch-deposition gap fill
US7381451Nov 17, 2004Jun 3, 2008Novellus Systems, Inc.Strain engineering—HDP thin film with tensile stress for FEOL and other applications
US7476621Mar 1, 2006Jan 13, 2009Novellus Systems, Inc.Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill
US7482245Jun 20, 2006Jan 27, 2009Novellus Systems, Inc.Stress profile modulation in STI gap fill
US8133797May 16, 2008Mar 13, 2012Novellus Systems, Inc.Protective layer to enable damage free gap fill
Classifications
U.S. Classification438/629, 257/E23.167, 257/E21.276
International ClassificationH01L23/532, H01L21/316
Cooperative ClassificationY10S257/915, H01L21/02131, H01L21/02274, H01L23/5329, H01L21/31629, H01L21/0214, H01L21/02332, H01L21/0234
European ClassificationH01L21/02K2E3B6B, H01L21/02K2C1L1F, H01L21/02K2T8B4B, H01L21/02K2T8H2, H01L21/02K2C1L1P, H01L23/532N, H01L21/316B6
Legal Events
DateCodeEventDescription
Mar 11, 2013FPAYFee payment
Year of fee payment: 12
Jun 22, 2009FPAYFee payment
Year of fee payment: 8
Jun 2, 2009ASAssignment
Owner name: AMD TECHNOLOGIES HOLDINGS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:022764/0488
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMD TECHNOLOGIES HOLDINGS, INC.;REEL/FRAME:022764/0544
Effective date: 20090302
Jun 30, 2005FPAYFee payment
Year of fee payment: 4
Jun 4, 2002CCCertificate of correction