|Publication number||US20010045595 A1|
|Application number||US 09/425,243|
|Publication date||Nov 29, 2001|
|Filing date||Oct 25, 1999|
|Priority date||Sep 15, 1997|
|Also published as||CN1147001C, CN1211827A, US6069381|
|Publication number||09425243, 425243, US 2001/0045595 A1, US 2001/045595 A1, US 20010045595 A1, US 20010045595A1, US 2001045595 A1, US 2001045595A1, US-A1-20010045595, US-A1-2001045595, US2001/0045595A1, US2001/045595A1, US20010045595 A1, US20010045595A1, US2001045595 A1, US2001045595A1|
|Inventors||Charles Thomas Black, Jeffrey John Welser|
|Original Assignee||Charles Thomas Black, Jeffrey John Welser|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (7), Classifications (16)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 This invention relates to microelectronics, and in particular to field effect transistors (FET's) that have a source, a drain, a channel therebetween, a floating gate over the channel, a ferroelectric material over the floating gate and a gate electrode over the ferroelectric material. This novel FET has particular application in high speed, high density computer memories.
 While FET's have uses throughout the microelectronics field, a major application is in memory cells for storage of data. According to standard industry practice, memory cells are currently formed in semiconductor materials such as silicon by a combination of an FET transistor and a capacitor which may, for example, be deep-etched into the silicon nearby and can store electric charge. While such memory cells, when combined to form DRAM's (Dynamic Random Access Memory) and SRAM's (static Random Access Memory), now dominate fast-access data storage in computer systems, they have a major drawback—they lose all their information when the power is removed. As a result, there has been a very strong interest in creating nonvolatile memory for low power applications. As is well known, FET's are also used in EEPROM, Flash memory and other non-volatile memory applications.
 Single-transistor memory cells using ferroelectric materials were first proposed in the 1960's and have been pursued since the early 1970's. These materials provide a means for nonvolatile information storage because of the inherent stability of the two ferroelectric polarization states. It is thought that the polarization charge of a ferroelectric material could be used to change the surface conductivity of a semiconductor material. In effect, such ferroelectric FET's would store information using the polarization direction, rather than using an excess electron charge on a capacitor or a floating gate—the current industry standard for memory cells. Because of their non volatility and their fast switching speeds (<1 ns), ferroelectrics have become attractive candidates for future generations of DRAM. Recently, several designs for ferroelectric memory transistors have been proposed that have significant shortcomings which limit their effectiveness for low-voltage, high-speed, high-density (i.e. DRAM-like) memory applications.
FIG. 1 (prior art) illustrates the operating principle of a ferroelectric memory transistor. The device 1 is essentially a MOSFET with a piece of ferroelectric material 2 positioned somewhere above the Si channel 3 c between source 3 s and drain 3 d. When the ferroelectric is polarized in one direction 4 (“downward” as depicted in FIG. 1(a)), a read voltage Vgs applied to the gate 5 induces an inversion layer in the transistor channel. If a voltage bias is placed across the source-drain, a current will flow through the transistor. A different case is shown in prior art FIG. 1(b), where the ferroelectric is polarized in the opposite direction 6. Because the ferroelectric is polarized differently, the same read voltage Vgs applied to the gate does not induce an inversion layer for conduction in the channel 3 c, and so little current flows. The threshold voltage of the transistor is thus controlled via the direction of ferroelectric polarization. An attractive feature of this type of device is that information is stored in the polarization state of the ferroelectric, and so the information remains undisturbed when power is removed from the device.
 Attempts to reduce this principle to practice have followed two main avenues. In the first design, the ferroelectric material is either placed directly on the Si transistor channel (as described in Rost et al, in Appl. Phys. Lett. 59, 3654, 1991 and in Sugubuchi et al., in J. Appl. Phys. 46, 2877, 1975), or alternatively on a dielectric layer which itself covers the channel (for example, see Chen et al in Appl. Phys. Lett. 69, 3275, 1996, Tokumitsu et al in IEEE Electron Device Letters 18, 160, 1997, Yu et al at Appl. Phys. Lett. 70, 490, 1997, and Hirai et al at Jpn. J. Appl. Phys. 33, 5219, 1994). This device geometry results in a strong electrostatic coupling between the top gate and the channel. Although this device design has several attractive features, it suffers severe fabrication difficulties, including diffusion of the ferroelectric into the Si channel, and uncontrolled formation of thin SiO2 layers at the Si/ferroelectric interface during thermal treatments. As a result of problems introduced by these fabrication issues, devices of this type have shown slow switching speeds (see Tokumitsu et al, supra, and Sugibuchi et al, supra), high operating voltages (see Chen et al, supra, Tokumitsu et al, supra, Rost et al, supra, and Sugibuchi et al, supra), and poor memory retention characteristics (see Yu et al, supra, and Hirai et al, supra).
FIG. 2 (prior art) shows a second (and more promising) design of a ferroelectric FET for use in memory applications, as described in Chen et al, supra, Nakamura et al at IEDM, 68, 1995, and in U.S. Pat. No. 5,365,094, issued Nov. 15, 1994 to H. Takasu). In this device, an electrically conducting (e.g. metal) floating gate 7 is inserted between the ferroelectric film 2 and a bottom gate insulator 8 (which is typically SiO2). From a fabrication standpoint, this device is attractive because the ferroelectric is separated from the Si channel by both the floating gate and a SiO2 layer. A suitable floating gate material (e.g. Pt or Ir) can be used to prevent diffusion of the ferroelectric material into the channel.
 A main drawback of this type of structure is the high voltage required for changing the polarization of the ferroelectric. By adding the SiO2 and floating gate layers to the gate stack, the ferroelectric becomes much more weakly coupled to the Si channel. For a given voltage applied to the gate only a fraction of Vgs is applied across the ferroelectric (and thus only a fraction of the applied voltage is available for writing the cell). Ferroelectric materials have large dielectric constants (typically between about 100-500) compared to SiO2 (about 3.9), which means that to sustain a reasonable voltage across the ferroelectric, a significantly higher voltage must be applied to the gate. In general the voltage required to write information to this device is much larger than that necessary for reading. All devices of this type built to date use operating voltages in excess of 5 V (see Chen et al, supra, and U.S. Pat. No. 5,365,094), while for high-density memory applications, the maximum operating voltages should be less than 3V.
 One interesting proposal has been to use a high-dielectric constant material (such as barium strontium titanate) in place of the SiO2 layer 8, to more closely match the dielectric constants of the two insulators in the gate stack (see Tokumitsu et al, supra, and U.S. Pat. No. 5,365,094). This would enable the memory device to function at lower voltages, although it introduces problems in fabrication similar to those discussed above with regard to the first type of ferroelectric FET design. Even with more closely matched dielectrics however, it is still impossible to use the entire gate voltage Vgs for writing the memory cell.
 The present invention therefore provides a field effect transistor comprising a source region and a drain region formed in a semiconductor material, a channel region disposed between said source region and said drain region, an insulating layer of electrically insulating material disposed over said channel region, a floating gate layer of electrically conducting material disposed over said insulating layer, a layer of electrically nonconducting ferroelectric material disposed over said floating gate layer, a gate electrode overlying said layer of ferroelectric material, and an electrical resistor for resistively coupling said floating gate layer to at least one of said source region, drain region, and channel region.
 According to a preferred embodiment of the invention, the aforesaid electrical resistor comprises the aforesaid insulating layer, which is disposed between the channel region and the floating gate layer; to serve as an electrical resistor, the aforesaid layer of insulator is made sufficiently thin to exhibit electrical resistance by acting as a quantum-mechanical tunnel barrier, permitting electron tunnelling through said layer. For example, the semiconductor material can be silicon and the aforesaid insulating material is preferably SiO2.
 When a voltage is applied to the aforesaid gate electrode, then the source region and the drain region are at an initial first potential and the aforesaid floating gate layer is at an initial second potential. Due to the resistive coupling, the potential of the floating gate will approach that of the source/drain region. The amount of time required, as measured by a “characteristic time” defined to be the time required for said floating gate layer to change its potential from said initial second potential to a value halfway between said first potential and said initial second potential, can be varied by the amount of resistance, and will be determined by the desired application. If the FET is to be used as an EEPROM device, the time should be less than about 1 second.
 For use in Flash memory devices, it is preferable that the characteristic time be less than about 1 millisecond.
 For use in DRAM memory devices, it is preferable to select the characteristic time to be is less than about 100 nanoseconds, and desirably less than 10 nanoseconds.
 Preferably, for DRAM applications, the layer of SiO2 should have a thickness of no more than 40 Angstroms, or even 15 Angstroms, in order to permit direct quantum-mechanical electron tunnelling as aforesaid.
 According to another preferred embodiment, the aforesaid transistor may have a fabricated resistor coupled to at least one member of the group consisting of said source region, said drain region, and said channel region. Preferably, the fabricated resistor is composed of doped polysilicon and coupled to at least one member of the group consisting of said source region, said drain region, and said channel region.
 The ferroelectric layer itself may be composed of any available ferroelectric material, including, for example, LiNbO3, BaTiO3, PbTiO3, Bi3Ti4O12, SrBi2TaO9, SrBi2TaxNb1−xO9, and PbZrxTi1−xO3.
 The present invention will be understood more fully with reference to the detailed description herein, when taken together with the accompanying drawings, wherein:
FIGS. 1a and 1 b illustrate the operating principles of a ferroelectric transistor in accordance with the prior art.
FIG. 2 is a crossectional view of the prior art ferroelectric FET transistor with a floating gate, along with a corresponding schematic circuit diagram thereof.
FIG. 3 is a crossectional view of a ferroelectric FET transistor in accordance with the present invention, along with a corresponding schematic circuit diagram thereof.
FIG. 4 is a schematic circuit diagram of a memory cell utilizing an FET transistor in accordance with the present invention.
FIG. 5 is graph that illustrates the relationship of the floating gate voltage with time elapsed after the gate voltage is applied, for both a positive and a negative polarization of the ferroelectric layer in a FET transistor according to the present invention.
FIG. 6 is a graph (based on Rana et al, Appl. Phys. Lett. 69, 1104, 1996) that illustrates the relationship between current density and gate voltage for SiO2 resistor layers of several thicknesses in FET transistors constructed in accordance with the present invention.
FIG. 7 is a cross-sectional view of a FET transistor constructed in accordance with a second embodiment of the invention, using a fabricated resistor to connect the floating gate to the source and drain regions.
FIG. 3 illustrates the ferroelectric memory transistor according to the present invention, in partly schematic form. In contrast to the designs discussed previously, the floating gate of this device is both capacitively and resistively coupled to the Si channel. Different ways for accomplishing this will be described hereinafter. As will be shown, this transistor is both readable and writable at high speeds and with low voltages.
 When a voltage Vgs is applied to the gate 5 of this device, Vgs is initially divided between the ferroelectric capacitor and the oxide capacitor, so that the floating gate potential VFG is raised to a fraction of the total applied voltage:
V FG=(C FE V gs +ΔP)/(C FE +C OX)
 where CFE and COX are the capacitances of the ferroelectric and oxide capacitors respectively, Vgs is the voltage applied to the gate, and ΔP is the change in ferroelectric polarization on applying the voltage to the gate. The voltage across the ferroelectric is:
V FE =V gs −V FG=(C OX V gs −ΔP)/(C FE +C OX)
 Because of the resistive coupling between floating gate 7 and channel 3 c (denoted by a resistance ROX), the floating gate potential does not stay fixed. In response to an applied voltage, charge flows through the resistor, bringing the floating-gate potential to that of the source/drain. After a certain amount of time, the entire voltage Vgs is dropped across the ferroelectric 2, and can thus be used to change the polarization state of ferroelectric 2. Unlike previous device designs, the full gate amplitude can be used to write the device.
 The time it takes for the floating-gate potential to change depends on intrinsic device characteristics such as the coupling resistance between floating gate 7 and all of the channel, source and drain, the capacitance of the ferroelectric capacitor, and the polarization state of the ferroelectric 2. For the purposes of this discussion, the characteristic time, T, for the floating gate potential to change, is defined as follows: when a voltage Vgs is applied to the gate electrode 5, then T is the time it takes for the floating-gate potential to change from its initial value (just after the voltage is applied to the gate) to halfway between its initial value and the source/drain potential (Vs/d).
 For example, information can be written to the device according to the following scenario. First, the source/drain voltage (Vs/d) is set to zero, and 3 Volts are applied to the gate electrode as Vgs. Immediately after Vgs is applied, the floating-gate voltage (VFG) rises to a maximum value (between 0 and 3 V) given by Equation (1). As time passes, VFG decreases toward Vs/d=0V. We define T as the time required for VFG to decay halfway to Vs/d. As will be understood, the requirements on T will depend on device application. For DRAM applications, it is desirable to have T on the order of 10 nanoseconds, and generally less than 100 ns. For Flash memory, T can be on the order of 100 ns, and generally less than 1 millisecond. On the other hand, EEPROM devices can be slow, with a T on the order of 1 second, and still be useful.
 Reading the information in the inventive cell can be carried out in the following way: When a read voltage pulse is applied to the gate 5, the potential of the floating gate VFG is initially given by Equation (1). As Equation (1) shows, this potential differs depending on the initial polarization state of the ferroelectric 2 (i.e. depending on the information that was stored in the cell). As shown schematically in FIG. 4, if the transistor source and drain have been suitably biased prior to device reading, current Id will flow through the transistor. The magnitude of the current Id through the transistor is mainly controlled by the floating gate potential, VFG. As described hereinabove, because of the resistive coupling between floating gate 7 and source/drain/channel 3 s/3 d/3 c, the floating-gate potential VFG changes over a characteristic time T. When the floating-gate potential, VFG, approaches Vs/d, the transistor turns off. FIG. 5 illustrates the drop in floating-gate potential after a read pulse. As shown in FIG. 5, the time it takes for the floating-gate potential, VFG, to drop is different depending on the polarization state of the ferroelectric. Therefore, the state of the memory cell can be read by measuring how much current flows through the device during a read pulse.
 The floating gate 7 is resistively coupled to the transistor channel using either a fabricated resistor, or a very thin SiO2 layer. For SiO2 layers less than 40 Angstroms thick, electrons can move through the insulator via direct quantum mechanical tunneling. This type of tunneling process does not degrade the thin oxide, and therefore does not shorten the device lifetime. FIG. 6 plots current-voltage curves for thin oxide layers (<about 35 Angstroms) as a function of voltage (see Rana et al, supra).
 Using these curves to extract oxide resistances per unit area, device switching speeds on the order of 200 ns for a 15 Angstrom oxide, and <20 ns for a 12.5 Angstrom oxide can be calculated. (These numbers are estimated assuming a ferroelectric dielectric constant of 500, and a ferroelectric thickness of 3000 Angstroms.) These device switching speeds are much faster than the speeds of existing non-volatile memories, and can approach DRAM speeds using extremely thin oxides and suitable (low dielectric constant) ferroelectrics such as described in U.S. Pat. No. 5,365,094, supra, and in Rost et al, supra.
 As an alternative to a very thin SiO2 layer for the resistive coupling between gate and channel, the transistor can include a fabricated resistor 9 between floating gate 7 and source 3 s (and/or drain 3 d) as shown in FIG. 7. Although slightly complicating the fabrication process, this geometry would allow the device to have a slightly thicker SiO2 layer (which would be more robust). It would also allow a finer control of the floating gate coupling resistance.
 The ferroelectric memory FET described herein offers significant advantages over existing non-volatile memory technologies, including all other proposed ferroelectric memory transistor designs. Because of the resistive coupling of floating gate to transistor channel, the memory can be both read and written using low voltages, and with speeds approaching that of DRAM. Because the memory cell consists of only a single transistor, memory can be very highly integrated. Finally, this device is attractive from a processing standpoint as well. The ferroelectric material is deposited onto a planar, metallic substrate, which alleviates step coverage and interface issues. Also, the ferroelectric thickness is not a critical device dimension, meaning that the ferroelectric film can be kept relatively thick in order to reduce leakage currents.
 Although the invention has been described with reference to an FET transistor for use with nonvolatile memory applications, other applications of the inventive concepts disclosed herein will be apparent to those skilled in the art. Accordingly, it is intended that all such applications of the invention be encompassed by the claims that follow.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7135736||Jul 11, 2003||Nov 14, 2006||Matsushita Electric Industrial Co., Ltd.||Semiconductor device|
|US7193264||Oct 28, 2003||Mar 20, 2007||Toumaz Technology Limited||Floating gate transistors|
|US7352605 *||Jul 7, 2006||Apr 1, 2008||Hynix Semiconductor Inc.||Nonvolatile ferroelectric memory device and method thereof|
|US8228730||Aug 31, 2010||Jul 24, 2012||Micron Technology, Inc.||Memory cell structures and methods|
|US8498156||Jul 20, 2012||Jul 30, 2013||Micron Technology, Inc.||Memory cell structures and methods|
|US8687432 *||Jan 17, 2012||Apr 1, 2014||National Chiao Tung University||Multi-bit resistive-switching memory cell and array|
|US20130119340 *||Jan 17, 2012||May 16, 2013||National Chiao Tung University||Multi-bit resistive-switching memory cell and array|
|U.S. Classification||257/316, 257/E29.304, 257/E29.272|
|International Classification||H01L29/78, G11C11/22, H01L27/105, H01L29/788, H01L21/8247, H01L29/792, H01L27/10, H01L21/8246|
|Cooperative Classification||H01L29/7883, G11C11/223, H01L29/78391|
|European Classification||H01L29/788B4, H01L29/78K|