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Publication numberUS20010048332 A1
Publication typeApplication
Application numberUS 09/754,514
Publication dateDec 6, 2001
Filing dateJan 4, 2001
Priority dateFeb 24, 2000
Also published asUS6351174
Publication number09754514, 754514, US 2001/0048332 A1, US 2001/048332 A1, US 20010048332 A1, US 20010048332A1, US 2001048332 A1, US 2001048332A1, US-A1-20010048332, US-A1-2001048332, US2001/0048332A1, US2001/048332A1, US20010048332 A1, US20010048332A1, US2001048332 A1, US2001048332A1
InventorsJose Soltero, Dale Stein
Original AssigneeSoltero Jose M., Stein Dale P.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Vcc-compensated bus-hold circuit
US 20010048332 A1
Abstract
A hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch.
In a preferred embodiment, a bus-hold integrated circuit servicing Insulated Gate FET digital switches can be operated from either of two distinct ranges of supply voltage (VCC). The magnitudes of the holding currents for the higher range of VCC are nearly the same as those for the lower range of VCC. This characteristic is achieved by changing the resistance in the feedback path of the bus-hold circuit according to the applied VCC. Resistance is increased by turning off wider channel IGFETs that are connected in parallel with narrower channel IGFETs when the higher range of VCC is applied. When the lower range of VCC is applied the wider channel IGFETs are switched on and the resistance of the holding current path is decreased in proportion to the decrease in VCC.
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Claims(10)
We claim:
1. A hold circuit for holding a digital switch, said digital switch having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving said digital switch, said hold circuit comprising:
an inverter having an input connected to said output of said digital switch and having an output; and
a variable resistor having a port connected to the output of said inverter and having a port connected to the input of said digital switch.
2. The hold circuit of
claim 1
further comprising a fixed resistor connected in series with said variable resistor between the output of said inverter and the input of said digital switch.
3. The hold circuit of
claim 1
, wherein said digital switch is powered by a power supply having a supply voltage, and wherein the value of said supply voltage may be in either of two different ranges, further comprising a circuit for determining a resistance value of said variable resistor, said resistance value being determined by the value of the supply voltage that is applied to the hold circuit.
4. A hold circuit for holding a CIGFET digital switch, said CIGFET digital switch having an input and having an output and comprising a first p-channel IGFET and a first n-channel IGFET, at the level of its last driven state regardless of whether the output impedance of the bus driver is high or low, said hold circuit comprising:
a CIGFET inverter comprising a second p-channel IGFET having a gate, a drain and a source, said source being tied to a supply voltage, and a second n-channel IGFET having a gate, a drain and a source, said source being tied to ground, the gates of both of said IGFETs being driven by the output of the CIGFET digital switch;
a first variable resistor, connected between the drain of said second p-channel IGFET and a first port of a fixed resistor;
a second variable resistor, connected between the drain of said second n-channel IGFET and said first port of said fixed resistor; and
a second port of said fixed resistor being connected to the input of said CIGFET digital switch.
5. The hold circuit of
claim 4
, wherein said CIGFET digital switch is powered by a power supply having a supply voltage, and wherein the value of said supply voltage may be in either of two different ranges, a higher range and a lower range, further comprising:
a first circuit for determining a resistance value of said first variable resistor, said resistance value being determined by the value of the supply voltage that is applied to the hold circuit
a second circuit for determining a resistance value of said second variable resistor, said resistance value being determined by the value of the supply voltage that is applied to the hold circuit.
6. The hold circuit of
claim 4
, wherein:
said first variable resistor is implemented by a pair of CIGFETs connected in parallel between the drain of said second p-channel IGFET of said inverter and said first port of said fixed resistor, and
said second variable resistor is implemented by a pair of CIGFETs connected in parallel between the drain of said second n-channel IGFET of said inverter and said first port of said fixed resistor.
7. The hold circuit of
claim 6
, wherein said first variable resistor comprises:
a wide p-channel IGFET having a source, a gate and a drain, said gate being tied to a first bias input,
a narrow p-channel IGFET having a source, a gate and a drain, said gate being tied to ground,
the sources of both said wide p-channel IGFET and said narrow p-channel IGFET being connected together at the drain of said second p-channel IGFET, and the drains of both said wide p-channel IGFET and said narrow p-channel IGFET being connected together at said first port of said fixed resistor.
8. The hold circuit of
claim 6
, wherein said second variable resistor comprises:
a wide n-channel IGFET having a source, a gate and a drain, said gate being tied to a second bias input,
a narrow n-channel IGFET having a source, a gate and a drain, said gate being tied to said power supply,
the sources of both said wide n-channel IGFET and said narrow n-channel IGFET being connected together at the drain of said second n-channel IGFET, and the drains of both said wide n-channel IGFET and said narrow n-channel IGFET being connected together at said first port of said fixed resistor.
9. The hold circuit of
claim 7
, wherein:
said wide p-channel IGFET is turned on by said first bias input when the applied supply voltage is in said lower range of said supply voltage, and
said wide p-channel IGFET is turned off by said first bias input when the applied supply voltage is in said higher range of said supply voltage.
10. The hold circuit of
claim 8
, wherein:
said wide n-channel IGFET is turned on by said second bias input when the applied supply voltage is in said lower range of said supply voltage, and
said wide n-channel IGFET is turned off by said second bias input when the applied supply voltage is in said higher range of said supply voltage.
Description
TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to the field of hold circuits, such as bus-hold circuits. More particularly, it relates hold circuits that may be used with power supplies of differing supply voltage.

BACKGROUND OF THE INVENTION

[0002] An IGFET circuit used as a digital switch can be left with a floating input either by design or in bus applications when all devices driving the bus are in 3-state. In this state the transistors on both sides of the driving circuits are turned off leaving them with high output impedance. A floating input of an IGFET circuit allows the capacitance of the IGFET gate to gradually charge. If the gate is sufficiently charged, the resulting voltage on the gate causes static current to flow through the IGFET, causing wasted power dissipation. Further, if the gate voltage rises even further, it can reach a certain threshold where a more serious consequence can occur. In the worst case condition, it can draw enough current from the supply to ground to destroy the metal lead and render the device useless.

[0003] Initially, external static pull-up or pull-down resistors were used to prevent floating of unused gates. These static resistors connect the gate either to the supply voltage, VCC, or ground, but still cause wasted power dissipation. For bus applications where a bus driver must drive the input, bus-hold circuits have been developed. The function of a bus-hold circuit is to hold the input of the digital switch, i.e., the gate of the IGFET, to the state previously set by the bus driver. The hold must be strong enough to prevent the input from floating (charging) but weak enough to allow the input to be driven by the bus driver. Initially, these were external circuits. Now bus-hold circuits are integrated into the IGFET (including CMOS) digital IC.

[0004] In the known art, a bus-hold circuit is a digital signal feedback path from the output of a digital switch to its input, consisting of an inverter and a current-limiting resistor. The purpose of the feedback is to hold the input to its last driven state until it is driven to the alternate state.

[0005] Current flows through the resistor only during the switching period when, due to propagation delays, there is a voltage difference between the output of the inverter and the input of the digital switch. Since voltage drops across the resistor occur only for brief intervals during state changes, bus-hold circuits significantly reduce the power dissipation.

[0006] The holding current through the resistor becomes the critical parameter for power dissipation by a bus-hold circuit. The magnitude of the holding current depends upon the values of the resistor and VCC. If the bus-hold circuit is used with a higher value of VCC then the magnitude of the hold override current is proportionately higher and the circuit dissipates more power in proportion to the square of the current.

[0007] Historically, the values of VCC for digital switches on IGFET integrated circuits have decreased as the state of the technology progresses. For CMOS, they have diminished from 5V to 3.3V, to 2.5V and to 1.8V. It is likely that this progression to still lower values of VCC will continue. An important benefit of evolving the technologies to operate from a lower value of VCC is that the magnitudes of the hold override currents also are reduced. That lowers the power consumption of the bus-hold circuit. This evolution to lower VCC creates the need for bus-hold circuits that can operate at two different values of VCC so it can be used with either version of the technology.

SUMMARY OF THE INVENTION

[0008] The present invention provides a hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch.

[0009] In accordance with a preferred embodiment of the present invention, a VCC-compensated bus-hold circuit is provided that can operate from either of two adjacent values of VCC without increasing the holding currents at the higher value of VCC. This duality in circuit behavior results from introducing a variable resistor (whose resistance depends on which of the two values of VCC is applied) between the bus-hold inverter and the current limiting resistor. The dual-valued variable resistor is implemented using two transistors of different strengths connected in parallel. The transistor with the smaller channel width and therefore higher resistance is biased on continuously. When the lower value of VCC is applied, the transistor with the larger channel width and therefore lower resistance is also turned on and the parallel combination has a lower resistance. When the higher value of VCC is applied, the transistor with the larger channel width is turned off and the parallel combination then has a higher resistance. A bias circuit with VCC as input supports the operation of this embodiment. This bias circuit uses the VCC value to control the state (ON or OFF) of that transistor in the parallel pair that has the larger channel width. If the lower value of VCC is applied then the transistor with the larger channel width is turned on and the resistance is lowered. If the higher value of VCC is applied then that transistor is turned off and the resistance is increased to a value that keeps the magnitudes of the holding currents approximately the same as for the lower value of VCC.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 illustrates a prior art bus-hold circuit.

[0011]FIG. 2 shows an example of a prior art bus-hold circuit implemented in CIGFET technology.

[0012]FIG. 3 is a graph of the typical holding current characteristics of a prior art bus-hold circuit.

[0013]FIG. 4 illustrates a first preferred embodiment of the present invention.

[0014]FIG. 5 illustrates a second preferred embodiment of the present invention, in a CIGFET digital switch IC.

[0015]FIG. 6 shows a third preferred embodiment of the present invention.

[0016]FIG. 7 illustrates the variation in holding currents of a preferred embodiment, for various conditions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017]FIG. 1 illustrates a known art bus-hold circuit consisting of an inverter 11 and a resistor 13 that are connected in series from the output to the input of an IGFET switch 10. If the input 14 is in a low state then the output 15 is in a high state. This puts the output of inverter 11 in a low state, and resistor 13 becomes a pull-down resistor with current flowing through it only during the switching period when there is a voltage difference between the output of 11 and the input of 10. Conversely, when the input 14 is high, the output 15 is low and the output of inverter 11 is high. In this state, resistor 13 is a pull-up resistor and current flows through it only during the switching period when there is a voltage difference between the output of 11 and the input of 10. Since voltage drops across resistor 13 occur only for brief intervals during state changes, as mentioned above bus-hold circuits significantly reduce the power dissipation.

[0018]FIG. 2 illustrates a Complementary IGFET (CIGFET) implementation of the known art bus-hold circuit 16. CMOS is a special case of the more general class of CIGFET circuits. CIGFET transistor pair 17 & 18 forms the inverter of the bus-hold circuit. The digital switch 3 is also a pair of CIGFET transistors 19 & 20.

[0019]FIG. 3 is a graphical plot of input current (IIN) versus input voltage (VIN) that characterizes the operation of a typical bus-hold circuit.

[0020] Referring now also to FIG. 1, IIN is defined as the current that flows from the output of the inverter through resistor 13 to the digital switch input 14. When the input is in the low state, VIN<VTHL (the threshold voltage at which the output of digital switch 10 remains in the high state). As the voltage at the input is driven from zero toward VTHL the value of IIN slowly begins to fall from zero toward ILHO, the low hold override current (also called the holding current, IHOLD) Near VIN=zero, the magnitude of the current is set by the value of resistor 13 (or 23, FIG. 2), and by the voltage difference between the input 14 (or 24, FIG. 2) and the output of inverter 11. As VIN approaches VTHL, IIN reaches its maximum negative value ILHO. Increasing VIN further strengthens the n-channel transistor and weakens the p-channel transistor of the digital switch, identified in FIG. 2 as transistors 20 and 19, respectively, thus forcing 15 (or 25, FIG. 2) to a low state and the output of the bus-hold circuit to a high state. IIN reverses and rises rapidly until VIN reaches VTHH (the threshold voltage at which the output of digital switch 10 remains in the low state). At this point, IIN reaches its maximum positive value IHHO the high hold override current. As VIN approaches VCC, IIN falls back to zero at a rate determined by the value of resistor 13 and the voltage difference between the output of inverter 11 and the input 14 to the digital switch. As the input 14 is driven from a high state to a low state, a similar process occurs as determined by this same IIN-VIN curve.

[0021] Referring to FIG. 2, the magnitudes of the hold override currents (ILHO and IHHO) depend upon the values of resistor 23 and VCC. Therefore, when the bus-hold circuit 16 is used with a higher value of VCC (for example, VCC=5V, instead of VCC=3.3V), the magnitudes of the hold override currents are proportionately higher and more power is dissipated by the circuit.

[0022]FIG. 4 shows a bus-hold circuit according to a first preferred embodiment of the present invention. A variable resistor 12 is provided in the bus-hold circuit between the inverter output and the resistor 13′, allowing the circuit to be operated with either of two prescribed values of supply voltage (VCC). The resistance of 12 switches between two values according to the value of the applied VCC. If the lower value of VCC is applied then 12 has the lower value of resistance. If the higher value of VCC is applied then 12 has the higher value of resistance. The holding currents, ILHO and IHHO, are thus made substantially independent of which of the two values of VCC is applied.

[0023]FIG. 5 shows a bus-hold circuit according to a second preferred embodiment of the present invention, in a CIGFET bus-hold circuit. In a circuit of this type, the variable resistance is divided into two components, 31 and 32. When VCC is set at the higher value (VCCH), 31 and 32 have higher resistance values. When VCC is set at the lower value (VCCL), they have lower resistance values.

[0024]FIG. 6, shows a third preferred embodiment of the present invention, which is a further application of the principles of the present invention to a CIGFET bus-hold circuit, but with enhancements over the circuit shown in FIG. 5. In the circuit shown in FIG. 6, four CIGFET switches (MPL, MNL, MPH and MNH) implement the two-state variable resistors 31 and 32 shown in FIG. 5. The drains of the digital switch CIGFET pair MPS and MNS at the output 45 are connected to the input gates of the bus-hold inverter CIGFET pair MPB and MNB. The drains of MPB and MNB are tied together at the node 41 on the bus-hold side of a current-limiting resistor 43 through two CIGFET pairs MPL/MNL, MPH/MNH, connected in parallel. The opposite side of resistor 43 is connected to the input 44 of the digital switch. The sources of MPL and MPH are connected to the drain of MPB. The sources of MNL and MNH are connected to the drain of MNB. The drains of MPL, MPH, MNL and MNH are connected to the node 41. The source of MPB and the gate of MNH are connected to VCC The source of MNB and the gate of MPH are connected to ground. The gate of MPL is connected to a first bias source B1, while the gate of MNL is connected to a second bias source B2.

[0025] A VCC-dependent bias circuit provides the bias sources B1 and B2. This bias circuit has two outputs, B1 and B2, where B1 and B2 have the following characteristics:

[0026] 1. If VCC=VCCL then B1=0.0V and B2=VCC

[0027] 2. If VCC=VCCH then B1=VCC and B2=0.0V

[0028] As mentioned above, the gate of MPL is connected to the bias circuit output B1, while the gate of MNL is connected to bias circuit output B2.

[0029] Since B2 is, in a sense, the complement or inverse of B1, CIGFET MPL and CIGFET MNL are either turned on or turned off in unison.

[0030] Transistors MPL and MNL are fabricated to have larger channel widths than transistors MPH and MNH. Thus they provide a lower resistance path for current when they are turned on. As such, their function can be considered in this context to be, effectively, that of resistors. If the value of VCC is at VCCL, then MPL and MNL are enabled.

[0031] This creates current paths through these two effective resistors. Resistor 31 is formed by the parallel combination of the lower channel resistance of MPL and the higher channel resistance of MPH. Resistor 32 is formed by the parallel combination of the lower channel resistance of MNL and the higher channel resistance of MNH. When VCC is at VCCH, then MPL and MNL are switched off and the values of the effective resistors 31 and 32 become the higher channel resistances through MPH and MNH, respectively. This keeps the bus-hold currents for the higher value of VCC approximately the same as those for the lower value of VCC. Thus, effective resistors 31 and 32 together comprise an effective variable resistor, wherein the variability is controlled by the switching on and off of MPL, MPH, MNL and MNH, as described above.

[0032]FIG. 7 shows the results of a transistor-level SPICE simulation of the embodiment shown in FIG. 6 for the specific VCC values: 3.0V and 4.5V. It shows two families of IIN-versus-VIN characteristic curves for a variety of transistor strengths and device temperature conditions. The family of curves on the left side of FIG. 7 (which terminate in a common left end point and a common right end point) were obtained for VCC=3.0V. The family of curves on the right side were obtained for VCC=4.5V. The curves in FIG. 7 show that in each case (I through V) of transistor strength and device temperature, the values of the hold override currents (ILHO and IHHO) for VCC=4.5V are very nearly the same as those for 3.0V.

[0033] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8508250Feb 17, 2012Aug 13, 2013Research In Motion LimitedAsymmetrical bus keeper
EP2581835A1 *Feb 17, 2012Apr 17, 2013Research In Motion LimitedAsymmetrical bus keeper
Classifications
U.S. Classification327/215
International ClassificationH03K3/356, H03K3/011, H03K3/037
Cooperative ClassificationH03K3/011, H03K3/037, H03K3/356165
European ClassificationH03K3/011, H03K3/356G4, H03K3/037
Legal Events
DateCodeEventDescription
Mar 18, 2013FPAYFee payment
Year of fee payment: 12
Jun 22, 2009FPAYFee payment
Year of fee payment: 8
Jun 30, 2005FPAYFee payment
Year of fee payment: 4
Jan 4, 2001ASAssignment
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SOLTERO, JOSE M.;STEIN, DALE P.;REEL/FRAME:011451/0258
Effective date: 20000301
Owner name: TEXAS INSTRUMENTS INCORPORATED P.O. BOX 655474, MS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SOLTERO, JOSE M. /AR;REEL/FRAME:011451/0258