US 20010050577 A1 Abstract In a method of evaluating the reliability of a TFT, time coefficient β, voltage coefficient d and temperature coefficient φ
_{0 }are experimentally produced from −BT stress tests, and the life of a TFT under −BT stress conditions is evaluated using the following expression:
where τ represents the life time of the TFT, ΔV
_{thτ} the tolerant threshold voltage shift amount of the TFT, t_{0 }(1/ΔV_{th0}) constant, q elementary electric charge, k Boltzmann constant, T temperature, V_{G }gate voltage, and t_{OX }the thickness of the gate oxide film. Claims(10) 1. In a TFT having a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, a method of evaluating the reliability of the TFT in a −BT stress state in which a gate is supplied with arbitrary constant voltage V_{G }and held at an arbitrary constant temperature T based on the following expressions: where ΔV
_{th }represents the threshold voltage shift amount of the TFT, t time, α time coefficient, q elementary electric charge, d voltage coefficient, k Boltzmann constant, t_{OX }the thickness of the gate oxide film, φ_{0 }temperature coefficient, and ΔV_{thτ} the tolerant threshold voltage shift amount of the TFT, and β=1/α said method comprising the steps of:
determining the time coefficient α in expression (3
a) based on the relation between a threshold voltage shift amount ΔV_{th }obtained from at least one −BT stress test and time t; determining voltage coefficient d in expression (4
a) based on the relation between a threshold voltage shift amount ΔV_{th }obtained from at least two −BT stress tests and different gate voltages V_{G }applied in the tests; determining the temperature coefficient φ
_{0 }in expression (5a) based on the relation between a threshold voltage shift amount ΔV_{th }obtained from at least two −BT stress tests and different temperatures T used in the tests; and in expression (6) obtained from the relation between expressions (3
a), (4a), determining the following constant of proportion using said determined time coefficient α, voltage coefficient d and temperature coefficient φ_{0}, , thereby obtaining the life of the TFT from expression (8) obtained by transforming expression (6) using said determined constant of proportion c
_{2 }and the tolerant threshold voltage shift amount ΔV_{thτ} of the TFT. 2. A method of evaluating the reliability of a TFT as recited in claim 1 in BT stress tests for TFTs (a) and (b), the threshold voltage shift amounts ΔV _{tha }and ΔV_{thb }of the TFTs (a) and (b) at the same temperature T and the same gate voltage V_{G}/t_{OX }at certain time t are produced, and the life of the TFT (b) is estimated by replacing ΔV_{th0 }in expression (8) obtained for the TFT (a) with ΔV_{th0}·ΔV_{thb}/V_{tha}. 3. A method of evaluating the reliability of a TFT as recited in claim 1 for a TFT in an SRAM memory cell, the threshold voltage of the TFT is determined according to a constant current method based on the current value of the TFT determined from the OFF current of bulk monocrystalline transistors arranged to form a CMOS inverter, and the difference between an initial threshold voltage thus determined and minimum power supply voltage necessary for guaranteeing data holding in said memory cell is used as a value for ΔV _{thτ}. 4. A method of evaluating the reliability of a TFT as recited in claim 1 for a TFT in an SRAM memory cell, the threshold voltage of the TFT is determined according to a constant current method based on an ON current value necessary for the TFT, and the difference between an initial threshold voltage thus determined and the operation power supply voltage is used as a value for ΔV _{thτ}. 5. In a TFT having a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, a method of evaluating the reliability of the TFT in a −BT stress state in which the gate is supplied with an arbitrary negative constant voltage V_{G }and held at a constant temperature T based on the following expressions: where ΔV
_{th }represents the threshold voltage shift amount of the TFT, t time, α time coefficient, q elementary electric charge, d voltage coefficient, k Boltzmann constant, t_{OX }the thickness of the gate oxide film, and ΔV_{thτ} the tolerant threshold voltage shift amount of the TFT, and β=1/α,
said method comprising the steps of:
determining the time coefficient α in expression (3
a) based on the relation between threshold voltage shift amounts ΔV_{th }obtained from at least one −BT stress test and time t; determining the voltage coefficient d in expression (4
a) based on the relation between threshold voltage shift amounts ΔV_{th }obtained from at least two −BT stress tests and different gate voltages V_{G }applied in the tests; and in expression (
6+ b) obtained from the relation between expressions (3a) and (4a), determining the following constant of proportion using said determined time coefficient α and voltage coefficient d, , thereby obtaining the life of the TFT by expression (8
b) obtained by transforming expression (6b) using said determined constant of proportion c_{2 }and the tolerant threshold voltage shift amount ΔV_{thτ} of the TFT. 6. A method of evaluating the reliability of a TFT as recited in claim 5 in −BT stress tests for the TFTs (a) and (b), the respective threshold voltage shift amounts ΔV _{tha }and ΔV_{thb }of the TFTs (a) and (b) at the same temperature t and the same gate voltage V_{G}/t_{OX }at certain time t are obtained, and the useful life of the TFT(b) is estimated by replacing ΔV_{th0 }in expression (8b) obtained for the TFT(a) with ΔV_{th0}·ΔV_{thb}/ΔV_{tha}. 7. In a TFT having a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, a method of evaluating the reliability of the TFT in a −BT stress state in which the gate is supplied with a predetermined negative constant voltage V_{G }and held at an arbitrary constant temperature T based on the following expressions: where ΔV
_{th }represents the threshold voltage shift amount of the TFT transistor, t time, α time coefficient, k Boltzmann constant, φ_{E }temperature coefficient, and ΔV_{thτ} the tolerant threshold voltage shift amount of the TFT, and β=1/α,
said method comprising the steps of:
determining the time coefficient a in expression (3
a) based on the relation between a threshold voltage shift amount ΔV_{th }obtained from at least one −BT stress test and time t; determining the temperature coefficient φ
_{E }in expression (5b) based on the relation between threshold voltage shift amounts ΔV_{th }obtained from at least two −BT stress tests and different temperatures T used in the tests; and in expression (6
c) obtained from the relation between expressions (3a) and (5b), determining the following constant of proportion using said determined time coefficient α and temperature coefficient φ_{E}, thereby obtaining the life of the TFT by expression (8
c) obtained by transforming expression (6c) using said determined constant proportion c_{2 }and tolerant threshold voltage shift amount ΔV_{thτ} of the TFT. 8. A method of evaluating the reliability of a TFT as recited in claim 7 in −BT stress tests for the TFTs (a) and (b), the respective threshold voltage shift amounts ΔV _{tha }and ΔV_{thb }of the TFTs (a) and (b) at the same temperature T and the same gate electric field V_{G}/t_{OX }at certain time t are obtained, and the life of the TFT (b) is estimated by replacing ΔV_{th0 }in expression (8c) obtained for the TFT (a) with ΔV_{th0}·ΔV_{thb}/ΔV_{tha}. 9. A TFT for use in an SRAM memory cell, comprising,
a channel layer of a silicon thin film, and a gate insulating film of a silicon oxide film, the threshold voltage of the TFT being set in advance shifted to the positive voltage side by the estimated amount of shift of the threshold voltage to the negative voltage side by a burn-in test. 10. A TFT operated with a power supply voltage V_{CC }and used at an absolute temperature T during operation, comprising,
a channel layer of a silicon thin film, and a gate insulating film of a silicon oxide film, said gate insulating film having a thickness of t _{OX}=qd|V_{G}|/2 kT, wherein t_{OX }represent the thickness of the gate insulating film, q elementary electric charge, d voltage coefficient, and k Boltzmann constant, said voltage coefficient d being determined in the following expression (4a) based on the relation between threshold voltage shift amounts ΔV_{th }obtained from at least two −BT stress tests and different gate voltages V_{G }in the tests, where q represents elementary electric charge, and k Boltzmann constant. Description [0001] 1. Field of the Invention [0002] The present invention relates generally to thin film transistors (TFT) and methods of evaluating reliability thereof, and more specifically, to a TFT including a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, and a method of evaluating reliability thereof. [0003] 2. Description of the Background Art [0004] TFTs are used for load transistors in the memory cells of a static random access memory (SRAM) or driver transistors for liquid crystal television pixels. When such products incorporated with TFTs are marketed, the reliability of TFTs should be evaluated. [0005] In FIG. 22, a typical top gate type P channel TFT is illustrated in a schematic cross section. In the TFT, an insulating film [0006] For reliability evaluation tests for the TFT as illustrated in FIG. 22, a hot carrier stress test, a breakdown voltage test for gate insulating film [0007]FIG. 23 sets forth one example of a bias condition in such a hot carrier stress test. In this example, source voltage V [0008] In FIG. 24, one example of a breakdown voltage evaluation test for a gate insulating film in a TFT is illustrated. In this example, for V [0009] It has been known that in a bulk silicon monocrystalline MOSFET the characteristic of the bulk MOSFET slightly degrades by a −BT (negative bias temperature) stress test by which the gate is supplied with constant voltage V [0010] The influence of −BT stress however is not exactly known. TFTs are therefore incorporated in SRAMs and the like and marketed without reliability evaluation by −BT stress tests. [0011] It is therefore an object of the invention to ascertain the influence of −BT stress upon a TFT and establish a method of evaluating reliability concerning the degradation of the characteristic of a TFT due to −BT stress. [0012] Another object of the invention is to provide a TFT satisfying reliability required in a −BT stress state based on thus established method of evaluating the reliability of a TFT due to −BT stress. [0013] A method of evaluating the reliability of a TFT according to a first aspect of the invention, in a TFT having a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, evaluates the reliability of the TFT in the −BT stress state in which the gate is supplied with an arbitrary negative constant voltage V [0014] where ΔV [0015] and is characterized in that the life of a TFT is produced from expression (8) obtained by modifying expression (6) from the determined constant proportion c [0016] A method of evaluating the reliability of a TFT according to a second aspect of the invention, in a TFT having a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, evaluates the reliability of the TFT in the −BT stress state in which the gate is supplied with an arbitrary constant voltage V [0017] where ΔV [0018] a step determining a constant of proportion given as follows using the determined time coefficient α and voltage coefficient d in expression (6 [0019] and the method is characterized in that the life of the TFT is produced from expression (8 [0020] A method of evaluating the reliability of a TFT according to a third aspect of the invention in a TFT having a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film evaluates the reliability of the TFT in the −BT stress state in which the gate is supplied with a predetermined negative constant voltage V [0021] where ΔV [0022] and the method is characterized in that the life of the TFT is produced from expression (8 [0023] A TFT according to a fourth aspect of the invention is used for an SRAM memory cell, includes a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, and is characterized in that the threshold voltage is shifted in advance toward positive voltage by the amount by which the threshold voltage is expected to shift toward negative voltage by a burn-in test. [0024] A TFT according to a fifth aspect of the invention is operated by gate voltage V [0025] where q represents elementary electric charge, k Boltzmann constant, and t [0026] In the method of evaluating the reliability of a TFT according to the first aspect of the invention, since life expected for the TFT is evaluated from expression (8) using time coefficient α, voltage coefficient d and temperature coefficient φ [0027] In the method of evaluating the reliability of a TFT according to the second aspect of the invention, since the TFT is limited for use at a predetermined constant temperature, life expected for the TFT can be evaluated without requiring at least two −BT stress tests at different temperatures T. [0028] In the method of evaluating the reliability of a TFT according to the third aspect of the invention, since the TFT is limited for use at a predetermined constant gate voltage V [0029] In the TFT according to the fourth aspect of the invention, since the threshold voltage is previously shifted toward the side of positive voltage by the amount of shift of the threshold voltage toward the side of negative voltage due to a burn-in test, a TFT for SRAM having an optimum characteristic can be provided after the burn-in test. [0030] In the TFT according to the fifth aspect of the invention, since the gate insulating film has the thickness of T [0031] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. [0032]FIG. 1 is a diagram showing one example of a TFT in a −BT stress state; [0033]FIG. 2 is a graph showing the shift of TFT due to −BT stress; [0034]FIG. 3 is a graph showing the time dependence of threshold voltage shift due to −BT stress for TFT and bulk monocrystalline MOSFET; [0035]FIG. 4 is a representation for use in illustration of the mechanism of threshold voltage shift of a TFT due to −BT stress; [0036]FIG. 5 is a graph showing the relation between time and threshold voltage shift amount in −BT stress; [0037]FIG. 6 is a diagram showing another example of −BT stress condition; [0038]FIG. 7 is a graph showing the relation between gate voltage and threshold voltage shift amount in a −BT stress test; [0039]FIG. 8 is a diagram showing another condition in a −BT stress test; [0040]FIG. 9 is a graph showing the relation between temperature and threshold voltage shift amount in a −BT stress test; [0041]FIG. 10 is a flow chart showing the procedure of a method of evaluating the reliability of a TFT using expression (6); [0042]FIG. 11 is a flow chart showing another procedure for readily conducting reliability evaluation for a TFT using the result of the reliability evaluation method shown in FIG. 10; [0043]FIG. 12 is a flow chart showing the procedure of a method of evaluating the reliability of a TFT for use at a predetermined temperature; [0044]FIG. 13 is a flow chart showing another procedure for readily evaluating the reliability of a TFT utilizing a result obtained by the reliability evaluation method shown in FIG. 12; [0045]FIG. 14 is a flow chart showing the procedure of a method of evaluating the reliability of a TFT which is used exclusively at certain determined gate voltage; and [0046]FIG. 15 is a flow chart showing another procedure for readily evaluating the reliability of a TFT using a result obtained by the reliability evaluation method in FIG. 14; [0047]FIG. 16 is an equivalent circuit diagram showing an example of an SRAM memory cell; [0048]FIG. 17 is a representation for use in illustration of the −BT stress state of a TFT in a memory cell in an SRAM; [0049]FIG. 18 is a graph showing the I [0050]FIG. 19 is a graph showing the I [0051]FIG. 20 is a graph showing another example of the I [0052]FIG. 21 is a graph showing the I [0053]FIG. 22 is a cross sectional view schematically showing one example of a TFT; [0054]FIG. 23 is a diagram showing one example of a hot carrier stress condition; and [0055]FIG. 24 is a representation for use in illustration of one example of gate breakdown voltage measurement. [0056] The inventors have found for the first time that the degradation of the electric characteristic due to −BT stress causes a problem in a TFT. The −BT stress state is the state in which the gate of a TFT is supplied with a negative bias voltage and held at a relatively high temperature. [0057] In FIG. 1, one example of such a −BT stress state is illustrated. In this example, for V [0058]FIG. 2 is a graph showing the result of a test in the −BT stress state illustrated in FIG. 1. In the graph, the abscissa represents gate voltage V [0059] The amount of shift of threshold voltage ΔV [0060] When TFTs operate as part of a CMOS (Complimentary MOS) circuit, a P channel TFT is put under the same bias condition as −BT stress at a higher time ratio, and therefore drain current does not continue to flow unlike the case of the hot carrier stress state. [0061] It can be understood from the above that the influence of −BT stress upon a TFT in terms of the reliability of the TFT is significant. [0062] As described above, degradation due to −BT stress has already been known in a bulk monocrystalline MOSFET. In a polysilicon TFT, however, since dangling bonds of silicon in grain boundaries are partly responsible for degradation due to −BT stress, the degradation of the polysilicon TFT due to the −BT stress is about ten times as large as the case of the monocrystalline MOSFET. [0063]FIG. 3 is a graph showing the results of −BT stress tests in a bulk monocrystalline MOSFET and a polysilicon TFT. In the graph, the abscissa represents time (sec), and the ordinate represents the amount of shift of threshold voltage −ΔV [0064] The inventors have ascertained the mechanism of threshold voltage shift due to −BT stress in a polysilicon TFT. [0065]FIG. 4 illustrates the mechanism of threshold voltage shift due to −BT stress in a polysilicon TFT. This mechanism is understood from FIG. 4 and the following expression (1). ≡Si [0066] More specifically, in polysilicon grain boundaries and the interface of polysilicon and SiO [0067] The inventors have found out that the amount of the shift of the threshold voltage can be expressed in a formula. The amount of shift ΔV [0068] where α represents time coefficient, φ [0069] In the following, a method of estimating the amount of shift of the threshold voltage ΔV [0070] First, the temperature of the TFT is for example set at 125° C., a temperature in the −BT stress state. At the temperature, I [0071] Then, as illustrated in FIG. 1, at temperature T=125° C., source S and drain D are connected to a potential of 0V and gate G is supplied with a negative voltage of −7V. This state is the −BT stress state, and time for initiating application of the gate voltage is set as t=0. [0072] After passage of prescribed time t, the −BT stress state is released, and threshold voltage V [0073] In FIG. 5, the abscissa represents time (sec), and the ordinate the amount of shift of threshold voltage −ΔV [0074] Based on the graph in FIG. 5, time coefficient α in the following expression (3) can be determined. Δ [0075] where V [0076] Now, in a polysilicon TFT manufactured under the same condition, as illustrated in FIG. 6, a −BT stress test in which a different gate voltage from process A is applied. In the example in FIG. 6, V [0077]FIG. 7 is a graph showing results of a plurality of −BT stress tests using different gate voltages V [0078] where V [0079] Note that the gate voltages V [0080] Hereinafter, the procedure for producing voltage constant d is called process B. Since |V [0081] In a polysilicon TFT manufactured under the same condition, as illustrated in FIG. 8, −BT stress test is conducted at a temperature different from the case of process A. In the example of FIG. 8, the temperature of 25° C. is used, and gate voltage is set to V [0082]FIG. 9 is a graph showing measurement results by the conditions in FIG. 1 and by the conditions in FIG. 8. In the graph, the abscissa represents the inverse number of temperature 1000/T(/K) and the ordinate the amount of shift of threshold voltage −ΔV [0083] In the example of FIG. 9, qφ [0084] Also in process C, by conducting tests under various more temperature conditions, the value of temperature coefficient φ [0085] By the above-described three processes A, B, and C, the amount of shift of threshold voltage ΔV [0086] Herein, t [0087] Processes A, B, and C may be conducted in an arbitrary order. In the above-described examples, voltage coefficient d produced in process B is used in process C, but if process C is conducted first, φ [0088] and then φ [0089] Using expression (6), the amount of shift of threshold voltage ΔV [0090] where β=1/α. More specifically, in expression (8), substituting the amount of shift of threshold voltage ΔV [0091] Note that the above-described method of evaluating reliability can be applied to a monocrystalline MOSFET. [0092]FIG. 10 is a flow chart showing a procedure in a method of evaluating the reliability of a TFT based on expression (8). In this figure, the procedure of the method of evaluating the reliability of the TFT using expression (8) can be understood visually more clearly. [0093] In the following, one example of a variation of the above-described reliability evaluation method will be described. If time coefficient α, voltage coefficient d, temperature coefficient φ [0094] have been already produced for the TFT (a), for example, the life of another TFT (b) can be estimated as follows. [0095] For TFT (b), at-least one −BT stress test is conducted, and the amount of shift of threshold voltage ΔV [0096] Once ΔV [0097] Since coefficients β, d and φ [0098]FIG. 11 is a flow chart for use in illustration of a method of readily estimating the life of a TFT using expression (8 [0099] If it is not necessary to estimate the life of the TFT at a temperature other than a certain predetermined temperature T [0100] The procedure of estimation of the life of the TFT in this case is illustrated in the flow chart in FIG. 12. [0101] Using the result related to TFT (a) obtained by the procedure in FIG. 12, the procedure of another method of estimation for the life of TFT (b) is illustrated in the flow chart in FIG. 13. More specifically, using the threshold voltage shift amounts ΔV [0102] Furthermore, if it is not necessary to estimate the life of the TFT at voltage other than predetermined gate voltage V [0103] The procedure in the method of evaluating the reliability of the TFT when it is not necessary to produce voltage coefficient d like this is illustrated in the flow chart in FIG. 14. [0104]FIG. 15 is a flow chart illustrating the procedure of another method of readily estimating the life of TFT (b) using the result for TFT (a) obtained by the procedure in FIG. 14. More specifically, using threshold voltage shift amounts ΔV [0105] In the following, a method of setting the tolerant amount of threshold voltage shift ΔV [0106] In FIG. 16, one example of a memory cell in an SRAM is illustrated in an equivalent circuit diagram. The memory cell in the SRAM stores data by a flipflop including two driver transistors [0107] Such shift of threshold voltage V [0108] Now, the operation of a memory cell when power supply voltage V [0109] Herein, the OFF current of driver transistor [0110] Driving of an SRAM at low voltage has been described by referring to the case in which power supply voltage V [0111] It is assumed that at a minimum voltage which guarantees data holding (1.5V in 1M-4M bit class SRAMS) increase of the OFF current of a driver transistor due to increase of the potential of L node is tolerated up to about ten times, and that data is not inverted unless the ON current of the TFT at the minimum voltage is at most ten times as large as the OFF current of the driver transistor. [0112]FIG. 19 is a graph showing shift in the I [0113] In this case, if the threshold voltage V Δ [0114] Herein, V [0115] Now, a method of determining the tolerant amount of shift of threshold voltage ΔV [0116] When an SRAM is driven at a high speed, it will not be operated with low voltage and therefore the graph in FIG. 19 is of no use. [0117]FIG. 20 is a graph showing change of the I [0118] Accordingly, if the threshold voltage V Δ [0119] The tolerant amount of shift of threshold voltage ΔV [0120] In FIG. 20, the intersection of initial characteristic Δ [0121] Substituting the value of tolerant threshold voltage shift amount ΔV [0122] SRAMs undergo burn-in tests before being marketed. The burn-in test is to generate defects in unstable semiconductor circuit chips by maintaining semiconductor circuit chips at a high temperature and high voltage, so that such semiconductor chips including the defects are avoided from being marketed. [0123] Burn-in tests include a static burn-in test and a dynamic burn-in test. In the dynamic burn-in test, data is periodically rewritten at a high temperature and under high voltage. On the other hand, in the static burn-in test, data may be maintained as constant. [0124] For ease of representation, in the case of the static burn-in test, TFT on the node side at which H is written attains a −BT stress state, and therefore its threshold voltage V [0125]FIG. 21 is a graph showing change of the I [0126] However, since only the TFT on the H node side attains a −BT stress state, the threshold voltage V [0127] In addition, in the case of a dynamic burn-in test, since H and L sides are exchanged alternately, for one TFT, only time periods when it attains H needs to be multiplied to set initial threshold voltage V [0128] Now, a TFT with a gate oxide film having a thickness permitting implementation of a maximum −BT stress life will be described. Under −BT stress, positive fixed charge ≡Si [0129] where ε [0130] Accordingly, as the thickness t [0131] Using expression (12), expressions (6) and (8) are transformed into the following expressions (6 [0132] It can be seen that with temperature T and V [0133] More specifically, when expression (8 [0134] This means that the −BT stress life τ is maximized when the gate insulating film has this thickness. [0135] For example, for a TFT at V [0136] In the above description, the operation temperature of the TFT means the temperature of the TFT itself. Stated differently, even for a TFT operated in a room temperature atmosphere, if the semiconductor chip generates heat and the temperature of the TFT itself is 77° C., the operation temperature of the TFT is 77° C. [0137] As described above, according to the present invention, the threshold voltage shift amount and life of a polysilicon TFT due to −BT stress are estimated using expressions based on the mechanism of threshold voltage shift, and therefore an accurate and efficient method of evaluating the reliability of a TFT can be provided. [0138] Furthermore, employing the method of reliability evaluation according to the present invention, a TFT with threshold voltage V [0139] Furthermore, employing the method of reliability evaluation according to the present invention, a TFT including a gate insulating film having a thickness achieving a maximum useful life for each −BT stress condition in which the TFT is used can be provided. [0140] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims. Referenced by
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