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Publication numberUS20010051413 A1
Publication typeApplication
Application numberUS 09/796,116
Publication dateDec 13, 2001
Filing dateFeb 28, 2001
Priority dateMar 6, 2000
Also published asEP1132955A1, US6436782
Publication number09796116, 796116, US 2001/0051413 A1, US 2001/051413 A1, US 20010051413 A1, US 20010051413A1, US 2001051413 A1, US 2001051413A1, US-A1-20010051413, US-A1-2001051413, US2001/0051413A1, US2001/051413A1, US20010051413 A1, US20010051413A1, US2001051413 A1, US2001051413A1
InventorsAlain Chantre, Michel Marty, Helene Baudry
Original AssigneeStmicroelectronics S.A.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Process for fabricating a self-aligned double-polysilicon bipolar transistor
US 20010051413 A1
Abstract
The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.
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Claims(9)
That which is claimed is:
1. Process for fabricating a self-aligned double-polysilicon bipolar transistor, characterized in that it comprises the following steps:
(a) the production of a silicon substrate (1) comprising a collector region of a first conductivity type and a base region (2) of a second conductivity type the opposite of the first;
(b) the formation on the base region (2) of an interlayer (3) made of Ge and/or SiGe of the second conductivity type;
(c) the formation over a predetermined zone of the interlayer (3) of an etch-stop film (10);
(d) the formation on the interlayer (3) and the etch-stop film (10) of a first thick layer (4) made of poly-Si of the second conductivity type;
(e) the formation on the first poly-Si layer (4) of an outer layer of a dielectric material;
(f) the etching, through an appropriate mask, of the outer layer of a dielectric material and of the first thick poly-Si layer (4) stopping on the etch-stop film (10), then removal of the corresponding part of the etch-stop film;
(g) the selective removal of the Ge and/or SiGe layer in order to form an emitter window (6) having a bottom formed by an exposed zone of the base region (2) and of the sidewalls;
(h) the formation of a passivation layer (7) on the sidewalls of the emitter window (6);
(i) the formation of a second poly-Si layer of the first conductivity type, so as to fill the emitter window (6) and cover the outer dielectric material layer (5); and
(j) the etching, through an appropriate mask, of the second poly-Si layer of the first conductivity type in order to form an emitter region (8) of the desired geometry and size.
2. Process according to
claim 1
, characterized in that the stop film is a film made of dielectric material
3. Process according to
claim 2
, characterized in that the stop film is a film made of SiO2 or Si3N4.
4. Process according to any one of
claims 1
to
3
, characterized in that the stop film has a thickness of 10 to 50 nm.
5. Process according to any one of
claims 1
to
4
, characterized in that the Ge and/or SiGe layer (3) has a thickness of 20 to 125 nm, and preferably of about 50 nm.
6. Process according to any one of the preceding claims, characterized in that the first thick poly-Si layer (4) of the second conductivity type has a thickness of 50 to 250 nm, and preferably of 125 to 250 nm.
7. Process according to any one of the preceding claims, characterized in that the SiGe alloy contains from 10 to 50 at % germanium.
8. Process according to any one of the preceding claims, characterized in that the outer layer of dielectric material (5) is made of SiO2.
9. Process according to any one of the preceding claims, characterized in that the passivation layer (7) is made of SiO2 or Si3N4.
Description
FIELD OF THE INVENTION

[0001] The present invention relates in general to the fabrication of double-polysilicon bipolar transistors (i.e. extrinsic base and emitter made of polycrystalline silicon (poly-Si), in contrast to the single-polysilicon bipolar transistors with only the emitter made of poly-Si). More particularly, the present invention relates to a process for fabricating a self-aligned double-polysilicon bipolar transistor having an epitaxially-grown base.

BACKGROUND OF THE INVENTION

[0002] The conventional process for fabricating a double-polysilicon bipolar transistor includes, as shown in FIG. 1a, forming, in or on a semiconductor substrate 1 having a first conductivity type (for example a substrate made of single-crystal silicon having an n-type conductivity), a region 2 having a second conductivity type the opposite of the first (for example a region made of silicon and/or SiGe alloy of p-type conductivity). Thus, a base region 2 of the second conductivity type (p) and a collector region underlying the base region 2 and of the first conductivity type (n) are formed in the substrate 1. The next step includes forming, on the base region 2, a first thick layer 3 made of poly-Si of the second conductivity type (for example, a heavily-doped p+ layer), and, on this thick poly-Si layer 3, a thick layer of a dielectric material 4 such as SiO2 or an SiO2/Si3N4 bilayer.

[0003] An emitter window 5 is then formed by conventional photolithographic etching of the dielectric material layer 4 and the thick poly-Si layer 3 down to the base region 2 (FIG. 1b). As shown in FIG. 1c, after depositing a passivation layer 6 on the sidewalls of the window 5, the window 5 is filled and the dielectric material layer 4 is coated with a second poly-Si layer of the first conductivity type (for example heavily doped with n+) to form, after masking and conventional etching, an emitter region 7 made of poly-Si of desired geometry and size. The rest of the first thick p+-doped poly-Si layer forms the extrinsic base region of the transistor, whereas the remaining part of the thin silicon or SiGe alloy layer 2 located under the emitter region 7, forms the intrinsic base region of the bipolar transistor.

[0004] The doping of the various layers can be carried out conventionally, either in situ, i.e. during the formation of the layers, or after formation of the layers by ion implantation. Also in a conventional manner, it is possible for the various doped layers to undergo activation annealing of the dopants. Furthermore, the base region 2 may be conventionally formed from a single-crystal SiGe/Si bilayer.

[0005] The etching of the window 5 usually comprises a first conventional step of etching the layer of dielectric material 4, for example SiO2, stopping on the first poly-Si layer 3, then a second step which is also conventional etching of the first thick poly-Si layer 3 stopping at the base region 2 (overetching). This overetching may, in practice, result in removing the active base region of the transistor, therefore leading to a defective device.

SUMMARY OF THE INVENTION

[0006] An object of the invention is to provide a process for fabricating a double-polysilicon bipolar transistor, while avoiding any risk of overetching the active base region of the transistor.

[0007] It has been found, according to the invention, that it is possible to avoid any risk of overetching the active base region of a double-polysilicon bipolar transistor during its fabrication using a process comprising: (a) the production of a substrate comprising a collector region of a first conductivity type and a base region of a second conductivity type the opposite of the first; (b) the formation on the base region of an interlayer made of germanium and/or SiGe alloy (preferably polycrystalline) of the second conductivity type; (c) the formation over a predetermined zone of the Ge and/or SiGe alloy interlayer of an etch-stop film; (d) the formation on the interlayer and the etch-stop film of a first thick layer made of polycrystalline silicone (poly-Si) of the second conductivity type; (e) the formation on the first poly-Si layer of an outer layer of a dielectric material; (f) the etching, through an appropriate mask, of a window preform in the layer of dielectric material and the first thick polysilicon layer, stopping on the etch-stop film, then removal in the window preform of the etch-stop film; (g) the selective removal in the window preform of the Ge and/or SiGe alloy layer in order to form an emitter window having a bottom formed by an exposed zone of the base region and of the sidewalls; (h) the formation of a passivation layer on the sidewalls of the emitter window; (i) the formation of a second polysilicon layer of the first conductivity type, so as to fill the emitter window and cover the outer dielectric material layer; and (j) the etching of the second polysilicon layer of the first conductivity type in order to form an emitter region of the desired geometry and size.

[0008] The processes of forming Ge and/or SiGe alloy layers are well known and it is possible to use, for example, conventional chemical vapor deposition (CVD) processes. Similarly, polysilicon layers may be formed by any conventional process such as CVD and plasma-enhanced chemical vapor deposition (PECVD). The formation of layers made of dielectric material, for example SiO2 or Si3N4, such as the layer of step (c) and the passivation layer of the sidewalls of the emitter window, is also conventional in bipolar transistor technology.

[0009] The Ge and/or SiGe interlayer of step (d) has a thickness which usually varies from 2 to 125 nm and is preferably about 2 to 40 nm. The first polysilicon layer usually has a thickness of 50 to 250 nm, and preferably of 125 nm to 250 nm. The doping of these layers is carried out conventionally, either by in situ doping with a dopant of appropriate conductivity, or, after deposition of the layers, by conventional ion implantation of a dopant of appropriate conductivity. Conventionally, annealing steps may be carried out in order to activate the dopants.

[0010] SiGe alloys are well known. Among these alloys, mention may be made of Si1-xGex where alloys 0<x<1 and Si1-x-yGexCy where alloys 0<x≦0.95 and 0<y≦0.05. Preferably, SiGe alloys with a relatively high germanium content, usually 10 to 50% at germanium, will be used, since the SiGe alloy etching selectivity with respect to silicon and to SiO2 increases with the germanium content of the alloy.

[0011] The masking and the etching of the various layers to form the emitter window preform may be done by any process, such as a isotropic etching by dry means, for example by plasma. The selective removal of the Ge or the SiGe film may be carried out conventionally via a chemical oxidant, for example with a 40 ml 70% HNO3+20 ml H2O2+5 ml 0.5% HF solution or by isotropic plasma etching. This removal is controlled so as to take off that part of the poly-Ge or poly-SiGe layer which is located at the bottom of the emitter window preform and possibly so as to etch a small fraction of this layer under the first polysilicon layer.

[0012] The presence of the etch-stop film, for example made of SiO2, means that the etching of the first polysilicon layer, which is usually by plasma etching, will definitely stop at the stop film. This is because the plasma etching of polysilicon is selective with respect to SiO2 and an end-of-etching detection signal can be used conventionally. So, while the first polysilicon layer is being etched, the interlayer definitely cannot be etched to such an extent that this layer is pierced, with consequent etching of or damage to the base region. The etching of the stop film and consequently of a fraction of the interlayer may then be carried out without risk of damaging the surface of the base region, by using known etching techniques which are gentler and more selective.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The rest of the description refers to the appended figures:

[0014]FIGS. 1a to 1 c are schematic cross-sectional views of the main steps of a process for fabricating a double-polysilicon bipolar transistor, according to the prior art; and

[0015]FIGS. 2a to 2 e are schematic cross-sectional views of the main steps of a first embodiment of the process according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] One embodiment of a double-polysilicon bipolar transistor with an npn structure, in accordance with the process of the invention, will now be described with reference to FIGS. 2a to 2 e. Of course, the process may also apply to a bipolar transistor with a pnp structure.

[0017] As in the process of the prior art, the process starts by producing an n-doped silicon substrate 1 comprising a p-doped base region 2. This base region may be formed by appropriate doping of the substrate region, immediately subjacent to a main surface of the substrate 1, that part of the substrate 1 which remains n-doped then forming a collector region. This base region may also be produced by forming an appropriately doped SiGe/Si bilayer or SiGe layer on a main surface of the substrate.

[0018] A layer 3 made of Ge or p+-doped SiGe alloy is then formed over the base region 2. A stop film 10, for example made of SiO2 or Si3N4, is formed in a manner known per se over a predetermined zone of the Ge or SiGe layer 3, followed by a thick p+-doped polycrystalline silicon layer, and finally an SiO2 layer 5. Usually, the stop film 10 has a thickness of 10 to 50 nm. After masking (not shown), the SiO2 layer 5 and the poly-Si layer 4 are etched, for example by anisotropic dry plasma etching, down to the stop film 10 in order to form an emitter window preform 6 (FIG. 2b).

[0019] During this etching of the poly-Si layer 4, as shown in FIG. 2b, it is certain that the entire poly-Si layer 4 has been etched without any risk of the interlayer, and subsequently the base region 2, being etched. The etching of the stop film 10 and the selective etching of the Ge or SiGe layer 3 are then carried out to expose the surface of the base region 2 and thus complete the opening of the emitter window 6, as shown in FIG. 2c. This selective removal of the Ge or SiGe layer 3 usually leads to slight etching of the layer 3 under the remaining parts 10 a, 10 b of the stop film and the poly-Si layer 4 on each side on the sidewalls of the emitter window 6.

[0020] Next, the process continues conventionally with the formation on the sidewalls of the emitter window 6 of a passivation layer 7 made of dielectric material, for example SiO2 or Si3N4, as shown in FIG. 2d. Then a second layer of n+-doped poly-Si is formed by filling in the emitter window 6 and by covering the outer layer 5 of dielectric material which, after masking, is then conventionally etched to form the emitter region 8. The bipolar transistor may then be conventionally finished by forming contacts and depositing an encapsulation layer.

[0021] Thus, by the process of the invention, a self-aligned double-polysilicon bipolar transistor is formed without any risk of overetching the base region 2.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6472287 *Mar 6, 2002Oct 29, 2002Nec CorporationManufacturing method of semiconductor with a cleansing agent
US7091100Aug 12, 2004Aug 15, 2006Infineon Technologies AgPolysilicon bipolar transistor and method of manufacturing it
US7682985 *Mar 17, 2004Mar 23, 2010Lam Research CorporationDual doped polysilicon and silicon germanium etch
US8173511 *Oct 29, 2006May 8, 2012Nxp B.V.Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
US20100289022 *Oct 29, 2006Nov 18, 2010Nxp B.V.Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
WO2003069663A1 *Jan 23, 2003Aug 21, 2003Infineon Technologies AgPolysilicon bipolar transistor and method for producing the same
Classifications
U.S. Classification438/364, 257/E21.371
International ClassificationH01L21/331
Cooperative ClassificationH01L29/66242
European ClassificationH01L29/66M6T2H
Legal Events
DateCodeEventDescription
Jan 23, 2014FPAYFee payment
Year of fee payment: 12
Feb 18, 2010FPAYFee payment
Year of fee payment: 8
Jan 27, 2006FPAYFee payment
Year of fee payment: 4
Jul 16, 2001ASAssignment
Owner name: STMICROELECTRONICS S.A., FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANTRE, ALAIN;MARTY, MICHEL;BAUDRY, HELENE;REEL/FRAME:011986/0859
Effective date: 20010517
Owner name: STMICROELECTRONICS S.A. 29, BOULEVARD ROMAIN ROLLA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANTRE, ALAIN /AR;REEL/FRAME:011986/0859