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Publication numberUS20010052802 A1
Publication typeApplication
Application numberUS 09/475,261
Publication dateDec 20, 2001
Filing dateDec 30, 1999
Priority dateDec 30, 1999
Also published asUS6411132
Publication number09475261, 475261, US 2001/0052802 A1, US 2001/052802 A1, US 20010052802 A1, US 20010052802A1, US 2001052802 A1, US 2001052802A1, US-A1-20010052802, US-A1-2001052802, US2001/0052802A1, US2001/052802A1, US20010052802 A1, US20010052802A1, US2001052802 A1, US2001052802A1
InventorsJed Griffin
Original AssigneeJed Griffin
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Matched current differential amplifier
US 20010052802 A1
Abstract
According to an embodiment of the invention, a circuit is provided that includes a first differential set and a second differential set each having a first and a second input node and a first and a second output node. The first differential set is referenced to a first supply node, and the second differential set is referenced to a second supply node. The first input node of the first differential set is coupled to the first input node of the second differential set. The second input node of the first differential set is coupled to the second input node of the second differential set. A first load element is cross coupled between the second output node of the second differential set and the first output node of the first differential set. A second load element is cross coupled between the second output node of the first differential set and the first output node of the second differential set.
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Claims(16)
1. A circuit, comprising:
a first differential set and a second differential set each having a first and a second input node and a first and a second output node, the first differential set referenced to a first supply node and the second differential set referenced to a second supply node, the first input node of the first differential set coupled to the first input node of the second differential set, and the second input node of the first differential set coupled to the second input node of the second differential set;
a first load element cross coupled between the second output node of the second differential set and the first output node of the first differential set; and
a second load element cross coupled between the second output node of the first differential set and the first output node of the second differential set.
2. The circuit of
claim 1
, further comprising:
a gain stage coupled across the first load element and the second load element, the gain stage having a gain output node.
3. The circuit of
claim 1
, further comprising:
a first gain transistor coupled between a gain output node and the first load element; and
a second gain transistor coupled between the gain output node and the second load element.
4. The circuit of
claim 3
, wherein the first differential comprises a first complementary pair of MOSFETs, and
the second differential set comprises a second complementary pair of MOSFETs.
5. The circuit of
claim 4
, wherein the first load element is one of a passive resistor and a transistor.
6. The circuit of
claim 5
, wherein betas of the first gain transistor and the second gain transistor are matched, and
the betas of each of the first complementary pair of MOSFETs and each of the second complementary pair of MOSFETs are matched.
7. A circuit, comprising:
a first differential group and a second differential group each having a first and a second input node and a first and a second output node, the first differential group referenced to a first supply node and the second differential group referenced to a second supply node, the first input node of the first differential group coupled to the first input node of the second differential group, and the second input node of the first differential group coupled to the second input node of the second differential group;
a first load element cross coupled between the second output node of the first differential group and the first output node of the second differential group; and
a second load element cross coupled between the second output node of the second differential group and the first output node of the first differential group.
8. The circuit of
claim 7
, further comprising:
a gain stage coupled across the first load element and the second load element, the gain stage having a gain output node..
9. The circuit of
claim 7
, wherein the gain stage comprises:
a first gain transistor coupled between the gain output node and the first load element; and
a second gain transistor coupled between the gain output node and the second load element.
10. The circuit of
claim 9
, wherein the first differential group comprises a first and a second pair of complementary MOSFETs, and
the second differential group comprises a first and a second pair of complementary MOSFETs.
11. The circuit of
claim 10
, wherein the first load element and the second load element is one of a passive resistor and a transistor.
12. The circuit of
claim 10
, wherein betas of the first gain transistor and the second gain transistor are matched, and
the betas of the first pair of complementary MOSFETs of the first differential group and the betas of the second pair of complementary MOSFETs of the second differential group are matched, and
the betas of the second pair of complementary MOSFETs of the first differential group are matched to the betas of the first pair of complementary MOSFETs of the second differential group.
13. A circuit, comprising:
a first differential set and a second differential set each having a first and a second input node and a first and a second output node, the first input node of the first differential set coupled to the first input node of the second differential and the second input node of the first differential set coupled to the second input node of the second differential set;
a first load element coupled to the first output node of the first differential set and a second load element coupled to the second output node of the first differential set; and
a third load element coupled to the first output node of the second differential set and a fourth load element coupled to the second output node of the second differential set, the first load element and the third load element are referenced to a first supply node, and the second load element and the fourth load element are referenced to a second supply node.
14. The circuit of
claim 13
, wherein the first differential set is comprised of a first complementary pair of MOSFETs, and
the second differential set is comprised of a second complementary pair of MOSFETs.
15. The circuit of
claim 14
, wherein the first load element, the second load element, the third load element, and the fourth load element are one of a passive resistor and a transistor.
16. The circuit of
claim 14
, wherein betas of each of the first complementary pair of MOSFETs, and each of the second complementary pair of MOSFETs are matched.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] Embodiments of the present invention relate to differential amplifier circuits.

[0003] 2. Background

[0004] Differential amplifiers are used to amplify differential inputs, usually small signal differentials, at a given common mode of operation. Superior performance can be achieved by the differential amplifier which exhibits higher amplification that remains consistent, constant, across a wide common mode range. Typical differential amplifiers are specified as having a Common Mode input Range (CMR) in which a given differential gain is available. Also, typical differential amplifiers are specified with a Common Mode Rejection Ratio (CMRR) which denotes the inconsistent behavior of traditional differential amplifiers at different common modes. The CMRR typically represents a high differential gain (as a function of common mode) divided by the common mode gain (which varies at different common modes). To compensate for the deficiencies of limited CMR and inconsistent CMRR across the CMR, many differential amplifiers in analog and mixed-mode chips require higher voltages and inefficient increases in power to meet an adequate range of common modes for acceptable behavior. Despite an immense amount of previous efforts, traditional designs have been notoriously far from ideal, always hampered by the paradoxical bias current inherent in differential set configurations.

[0005] Conventional differential amplifiers use a bias current through a differential transistor pair. In metal oxide semiconductor (MOS) circuits, the differential pair features matched devices with resistive loading at their drains. Increased bias current yields greater differential gain as well as greater common mode gain. Thus, changing the bias current is only a limited solution to the problem of optimizing the CMRR. Increasing the common mode input voltage VCM helps reduce common mode gain, thus improving CMRR. But this means that the CMR will be constrained to the “high” side of the power supply. Thus, a wider CMR may only be obtained at the expense of a lower CMRR.

[0006] Prior differential amplifiers also have a few other limitations. Coupling a differential amplifier to a high gain stage, for instance, typically requires level shifting, thus limiting the high gain of that stage. Also the slew rate (SR) is adversely dependent upon the CMRR. That is, when the bias current is kept low for a high CMRR, the SR is decreased.

SUMMARY

[0007] According to an embodiment of the invention, a circuit is provided that includes a first differential set and a second differential set each having a first and a second input node and a first and a second output node. The first differential set is referenced to a first supply node, and the second differential set is referenced to a second supply node. The first input node of the first differential set is coupled to the first input node of the second differential set. The second input node of the first differential set is coupled to the second input node of the second differential set. A first load element is cross coupled between the second output node of the second differential set and the first output node of the first differential set. A second load element is cross coupled between the second output node of the first differential set and the first output node of the second differential set.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a circuit schematic of the present invention.

[0009]FIG. 2 is an embodiment of the present invention coupled to a gain stage.

[0010]FIG. 3 is an embodiment of the present invention for optimal gain.

[0011]FIG. 4 is an embodiment of the present invention for optimal gain coupled to a gain stage.

[0012]FIG. 5 is an embodiment of the present invention for even gain across a common mode range.

[0013]FIG. 6 is a block diagram of an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0014] Referring to the figures, exemplary embodiments of the invention will now be described. The exemplary embodiments are provided to illustrate the invention and should not be construed as limiting the scope of the invention.

[0015] An embodiment of the present invention is illustrated in FIG. 1. As can be seen in the circuit 100, there are two matched differential paths comprised of two differential sets (transistors 110, 140, and transistors 130, 160) each having two input paths and two output paths. The first differential set (transistors 110 and 140) is referenced to a first supply node, VDD. The second differential set (transistors 130 and 160) is referenced to a second supply node, VSS. A first load element 120 is coupled between transistor 110 and transistor 130. A second load element 150 is coupled between transistor 110 and transistor 130. Common mode input nodes are labeled 180 and 190. Where common input node 180 (VCM+) is the non-inverting differential input node, and common input node 190 (VCM−) is the inverting differential input node. Additionally, as illustrated in FIG. 2, a gain stage may be coupled to the circuit 100 resulting in the circuit 200 illustrated in FIG. 2. Note that the gain stage shown in FIG. 2 is an illustration of a typical gain stage, however, there are a number of gain stages which work equally well or better than the gain stage used for illustration here. The gain stage has a gain output node 270 coupled across the two load elements (load element 120 and load element 150. The matched current differential amplifier coupled to a gain stage illustrated by the circuit 200 in FIG. 2 comprises p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) 110 and 140 in the matched current differential amplifier, and transistor 285 in the gain stage. The circuit 200 is comprised of n-channel metal oxide semiconductor field effect transistors (n-MOSFETs) 130 and 160 in the matched current differential amplifier, and transistor 295 in the gain stage. The load elements 120 and 150 can be comprised of, but not limited to, transistors (for active resistors) or passive resistors.

[0016] If the betas of transistors 110, 130, 140 and 160, are matched to each other, and both the inverting differential input node 190 and the non-inverting differential node 180 are connected to the same voltage (a common mode between supply voltages VDD and VSS), then the current through transistors 110, 120, 140 and 160 is matched. The current through transistor 140 and 160 will be the same as that of the current through 110 and 130. Assuming the betas of transistors 285 and 295 are matched, then the current through transistor 285 will match the current through transistor 295. The voltage at the gain output node 270 will be midway between the supply voltages, requiring no level-shifting and thus optimal gain at the next stage.

[0017] When the non-inverting differential input node 180 (VCM+) increases to a higher voltage than that of the fixed common mode voltage at the inverting differential input node 190 (VCM−), the current I+ through load element 150 increases and the current I− through load element 120 decreases. The current through transistor 285 then mirrors the increased current I+. Correspondingly, the current through transistor 295 then mirrors the decreased current of I−. This results in a higher voltage at the gain output node 270 (VO). It follows that the voltage at VO 270 decreases upon the non-inverting differential input 180 (VCM+) decreasing below the inverting differential input node that is still fixed at a common mode. Therefore, by fixing the non-inverting input 180 (VCM+) to a common mode, VO 270 increases as VCM− 190 decreases, and VO 270 decreases as VCM− 190 increases. Since the gain output VO 270 is equally determined from current path I+ and I−, any common mode gain in the current paths I+ and I− essentially cancels.

[0018] For the embodiment when the load elements 150 and 120 are passive resistors with resistance R, and the betas of transistors 110, 130, 140, and 160 are matched to each other as the value β and 285 and 295 are likewise matched to each other, then Ad, Acm and CMRR are described by the following equations: Differential Gain ( A d ) 2 * R * 2 * I CM * β Common Mode Gain ( A cm ) 0 ( due to matched currents paths ) CMRR ( A d / A cm ) I CM β 2 ( V CM - V T ) 2

[0019] Note that the CMRR is relatively independent of the common mode, as long as ICM is kept much larger than 0 (VCM>>VT). A very high CMRR results because the common mode gain approaches zero and the differential gain can be set high as long as VCM>>VT. Because circuit 200 does not have a bias current, all of the power consumed by the circuit contributes directly to an optimal differential gain while effectively eliminating the common mode gain due to the symmetry of the inputs. Therefore, optimizing CMRR.

[0020] Also, because there is not a bias current in circuit 200, CMR is as wide as VT will allow for any given power. As the common mode voltage approaches the voltage of either supply, the differential current paths I+ and I− through 150 and 120, still detect any changes around the common mode. This stays true up until a threshold drop from the supply voltage. At this point, the matched transistors, 110, 130, 140, and 160 will enter into cutoff. The following embodiments allow for more optimal differential gain across all possible common modes by allowing ICM to be optimally set even when the common mode is at the supply voltages (making ICM independent of VT).

[0021] Another embodiment is illustrated in FIG. 3. The circuit 300 illustrated in FIG. 3, includes two matched differential paths that are comprised of two differential groups (transistors 305, 310, 350, 360 and transistors 330, 340, 370, 380) each having two input paths and two output paths. The first differential group (transistors 305, 310, 350 and 360) is referenced to a first supply node, VDD. The second differential group (transistors 330, 340, 370 and 380) is referenced to a second supply node, VSS. A first load element 320 is coupled between the transistor pair 305 and 310, and the transistor pair 330 and 340. A second load element 390 is coupled between the transistor pair 350 and 360, and the transistor pair 370 and 380. Common mode input nodes are labeled 375 and 345. Where the common mode input node 375 (VCM+) is the non-inverting differential input node, and the common mode input node 345 (VCM−) is the inverting differential input node. Additionally, as illustrated in FIG. 4, a gain stage may be coupled to the circuit 300 resulting in the circuit 400 illustrated in FIG. 4. The gain stage has a gain output node 486 coupled across the two impedance elements 320 and 390. The matched current differential amplifier coupled to a gain stage 400, shown in FIG. 4, consists of the following p-MOSFETs 305, 330, 360 and 380 in the matched current differential amplifier, and transistor 485 in the gain stage. The circuit 400 in FIG. 4 consists of the following n-MOSFETs 310, 340, 350 and 370 in the matched current differential amplifier, and transistor 495 in the gain stage. The load elements 320 and 390 can be comprised of, but not limited to, transistors (for active resistors) or passive resistors.

[0022] If the betas of transistors 305, 340, 360, and 370 are matched to each other and the betas of transistors 310, 330, 350, and 380 are matched to each other, and both the inverting differential input node 345 and the non-inverting differential node 375 are connected to the same voltage (a common mode between supply voltages VDD and VSS), then the current through the load impedances 390 and 320 are matched. The current through load impedance 390 will be the same as that of the current through load impedance 320. Assuming the betas of transistors 485 and 495 are matched, then the current through transistor 485 will match the current through transistor 495. The voltage at the gain output node 386 (VO) will be midway between the supply voltages.

[0023] The current through transistors 305, 310, 330 and 340 will be the same as that of the current through transistors 350, 360, 370 and 380. Assuming the betas of transistors 485 and 495 are matched, then the current through transistor 485 will match the current through transistor 495.

[0024] When the non-inverting differential input node 375 (VCM+) increases to a higher voltage than that of the fixed common mode voltage at the inverting differential input node 345 (VCM−), the current I+ through load element 390 increases and the current I− through load element 320 decreases. The current through transistor 485 then mirrors the increased current I+. Correspondingly, the current through transistor 495 then mirrors the decreased current of I−. This results in a higher voltage at VO 486. It follows that the voltage at VO decreases upon the non-inverting differential input 375 (VCM+) decreasing below the inverting differential input node that is still fixed at a common mode. Therefore, by fixing the non-inverting input VCM+ to a common mode, VO increases as VCM− decreases, and VO decreases as VCM− increases. Since the gain output VO (486) is equally determined from current path I+ and I−, any common mode gain in the current paths I+ and I− essentially cancels.

[0025] For an embodiment when the load impedance elements 390 and 320 are passive resistors with resistance R, and the betas of transistors 305, 340, 360, and 370 are matched to each other as the value β and the betas of transistors 310, 330, 350, and 380 are matched to each other as the value βE, then Ad, Acm and CMRR are described by the following equations: Differential Gain ( A d ) 2 * R * 2 * I CM * β Common Mode Gain ( A cm ) 0 ( due to matched currents paths ) CMRR ( A d / A cm ) I CM β 2 ( V CM - V T ) 2 + V DD - V SS R * β E 2

[0026] Circuit 400 ensures a high current when operating at extreme common modes by sizing βE such that matched currents at the extreme common modes equals the matched currents at the center common modes. The threshold voltage drop of circuit 200 is no longer a limit. This is because even when the common mode is at the high and low supply voltages, there will be equal common mode currents flowing through load impedances 320 and 390, ensuring consistent differential gain across all common modes. Therefore, optimal performance across all possible common modes, from the lowest supply voltage to the highest is achieved.

[0027] Another embodiment is illustrated in FIG. 5. The circuit 500 illustrated in FIG. 5, includes two matched differential paths are comprised of two differential sets (transistors 520, 530, and transistors 560, 570) each having two input paths and two output paths. A first load element 510 is coupled between the first differential set and a first supply node, VDD. A second load element 540 is coupled between the first differential set and a second supply node, VSS. A third load element 550 is coupled between the second differential set and a first supply node, VDD. A fourth load element 580 is coupled between the second differential set and a second supply node, VSS. Common mode input nodes are labeled 590 and 595. Where common mode input node 590 (VCM+) is the non-inverting differential input node, and common input node 595 (VCM−) is the inverting differential input node. Additionally, a gain stage may be coupled to the circuit 500. The circuit 500 is comprised of p-MOSFETs 520 and 570, and n-MOSFETs 530 and 560. The load elements 510, 540, 550 and 580 can be comprised of, but not limited to, transistors (for active resistors) or passive resistors.

[0028] If the betas of transistors 520, 530, 560 and 570 are matched to each other, and both the inverting differential input node 595 and the non-inverting differential node 590 are connected to the same voltage (a common mode between supply voltages VDD and VSS), then the current through transistors 520, 530, 560 and 570 are matched. The current through the load impedances 510 and 540 will be the same as that of the current through load impedances 550 and 580. The current through transistors 520 and 560 will be the same as that of the current through transistors 530 and 570. When the non-inverting differential input node VCM+ (590) increases to a higher voltage than that of the fixed common mode voltage at the inverting differential input node 595 (VCM−), the current I+ increases and the current I− decreases.

[0029] For the embodiment when the load elements are passive resistors with resistance R, and the betas of transistors 520, 530, 560 and 570 are matched to each other, as the value β, then Ad, Acm and CMRR are described by the following equations: Differential Gain ( A d ) 4 * R * 2 * I CM * β 1 + 2 * I CM * β Common Mode Gain ( A cm ) 0 ( due to matched currents paths ) CMRR ( A d / A cm ) I CM β 2 ( V CM - V T ) 2 + V DD R * β E 2

[0030] The threshold voltage drop of the circuit 200 illustrated in FIG. 2 is also no longer a limit here. This is because even when the common mode is at the high and low supply voltages, there will be equal common mode current flowing through I+ and I−, ensuring differential gain. In this embodiment, more even, but less differential gain across all possible common modes, from the lowest supply voltage to the highest supply is achieved.

[0031] It should be noted that while the above discussion involved MOSFET transistors, bipolar junction transistors (BJTs) and junction field effect transistors (JFETs) can also be implemented with similar results. The embodiments of the invention described above are, of course, subject to other variations in structure and implementation. For instance, additional devices may be inserted between various nodes, terminals, and devices in the above embodiments without materially changing their overall function. For example, voltage drops may be introduced by resistors, diodes, or transistors configured as diodes, to change various voltage levels, or buffers may be inserted between various nodes, terminals, and devices. In general, the scope of the invention should be determined not by the embodiments illustrated but by the appended claims and their legal equivalents.

Classifications
U.S. Classification327/65
International ClassificationH03F3/45
Cooperative ClassificationH03F3/45264
European ClassificationH03F3/45S1B7
Legal Events
DateCodeEventDescription
Nov 27, 2013FPAYFee payment
Year of fee payment: 12
Dec 16, 2009FPAYFee payment
Year of fee payment: 8
Dec 27, 2005FPAYFee payment
Year of fee payment: 4
Dec 17, 2002CCCertificate of correction
Apr 10, 2000ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GRIFFIN, JED;REEL/FRAME:010694/0266
Effective date: 20000211
Owner name: INTEL CORPORATION 2200 MISSION COLLEGE BOULEVARD S